Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. The semiconductor device comprises a first dielectric layer, an etching stop layer located on the first dielectric layer, and a second dielectric layer located on the etching stop layer, an optical modulator structure in the first dielectric layer and a modulation heater structure over the optical modulator structure and included in the second dielectric layer wherein the modulation heater structure includes a heater ring directly over the optical modulator structure and a heater pad coupled to the heater ring, wherein the thickness of the heater pad is greater than that of the heater ring. The large thickness of the heater pad provides low resistance so that current can be provided to the heater ring through the heater pad, and heat dissipation in the heater pad is reduced due to low current dissipation in the heater pad, so that the modulation heater structure can operate efficiently. The configuration consumes less current to provide heat to the optical modulator relative to other modulation heater structures.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor device, and more particularly to a semiconductor device including an optical modulator structure and a modulated heater structure. Background Art

[0002] The semiconductor device can be configured to use optical signals to perform high-speed and secure data transmission between integrated circuits and / or semiconductor dies of the semiconductor device. The optical signal can be transmitted through a waveguide in the semiconductor device. The waveguide can confine the optical signal, which can reduce optical losses and improve the propagation efficiency of the optical signal. Data can be encoded into the optical signal by modulating light into optical pulses using an optical modulator. The optical pulses are then transmitted to the waveguide to propagate to other areas of the semiconductor device. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device including a first dielectric layer, an etch stop layer located above the first dielectric layer, a second dielectric layer located above the etch stop layer, an optical modulator structure located in the first dielectric layer, and a modulation heater structure located above the optical modulator structure and included in the second dielectric layer, wherein the modulation heater structure includes a heater ring located directly above the optical modulator structure and a heater pad coupled to the heater ring, wherein the thickness of the heater pad is greater than the thickness of the heater ring.

[0004] An embodiment of the utility model provides a semiconductor device including a first dielectric layer, an etch stop layer located on the first dielectric layer, a second dielectric layer located on the etch stop layer, an optical modulator structure located in the first dielectric layer, a modulation heater structure located above the optical modulator structure and included in the second dielectric layer, a back-end process internal wiring layer, and a back-end process extension layer. The modulation heater structure includes a heater ring located directly above the optical modulator structure, a heater pad coupled to the heater ring, and a contact area coupled to the heater pad. The back-end process internal wiring layer is located on the contact area of ​​the modulation heater structure and coupled to the contact area, and the back-end process extension layer is located on the heater pad and coupled to the heater pad.

[0005] Based on the above, a heater ring of a modulated heater structure may have a first thickness. A heater pad of the modulated heater structure configured to provide current to the heater ring may have a second thickness that is greater than the first thickness. The smaller thickness of the heater ring of the modulated heater structure provides a high resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat, which heat can be provided to stabilize the operating temperature of the optical modulator structure. The larger thickness of the heater pad provides a low resistance in the second region, which enables current to be efficiently provided to the heater ring through the heater pad, while heat dissipation in the heater pad is reduced due to the lower current dissipation in the heater pad. This enables the modulated heater structure to operate more efficiently and consume less current to provide a similar amount of heat to the optical modulator relative to other modulated heater structure configurations.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described in embodiments of the present invention may be implemented.

[0008] Figure 2 is a diagram of an exemplary semiconductor device described in an embodiment of the present invention.

[0009] Figure 3A and Figure 3B An exemplary implementation of one or more portions of the semiconductor device described in the embodiments of the present invention is shown.

[0010] Figures 4A to 4AA FIG. 2 is a diagram of an exemplary implementation of a semiconductor device described in an embodiment of the present invention.

[0011] Figure 5 is a diagram of an exemplary semiconductor device described in an embodiment of the present invention.

[0012] FIG. 6A to FIG. 6U FIG. 2 is a diagram of an exemplary implementation of a semiconductor device described in an embodiment of the present invention.

[0013] Figure 7 is a diagram of exemplary components of the apparatus described in the embodiments of the present invention.

[0014] Figure 8 is a flow chart of an exemplary process associated with forming the semiconductor device described in the embodiments of the present invention.

[0015] Description of Reference Numerals

[0016] 100: environment; 102: deposition tool; 104: exposure tool; 106: development tool; 108: etching tool; 110: planarization tool; 112: plating tool; 114: ion implantation tool; 116: wafer / die transport tool; 200, 500: semiconductor device; 202, 502: optical modulator structure; 204, 504: waveguide structure; 206, 506: modulated heater structure; 208, 508: back-end-of-line (BEOL) interconnect layer; 210a: lower part; 210b: Upper portion; 212: overhanging section; 214, 514: heater ring; 216a, 216b: connection area; 218a, 218b, 518a, 518b: heater pad; 220a, 220b, 520a, 520b: contact area; 222, 224, 228, 522, 524, 528: dielectric layer; 226, 526: etch stop layer; 300, 310, 400, 600: implementation scheme; 402, 602: substrate; 404, 604: semiconductor substrate; 406, 60 6: dielectric layer; 408, 608: semiconductor layer; 410, 610: contact structure; 412, 612: etch stop layer; 414, 614: silicide layer; 416, 420, 422, 616, 620: shielding layer; 418, 424, 618, 622: groove; 418a, 418b: part; 426, 624: conductive material layer; 428, 626: interconnect structure; 430, 432, 434, 436, 628, 630, 632, 634: back-end process (BEO) L) Internal wiring layer; 510: extension layer; 510a: main part; 510b: extension part; 512: extension section; 700: device; 710: bus; 720: processor; 730: memory; 740: input component; 750: output component; 760: communication component; 800: process; 810, 820, 830, 840: blocks; AA: line / cross-section line; BB, CC: cross-section line; D1, D2, D3, D4, D5, D6, D7, D8: size; x, y, z: direction. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0019] In some cases, a photonic integrated circuit including a waveguide and an optical modulator may be included in a dielectric region of a semiconductor device. The dielectric region may be located above a substrate of the semiconductor device. The resonant wavelength of the optical modulator may be sensitive to variations in process and operating temperature. Therefore, a modulated heater structure may be included in the dielectric region to stabilize the operating temperature of the optical modulator, thereby stabilizing the operating performance of the optical modulator.

[0020] The modulated heater structure may include a heater ring located directly above the optical modulator. The heater ring may be configured to receive an electric current and dissipate the electric current, thereby generating heat for heating the optical modulator. The heater ring may be coupled to a heater pad of the modulated heater structure. The heater pad may be configured to provide electric current to the heater ring (e.g., from one or more back end of line (BEOL) internal connections). Some of the electric current may also be dissipated in the heater pad, which may reduce the operating efficiency of the modulated heater structure. The current dissipated in the heater pad may result in a reduction in the current provided to the heater ring. Therefore, the more current dissipated in the heater pad, the lower the operating efficiency of the modulated heater structure.

[0021] In some implementations described in the embodiments of the present invention, a waveguide structure and an optical modulator structure of a semiconductor photonic device are included in a dielectric region located above a substrate of the semiconductor photonic device. A modulated heater structure is included above the optical modulator structure to stabilize the operation of the optical modulator structure during operation by heating the optical modulator structure to a stable temperature.

[0022] The modulated heater structure may include multiple zones with different thicknesses. For example, a heater ring of the modulated heater structure located directly above the optical modulator structure may have a first thickness. A heater pad of the modulated heater structure configured to provide current to the heater ring may have a second thickness that is greater than the first thickness. The smaller thickness of the heater ring of the modulated heater structure provides a high resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat, which can be provided to stabilize the operating temperature of the optical modulator structure. The larger thickness of the heater pad provides a low resistance in the second zone, which enables current to be efficiently provided to the heater ring through the heater pad, while heat dissipation in the heater pad is reduced due to the lower current dissipation in the heater pad. This enables the modulated heater structure to operate more efficiently and consume less current to provide a similar amount of heat to the optical modulator relative to other modulated heater structure configurations.

[0023] Figure 1 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described in embodiments of the present invention may be implemented. Figure 1 As shown in , environment 100 may include multiple semiconductor processing tools (102-114) and a wafer / die transport tool 116. The multiple semiconductor processing tools (102-114) may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0024] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, example environment 100 includes multiple different types of deposition tools 102. "Deposition tool 102" as used in embodiments of the present invention may refer to one or more deposition tools 102, one or more of the same type of deposition tools 102, and / or one or more different types of deposition tools 102, among other examples.

[0025] The exposure tool 104 is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep ultraviolet light source, an extreme ultraviolet (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 may expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0026] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developer tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0027] The etching tool 108 is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or similar etching tools. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions in an isotropic manner or in a directional manner.

[0028] The planarization tool 110 is a semiconductor processing tool that is capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and abrasive polishing) to grind or planarize the surface of a semiconductor device. The planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and the polishing pad and the semiconductor device may be fixed in position by a retaining ring. The dynamic polishing head may rotate on different rotation axes to remove material and flatten any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0029] The plating tool 112 is a semiconductor processing tool that is capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0030] The ion implantation tool 114 is a semiconductor processing tool that is capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate.

[0031] The wafer / die transport tool 116 may be included in a cluster tool or another type of tool including multiple processing chambers and may be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, between a processing chamber and a buffer area, between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transport tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidations, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0032] In some implementations, one or more of the semiconductor processing tools (102 to 114) may implement one or more semiconductor processing operations described in the embodiments of the present invention. For example, one or more of the semiconductor processing tools (102 to 114) may form an optical modulator structure and a waveguide structure adjacent to the optical modulator structure in a semiconductor layer located above a first dielectric layer; form an etch stop layer above the first dielectric layer, above the optical modulator structure, and above the waveguide structure; form a second dielectric layer above the etch stop layer; and form a modulated heater structure in the second dielectric layer, wherein a heater ring of the modulated heater structure is formed above the optical modulator structure, wherein heater pads of the modulated heater structure coupled to the heater ring extend laterally outward from the heater ring, and wherein a thickness of the heater pads is greater than a thickness of the heater ring. One or more of the semiconductor processing tools (102 to 114) may implement, for example, a combination of Figures 4A to 4AA , FIG. 6A to FIG. 6U and / or Figure 8 Other semiconductor processing operations and other examples are described in the embodiments of the present invention.

[0033] Figure 1 The number and arrangement of devices shown in are provided as one or more examples. In practice, there may be Figure 1 The device shown in the additional device, less device, and Figure 1 In addition, Figure 1 Two or more of the devices shown in may be implemented in a single device, or Figure 1 The single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0034] Figure 2 2 is a diagram of an exemplary semiconductor device 200 described in an embodiment of the present invention. The semiconductor device 200 may include a semiconductor photonic device and / or another type of semiconductor device including one or more photonic integrated circuits.

[0035] Figure 2A top view of a semiconductor device 200 and a corresponding cross-sectional view along line AA in the top view are shown. The semiconductor device 200 may be configured to use optical signals for high-speed and secure data transmission between integrated circuits and / or semiconductor dies of the semiconductor device 200. Therefore, the semiconductor device 200 may include an optical modulator structure 202 and one or more waveguide structures 204. The optical signal may be transmitted through the waveguide structure 204 in the semiconductor device 200. The waveguide structure 204 is capable of confining the optical signal, which may reduce optical losses and improve the propagation efficiency of the optical signal. Data may be encoded into the optical signal by modulating light into optical pulses in the optical modulator structure 202. The optical pulses are then transmitted to the waveguide structure 204 to propagate to other areas of the semiconductor device 200. The optical modulator structure 202 and the waveguide structure 204 may be adjacent and / or side-by-side in the semiconductor device 200 to enable coupling of the optical signal from the optical modulator structure 202 to the waveguide structure 204 (and vice versa for demodulation of the optical signal).

[0036] The optical modulator structure 202 may include an approximately circular shape and may be referred to as a micro-ring modulator (MRM). The optical modulator structure 202 may be used as a resonant chamber and may modulate an input signal from a light source to generate an optical signal (e.g., a modulated light signal). The optical signal may be coupled to the waveguide structure 204 based on the optical signal reaching a threshold modulation frequency and / or based on the optical signal reaching a threshold signal intensity. The waveguide structure 204 may facilitate propagation of the optical signal to another device or region in the semiconductor device 200. In some implementations, the optical modulator structure 202 includes one or more doped regions. The one or more doped regions may facilitate and / or promote the flow of electrons in the optical modulator structure 202 and / or may facilitate and / or promote the formation of an optical signal from an electrical signal. For example, the one or more doped regions may be configured as a pn junction, which is configured to generate an optical signal.

[0037] like Figure 2As further shown in FIG. 2 , the semiconductor device 200 may include a modulated heater structure 206. The modulated heater structure 206 may be included above the optical modulator structure 202 and / or above the waveguide structure 204. As described above, the resonant wavelength of the optical modulator structure 202 may be sensitive to changes in operating temperature. Therefore, the modulated heater structure 206 may be configured to stabilize the operating temperature of the optical modulator structure 202 during operation of the optical modulator structure 202. Specifically, the modulated heater structure 206 may heat the optical modulator structure 202 (e.g., may increase the temperature of the optical modulator structure 202) to an operating temperature set point or to a temperature within an operating temperature range, thereby stabilizing the operating performance of the optical modulator structure 202. The modulated heater structure 206 may include tungsten (W), titanium nitride (TiN), and / or another material capable of radiating heat toward the optical modulator structure 202.

[0038] The modulated heater structure 206 may be electrically and / or physically coupled to one or more back-end-of-line (BEOL) interconnect layers 208. The BEOL interconnect layers 208 may be configured to provide current to the modulated heater structure 206. The BEOL interconnect layers 208 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), among other examples of conductive materials. The BEOL interconnect layers 208 may each include vias, trenches, contact plugs, and / or another type of metallization layer.

[0039] As along Figure 2 As further shown in the cross-sectional view of the semiconductor device 200 along line AA in FIG. 2 , the modulated heater structure 206 may include a lower portion 210 a (e.g., a first heater portion) and an upper portion 210 b (e.g., a second heater portion) located above the lower portion. The lower portion 210 a and the upper portion 210 b may be formed as a single body (e.g., in the same set of one or more deposition operations) or may be formed in separate sets of one or more deposition operations such that a seam or material interface is located between the lower portion 210 a and the upper portion 210 b.

[0040] The upper portion 210b may extend laterally outward from an end or sidewall of the lower portion 210a such that the modulated heater structure 206 includes an overhanging section 212 (see Figure 4V). The overhang section 212 forms a stepped inner end portion of the modulation heater structure 206. The overhang section 212 may be located above and / or on the optical modulator structure 202 and the waveguide structure 204. At least a portion of the overhang section 212 may correspond to a heater ring 214 located directly above the optical modulator structure 202. Therefore, the heater ring 214 may include only the upper portion 210b of the modulation heater structure 206. The overhang section 212 enables the heater ring 214 to have a smaller thickness than other portions of the modulation heater structure 206, including both the lower portion 210a and the upper portion 210b. The smaller thickness of the heater ring 214 enables the heater ring 214 to heat quickly and efficiently to provide heat to the optical modulator structure 202.

[0041] The optical modulator structure 202 may further include: connection areas 216a and 216b electrically and / or physically coupled to opposite sides of the heater ring 214, heater pads 218a and 218b electrically and / or physically coupled to the connection areas 216a and 216b, respectively, and contact areas 220a and 220b electrically and / or physically coupled to the heater pads 218a and 218b, respectively. The heater pad 218a may couple the connection area 216a with the contact area 220a, and the heater pad 218b may couple the connection area 216b with the contact area 220b. The connection area 216a may couple the heater ring 214 with the heater pad 218a, and the connection area 216b may couple the heater ring 214 with the heater pad 218b. The connection regions 216a and 216b, heater pads 218a and 218b, and contact regions 220a and 220b are located on opposite sides of the heater ring 214 so that the heater ring 214 can be heated evenly to provide uniform heat distribution across the optical modulator structure 202. However, other configurations of connection structures, heater pads, and / or contact regions are also within the scope of embodiments of the present invention.

[0042] The connection area 216a, the heater pad 218a, and the contact area 220a may enable current or another type of electrical input to be provided from the BEOL intra-connection layer 208 to the heater ring 214 via the contact area 220a, the heater pad 218a, and the connection area 216a. Similarly, the connection area 216b, the heater pad 218b, and the contact area 220b may enable current or another type of electrical input to be provided from another BEOL intra-connection layer 208 to the heater ring 214 via the contact area 220b, the heater pad 218b, and the connection area 216b.

[0043] The heater pads 218a and / or 218b may include the lower portion 210a and the upper portion 210b of the modulated heater structure 206. Therefore, the thickness of the heater pads 218a and / or 218b may be greater than the thickness of the heater ring 214. Figure 2 In the cross-sectional view along line AA in FIG. 2 , the bottom surface of the heater pads 218 a and / or 218 b may be closer to the etch stop layer 226 than the bottom surface of the heater ring 214 due to the greater thickness of the heater pads 218 a and / or 218 b and due to the fact that the top surface of the heater ring 214 and the top surface of the heater pads 218 a and / or 218 b may be approximately coplanar in the semiconductor device 200. The greater thickness of the heater pads 218 a and / or 218 b makes the resistance in the heater pads 218 a and / or 218 b smaller than the resistance in the heater ring 214. This enables a large amount of current to be provided to the heater ring 214 through the heater pads 218 a and / or 218 b while the heat dissipation in the heater pads 218 a and / or 218 b is less than the heat dissipation in the heater ring 214. In this way, relative to a single thickness modulated heater structure, the larger thickness of the heater pads 218a and / or 218b and the smaller thickness of the heater ring 214 will improve the operating efficiency of the modulated heater structure 206 (for example, due to reduced heat dissipation in the heater pads 218a and / or 218b and increased heat dissipation in the heater ring 214).

[0044] The heater pads 218a and / or 218b may be positioned such that the heater pads 218a and / or 218b are not located directly above the optical modulator structure 202 and / or the waveguide structure 204. This instead enables the heater ring 214 to be located directly above the optical modulator structure 202 and / or the waveguide structure 204, thereby enabling the optical modulator structure 202 to be heated utilizing more efficient heat dissipation of the heater ring 214 (e.g., relative to the heater pads 218a and / or 218b).

[0045] The heater ring 214 may include a ring structure in a top view of the semiconductor device 200 and / or may be substantially conformal to the top view shape of the optical modulator structure 202. The top view shape of the heater pad 218a (and / or similarly for the heater pad 218b) may taper between the contact region 220a (and / or similarly for the contact region 220b) and the connection region 216a (and / or similarly for the connection region 216b). The tapered top view shape of the heater pad 218a (and / or similarly for the heater pad 218b) provides low resistance for a large amount of current to flow through the heater pad 218a (and / or similarly for the heater pad 218b) and enables the current to be concentrated toward the heater ring 214 via the connection region 216a (and / or similarly for the connection region 216b). The heater pad 218a (and / or similarly for the heater pad 218b) may be tapered in a first direction (e.g., x-direction) such that the top-view width of the heater pad 218a (and / or similarly for the heater pad 218b) decreases in a second direction (e.g., y-direction) toward the connection region 216a (and / or similarly for the connection region 216b). The heater pad 218a (and / or similarly for the heater pad 218b) may further include a plurality of members extending in a second direction (e.g., y-direction) approximately perpendicular to the first direction (e.g., x-direction) in a top view. The members may be coupled to the BEOL interconnect layer 208 at a first end and may be coupled to a V-shaped portion of the heater pad 218a (and / or similarly for the heater pad 218b) at a second end opposite to the first end.

[0046] like Figure 2 As further shown in FIG. 1 , the modulated heater structure 206 may include one or more dimensions, such as dimension D1, dimension D2, dimension D3, and / or dimension D4, among other examples. Dimension D1 may correspond to a cross-sectional thickness (e.g., z-direction thickness) of an upper portion 210b of the modulated heater structure 206. Further, dimension D1 may correspond to a cross-sectional thickness (e.g., z-direction thickness) of a heater ring 214. In some embodiments, dimension D1 is included within a range of approximately 80 nanometers to approximately 240 nanometers. Values ​​less than approximately 80 nanometers for dimension D1 may result in uneven heating of the optical modulator structure 202 due to variations in the process of forming the heater ring 214. Values ​​greater than approximately 240 nanometers for dimension D1 may result in insufficient resistance in the heater ring 214, and thus the heater ring 214 may not adequately heat the optical modulator structure 202. However, ranges other than approximately 80 nanometers to approximately 240 nanometers for dimension D1 may be used and are within the scope of embodiments of the present invention.

[0047] Dimension D2 can correspond to the cross-sectional thickness (e.g., z-direction thickness) of the lower portion 210a of the modulated heater structure 206. In some implementations, dimension D2 is included in a range between approximately 0.5 times dimension D1 to approximately 1.5 times dimension D1 to achieve sufficiently low resistance in the heater pads 218a and / or 218b, which enables high energy efficiency to be achieved for the modulated heater structure 206. However, ranges for dimension D2 other than approximately 0.5 times dimension D1 to approximately 1.5 times dimension D1 can be used and are within the scope of embodiments of the present invention.

[0048] Dimension D3 may correspond to a cross-sectional thickness (e.g., z-direction thickness) of the heater pads 218a and / or 218b of the modulated heater structure 206. Thus, dimension D3 may correspond to a combined thickness of the lower portion 210a (e.g., dimension D1) and the upper portion 210b (e.g., dimension D2) of the modulated heater structure 206. In some implementations, dimension D3 is included within a range of approximately 120 nanometers to approximately 600 nanometers to achieve sufficiently low resistance in the heater pads 218a and / or 218b, which enables high energy efficiency to be achieved for the modulated heater structure 206. However, ranges other than approximately 120 nanometers to approximately 600 nanometers for dimension D3 may be used and are within the scope of embodiments of the present invention.

[0049] Dimension D4 can correspond to the cross-sectional width (e.g., y-direction width) of the overhanging section 212 of the modulated heater structure 206. In some embodiments, dimension D4 is included in a range of approximately 0.3 microns to approximately 2 microns. Values ​​for dimension D4 less than approximately 0.3 microns may result in uneven heating of the optical modulator structure 202 due to process variations in forming the heater ring 214. Values ​​for dimension D4 greater than approximately 2 microns may result in insufficient resistance in the heater ring 214, and thus the heater ring 214 may not adequately heat the optical modulator structure 202. However, ranges other than approximately 0.3 microns to approximately 2 microns for dimension D4 may be used and are within the scope of embodiments of the present invention.

[0050] As along Figure 2As further shown in the cross-sectional view of the semiconductor device 200 along line AA in FIG. 1 , the semiconductor device 200 may include a plurality of dielectric layers, such as a dielectric layer 222, a dielectric layer 224 located above the dielectric layer 222, an etch stop layer 226 located between the dielectric layer 222 and the dielectric layer 224, and / or a dielectric layer 228 located above the dielectric layer 224. The dielectric layers 222 and 224 and the etch stop layer 226 may be included in a front end of line (FEOL) region of the semiconductor device 200. The dielectric layer 228 may be included in a BEOL region of the semiconductor device 200. The FEOL region may include active semiconductor devices or circuitry of the semiconductor device 200, such as the optical modulator structure 202. The optical modulator structure 202 and the waveguide structure 204 may be included in the dielectric layer 222, and the modulated heater structure 206 may be included in the dielectric layer 224. The BEOL region may include metallization layers of the semiconductor device 200 (eg, the BEOL interconnect layer 208 ) and may be configured for signal and / or power delivery to active semiconductor devices in the FEOL region.

[0051] The dielectric layers 222, 224, and 228 may each include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide (TESO), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide and / or another dielectric material. The etch stop layer 226 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide and / or another dielectric material.

[0052] Therefore, the semiconductor device 200 may include: a first dielectric layer (e.g., dielectric layer 222), an etch stop layer (e.g., etch stop layer 226) located on the first dielectric layer, a second dielectric layer (e.g., dielectric layer 224) located on the etch stop layer, an optical modulator structure 202 located in the first dielectric layer, and a modulated heater structure 206 located above the optical modulator structure 202 and included in the second dielectric layer. The modulated heater structure 206 may include: a heater ring 214 located directly above the optical modulator structure and heater pads 218a and / or 218b coupled to the heater ring 214, wherein the thickness (e.g., dimension D3) of the heater pads 218a and / or 218b is greater than the thickness (e.g., dimension D1) of the heater ring 214.

[0053] In addition to the cross-sectional line AA, other cross-sectional lines are also Figure 2 In the combination shown and referenced Figures 4A to 4AA Cross-sectional line AA is in a second direction (e.g., y-direction) in semiconductor device 200 and extends along modulated heater structure 206. Cross-sectional line BB is in a first direction (e.g., x-direction) in semiconductor device 200 and extends across heater ring 214 of modulated heater structure 206. Cross-sectional line CC is in a first direction (e.g., x-direction) in semiconductor device 200 and extends across heater pad 218a of modulated heater structure 206.

[0054] As mentioned above, Figure 2 are provided as examples. Other examples may be used with Figure 2 Different from what is described.

[0055] Figure 3A and Figure 3B An exemplary implementation of one or more portions of a semiconductor device 200 described in an embodiment of the present invention is shown. Figure 3A An example implementation 300 of an optical modulator structure 202 and a plurality of waveguide structures 204 located on opposite sides of the optical modulator structure 202 is shown. Figure 3A As shown in FIG. 2 , the optical modulator structure 202 may have an approximately annular body or an approximately circular body. The waveguide structure 204 may have an approximately elongated shape extending along a first direction (eg, an x-direction in the semiconductor device 200 ).

[0056] Figure 3B An example embodiment 310 of the modulated heater structure 206 is shown. Figure 3BAs shown in , the heater ring 214 may include a ring structure in a top view of the semiconductor device 200 and / or may be substantially conformal to the top view shape of the optical modulator structure 202. The top view shape of the heater pad 218a (and / or similarly for the heater pad 218b) may taper between the contact region 220a (and / or similarly for the contact region 220b) and the connection region 216a (and / or similarly for the connection region 216b). The tapered top view shape of the heater pad 218a (and / or similarly for the heater pad 218b) provides low resistance for a large amount of current to flow through the heater pad 218a (and / or similarly for the heater pad 218b) and enables the current to be concentrated toward the heater ring 214 via the connection region 216a (and / or similarly for the connection region 216b). The heater pad 218a (and / or similarly for the heater pad 218b) may be tapered in a first direction (e.g., x-direction) such that the top-view width of the heater pad 218a (and / or similarly for the heater pad 218b) decreases in a second direction (e.g., y-direction) toward the connection region 216a (and / or similarly for the connection region 216b). The heater pad 218a (and / or similarly for the heater pad 218b) may further include a plurality of members extending in a second direction (e.g., y-direction) approximately perpendicular to the first direction (e.g., x-direction) in a top view. The members may be coupled to the BEOL interconnect layer 208 at a first end and may be coupled to a V-shaped portion of the heater pad 218a (and / or similarly for the heater pad 218b) at a second end opposite to the first end.

[0057] As mentioned above, Figure 3A and Figure 3B are provided as examples. Other examples may be used with Figure 3A and Figure 3B Different from what is described.

[0058] Figures 4A to 4AA 1 is a diagram of an example implementation 400 that forms a semiconductor device 200 (or a portion of a semiconductor device 200) described in an embodiment of the present invention. In some implementations, one or more of the semiconductor processing operations described in connection with the example implementation 400 may be performed using one or more of the semiconductor processing tools (102-114) and / or by a wafer / die transport tool 116. In some implementations, one or more of the semiconductor processing operations described in connection with the example implementation 400 may be performed using another semiconductor processing tool.

[0059] Go to Figure 4A, a substrate 402 may be provided. The substrate 402 may include a silicon on insulator (SOI) substrate, the SOI substrate including a semiconductor substrate 404 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a dielectric layer 406 (e.g., a buried oxide or bottom oxide (BOX) layer and / or another type of insulator layer) located on and / or on the semiconductor substrate 404, and a semiconductor layer 408 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) located on and / or on the dielectric layer 406. Alternatively, the semiconductor substrate 404 may be provided as a semiconductor wafer, and the dielectric layer 406 may be formed on and / or on the semiconductor substrate 404 using a deposition tool 102, and the semiconductor layer 408 may be formed on and / or on the dielectric layer 406 using another deposition tool 102. The dielectric layer 406 may be formed using a deposition tool 102 using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. The semiconductor layer 408 may be formed using a deposition tool 102 using a CVD technique, a PVD technique, an epitaxial technique, and / or another type of deposition technique.

[0060] like Figure 4B and Figure 4C As shown in FIG. 4 , the optical modulator structure 202 and the waveguide structure 204 may be formed in the semiconductor layer 408. Figure 4C As shown in FIG. 4 , a contact structure 410 may also be formed in the semiconductor layer 408. The contact structure 410 may be formed adjacent to the optical modulator structure 202 and may be used to provide an electrical input to the optical modulator structure 202 for generating a modulated optical signal.

[0061] In some implementations, the semiconductor layer 408 is etched using a pattern in a masking layer (e.g., a hard mask layer, a photoresist layer) to form the optical modulator structure 202, the waveguide structure 204, and / or the contact structure 410. The masking layer can be formed on the semiconductor layer 408 using a deposition tool 102 (e.g., using a CVD technique, a PVD technique, and / or another type of deposition technique). Portions of the masking layer can be removed using an exposure tool 104 and an etching tool 108 to form a pattern in the masking layer. Then, an etching operation can be performed using an etching tool 108 to etch the semiconductor layer 408 based on the pattern in the masking layer to form the optical modulator structure 202, the waveguide structure 204, and / or the contact structure 410. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool is used to remove the remaining portion of the masking layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a planarization tool 110 is used to remove the remaining portions of the masking layer using a CMP technique and / or another type of planarization technique.

[0062] like Figure 4D and Figure 4E As shown in , dielectric material may be deposited over dielectric layer 406 to encapsulate optical modulator structure 202, waveguide structure 204, and / or contact structure 410 in dielectric layer 222 of semiconductor device 200. Deposition tool 102 may be used to deposit dielectric material using CVD technique, PVD technique, oxidation technique (e.g., thermal oxidation technique), and / or another type of deposition technique. In some implementations, one or more additional semiconductor processing operations may be performed to deposit additional material of dielectric layer 222. For example, deposition tool 102 may be used to perform a shallow trench isolation (STI) liner oxidation operation and / or a high density plasma (HDP) deposition operation to deposit dielectric material of dielectric layer 222. As another example, planarization tool 110 may be used to perform a CMP operation and / or another type of planarization operation to planarize dielectric layer 222 after the dielectric material is deposited. The CMP operation may expose the top surface of the optical modulator structure 202 , the top surface of the waveguide structure 204 , and / or the top surface of the contact structure 410 through the dielectric layer 222 .

[0063] In some implementations, one or more portions of the optical modulator structure 202 may then be doped with one or more types of dopants to form one or more doped regions in the optical modulator structure 202. For example, one or more portions of the optical modulator structure 202 may be implanted with p-type ions using an ion implantation tool 114 (e.g., using an ion implantation technique and / or another type of doping technique) to form one or more p-type regions in the optical modulator structure 202. As another example, one or more portions of the optical modulator structure 202 may be implanted with n-type ions using an ion implantation tool 114 (e.g., using an ion implantation technique and / or another type of doping technique) to form one or more n-type regions in the optical modulator structure 202.

[0064] like Figure 4F and Figure 4G As shown in , one or more additional layers may be formed over and / or on the dielectric layer 222 after forming the optical modulator structure 202, after forming the waveguide structure 204, and / or after forming the contact structure 410. For example, an etch stop layer 226 may be formed over and / or on the dielectric layer 222. As another example, a dielectric layer 224 may be formed over and / or on the etch stop layer 226. As another example, an etch stop layer 412 may be formed over and / or on the dielectric layer 224.

[0065] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The etch stop layer 226, the dielectric layer 224, and / or the etch stop layer 412 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some implementations, after the deposition tool 102 deposits the etch stop layer 226, the dielectric layer 224, and / or the etch stop layer 412, the planarization tool 110 planarizes the etch stop layer 226, the dielectric layer 224, and / or the etch stop layer 412.

[0066] like Figure 4GAs further shown in FIG. 1 , in some embodiments, a silicide layer 414 can be formed on and / or on the top surface of the contact structure 410 before forming the one or more additional layers. The silicide layer 414 can include a metal silicide layer that is included to achieve a relatively low contact resistance of the contact structure 410 and / or to reduce the possibility of forming a native oxide on the top surface of the contact structure 410. The silicide layer 414 can be deposited using a deposition tool 102 using a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some embodiments, a pre-cleaning operation can be performed using the deposition tool 102 to remove oxide (e.g., native oxide) from the top surface of the contact structure 410 before forming the silicide layer 414.

[0067] like Figure 4H and Fig. 4I As shown in FIG. 4 , a masking layer 416 may be formed above and / or on the etch stop layer 412. The masking layer 416 may include a hard mask layer, a photoresist layer, and / or another type of masking layer. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The masking layer 416 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. A pattern can then be formed in the masking layer 416. In some implementations, the pattern can be formed by etching the masking layer 416 using the etching tool 108 to remove portions of the masking layer 416.

[0068] like Figure 4J and Figure 4K As shown in , a shielding layer 416 can be used to etch through the etch stop layer 412 and into a portion of the dielectric layer 224 to form a recess 418 in the dielectric layer 224. The recess 418 can be formed to a first depth corresponding to the dimension D1. An etching operation (e.g., a first etching operation) can be performed using an etching tool 108 to etch the etch stop layer 412 and the dielectric layer 224 to form the recess 418. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the shielding layer 416 (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a planarization tool 110 is used to remove the remaining portion of the shielding layer 416 using a CMP technique and / or another type of planarization technique.

[0069] like Figure 4L and Figure 4MAs shown in FIG. 1 , a masking layer 420 (e.g., another masking layer) may be formed after removing the masking layer 416. The masking layer 420 may include a hard mask layer, a photoresist layer, and / or another type of masking layer. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The masking layer 420 is deposited during one or more deposition operations of another type and / or during one or more deposition operations of another type.

[0070] A pattern may then be formed in the masking layer 420. In some implementations, the pattern may be formed by etching the masking layer 420 using the etching tool 108 to remove portions of the masking layer 420. The remaining portions of the masking layer 420 may cover portions 418a of the recess 418 that are located above the optical modulator structure 202 and above the waveguide structure 204. Portions 418b of the recess 418 that are not located above the optical modulator structure 202 and the waveguide structure 204 may be exposed by the pattern in the masking layer 420.

[0071] like Figure 4N and Fig.4O As shown in , a masking layer 420 located above the portion 418a of the recess 418 can be used to etch the portion 418b (e.g., the exposed portion) of the recess 418 (e.g., so that the portion 418a is not etched). The etching tool 108 can be used to perform an etching operation (e.g., a second etching operation after the first etching operation) to etch the dielectric layer 224, thereby increasing the depth of the portion 418b of the recess 418 from a first depth (e.g., corresponding to the dimension D1) to a second depth corresponding to the dimension D3. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. Because the portion 418a is covered by the masking layer 420, the portion 418a remains at the first depth.

[0072] like Figure 4P and Figure 4Q As shown in , a photoresist removal tool is used to remove the remaining portion of the shielding layer 420 (e.g., using a chemical stripper, plasma ashing, and / or another technique). Additionally and / or alternatively, a planarization tool 110 is used to remove the remaining portion of the shielding layer 420 using a CMP technique and / or another type of planarization technique. Figure 4P and Figure 4QAs further shown in FIG. 4 , portion 418a of recess 418 may be formed to a first depth corresponding to dimension D1 (e.g., relative to the top surface of dielectric layer 224). Portion 418b of recess 418 may be formed to a second depth corresponding to dimension D3 (e.g., relative to the top surface of dielectric layer 224). The depth difference between portion 418a and portion 418b may correspond to dimension D2.

[0073] like Figure 4R As shown in FIG. 4 , a masking layer 422 may be formed on and / or over the etch stop layer 412 and in the recess 418 such that the portion 418a and the portion 418b are covered by the masking layer 422. The masking layer 422 may include a hard mask layer, a photoresist layer, and / or another type of masking layer. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The shielding layer 422 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. A pattern can then be formed in the shielding layer 422. In some implementations, the pattern can be formed by etching the shielding layer 422 using an etching tool 108 to remove portions of the shielding layer 422 that are located above the contact structure 410.

[0074] like Figure 4S As shown in , the pattern in the shielding layer 422 can be used to etch the etch stop layer 412, the dielectric layer 224, and the etch stop layer 226 to form a recess 424 on the contact structure 410. The silicide layer 414 located on the top surface of the contact structure 410 can be exposed through the recess. The etching operation can be performed using the etching tool 108 to etch the etch stop layer 412, the dielectric layer 224, and the etch stop layer 226 to form the recess 424. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the shielding layer 422 (for example, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a planarization tool 110 is used to remove the remaining portion of the shielding layer 422 using a CMP technique and / or another type of planarization technique.

[0075] like Figure 4T and Figure 4UAs shown in FIG. 4 , a conductive material layer 426 may be formed in the recess 418 and in the recess 424. The conductive material layer 426 may land on the silicide layer 414 located on the top surface of the contact structure 410. The conductive material layer 426 may include tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), cobalt (Co), and / or another conductive material. The deposition tool 102 and / or the plating tool 112 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1 Conductive material layer 426 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some implementations, a seed layer is deposited first, and conductive material layer 426 is deposited on the seed layer.

[0076] like Figure 4V and Figure 4W , material may be removed from the conductive material layer 426. The remaining portion of the conductive material layer 426 may correspond to the modulated heater structure 206 (the modulated heater structure 206 may be formed in the recess 418) and the interconnect structure 428 (the interconnect structure 428 may be formed in the recess 424 above the contact structure 410). The conductive material layer 426 may be planarized using the planarization tool 110 to remove material from the conductive material layer 426.

[0077] like Figure 4V , the modulated heater structure 206 may include a lower portion 210a and an upper portion 210b. The upper portion 210b may include an overhang section 212. The overhang section 212 of the upper portion 210b may be formed in a portion 418a of a recess 418 (e.g., located above the optical modulator structure 202 and above the waveguide structure 204). The lower portion 210a and the upper portion 210b (e.g., except for the overhang section 212) may be formed in a portion 418b of the recess 418.

[0078] like Figure 4X and Figure 4Y As shown in , a portion of the BEOL region of the semiconductor device 200 can be formed over the FEOL region of the semiconductor device 200. For example, a dielectric layer 228 can be formed over and / or on the dielectric layer 224 and over and / or on the modulated heater structure 206. A BEOL interconnect layer 208 can be formed in the dielectric layer 228. The BEOL interconnect layer 208 can be formed over and / or on the modulated heater structure 206 and over and / or on the interconnect structure 428, as well as at other examples. The BEOL interconnect layer 208 can be approximately coplanar and can be referred to as a first metal (metal-1, M1) layer of the BEOL region.

[0079] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The dielectric layer 228 may be deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described herein. The deposition tool 102 and / or the plating tool 112 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1 The BEOL interconnect layer 208 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some embodiments, a seed layer is deposited first, and the BEOL interconnect layer 208 is deposited on the seed layer. A CMP operation and / or another type of planarization operation can be performed using the planarization tool 110 to planarize the BEOL interconnect layer 208.

[0080] like Figure 4Z and Figure 4AA As shown in , additional metallization layers of the BEOL region can be formed over and / or on the BEOL interconnect layer 208. For example, a BEOL interconnect layer 430 (e.g., a first via layer) can be formed over and / or on the BEOL interconnect layer 208. As another example, a BEOL interconnect layer 432 (e.g., a second metal or M2 layer) can be formed over and / or on the BEOL interconnect layer 430. As another example, a BEOL interconnect layer 434 (e.g., a second via layer) can be formed over and / or on the BEOL interconnect layer 432. As another example, a BEOL interconnect layer 436 (e.g., a third metal or M3 layer) can be formed over and / or on the BEOL interconnect layer 434.

[0081] The deposition tool 102 and / or the plating tool 110 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1 The BEOL interconnect layers 430 to 436 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some embodiments, a seed layer is deposited first, and the BEOL interconnect layers 430 to 436 are deposited on the seed layer. A CMP operation and / or another type of planarization operation can be performed using the planarization tool 110 to planarize the BEOL interconnect layers 430 to 436.

[0082] As mentioned above, Figures 4A to 4AA are provided as examples. Other examples may be found in the Figure 4AA Different from what is described.

[0083] Figure 5 is a diagram of an exemplary semiconductor device 500 described in an embodiment of the present invention. The semiconductor device 500 may include a semiconductor photonic device and / or another type of semiconductor device including one or more photonic integrated circuits. Figure 5 A top view of semiconductor device 500 and a corresponding cross-sectional view along line AA in the top view are shown. Semiconductor device 500 may be configured to perform high-speed and secure data transfer between integrated circuits and / or semiconductor dies of semiconductor device 500 using optical signals.

[0084] like Figure 5 As shown in FIG. 5 , the semiconductor device 500 may include a Figure 2 The semiconductor device 500 may include components (502-528) that may be similar to the components (202-228) of the semiconductor device 200 shown and described. For example, the semiconductor device 500 may include components (502-528) that may be similar to the components (202-228) of the semiconductor device 200. However, instead of including the lower portion 210a and the upper portion 210b in the dielectric layer 224, the semiconductor device 500 includes a main portion 510a located in the dielectric layer 524 and one or more extension portions 510b located on the main portion 510a. The extension portion 510b (also referred to as an extension layer) may be included in the BEOL region of the semiconductor device 500 (e.g., included in the dielectric layer 528) and as such may be referred to as a BEOL extension portion of the modulated heater structure 506.

[0085] The extension portion 510b may be included on and / or over one or more of the heater pads 518a and / or 518b to effectively increase the thickness of the heater pads 518a and / or 518b. This enables low resistance to be achieved in the heater pads 518a and / or 518b. The main portion 510a may extend laterally outward from the end or inner edge of the extension portion 510b so that the modulation heater structure 506 includes an extension section 512 (the extension section 512 is inverted in the z-direction relative to the overhang section 212 of the modulation heater structure 206). The extension section 512 may correspond to the heater ring 514 of the modulation heater structure 506. The smaller thickness of the extension section 512 relative to the combined thickness of the main portion 510a and the extension portion 510b provides a resistance in the heater ring 514 that is greater than the resistance in the heater pads 518a and / or 518b, which enables the heater ring 514 to efficiently generate heat to be provided to the optical modulator structure 502.

[0086] The main portion 510a and the extension portion 510b of the modulated heater structure 506 may be formed during different processes of forming the semiconductor device 500. For example, the main portion 510a may be formed during a FEOL process, and the extension portion 510b may be formed during a BEOL process (e.g., together with the BEOL interconnect layer 508). Thus, the main portion 510a and the extension portion 510b may be formed in a separate set of one or more deposition operations, thereby forming a seam or material interface between the main portion 510a and the extension portion 510b. In some implementations, the main portion 510a and the extension portion 510b are formed of the same material or the same material composition. In some implementations, the main portion 510a and the extension portion 510b are formed of different materials or different material compositions. For example, the main portion 510a may be formed of a FEOL material such as tungsten (W) and / or another conductive FEOL material, and the extension portion 510b may be formed of copper (Cu), ruthenium (Ru), cobalt (Co), and / or another BEOL conductive material.

[0087] like Figure 5 As further shown in FIG. 5 , the modulated heater structure 206 may include one or more dimensions, such as dimension D5, dimension D6, dimension D7, and / or dimension D8, among other examples. Dimension D5 may correspond to the cross-sectional thickness (e.g., z-direction thickness) of the main portion 510a of the modulated heater structure 506. In addition, dimension D5 may correspond to the cross-sectional thickness (e.g., z-direction thickness) of the heater ring 514. In some embodiments, dimension D5 is included in a range of approximately 80 nanometers to approximately 240 nanometers. Values ​​less than approximately 80 nanometers for dimension D5 may result in uneven heating of the optical modulator structure 502 due to process variations in forming the heater ring 514. Values ​​greater than approximately 240 nanometers for dimension D5 may result in insufficient resistance in the heater ring 514, and thus the heater ring 514 may not adequately heat the optical modulator structure 502. However, ranges other than approximately 80 nanometers to approximately 240 nanometers for dimension D5 may be used and are within the scope of embodiments of the present invention.

[0088] Dimension D6 can correspond to the cross-sectional thickness (e.g., z-direction thickness) of the extended portion 510b of the modulated heater structure 506. In some implementations, dimension D6 is included in a range of approximately 200 nanometers to approximately 300 nanometers to achieve sufficiently low resistance in the heater pads 518a and / or 518b, which enables high energy efficiency to be achieved for the modulated heater structure 506. However, ranges other than approximately 200 nanometers to approximately 300 nanometers for dimension D6 can be used and are within the scope of embodiments of the present invention.

[0089] Dimension D7 can correspond to the cross-sectional thickness (e.g., z-direction thickness) of the heater pads 518a and / or 518b of the modulated heater structure 506. Thus, dimension D7 can correspond to the combined thickness of the main portion 510a (e.g., dimension D5) and the extended portion 510b (e.g., dimension D6) of the modulated heater structure 506. In some implementations, dimension D7 is included within a range of approximately 280 nanometers to approximately 540 nanometers to achieve sufficiently low resistance in the heater pads 518a and / or 518b, which enables high energy efficiency to be achieved for the modulated heater structure 506. However, ranges other than approximately 280 nanometers to approximately 540 nanometers for dimension D7 can be used and are within the scope of embodiments of the present invention.

[0090] Dimension D8 may correspond to the cross-sectional width (e.g., y-direction width) of the extension section 512 of the modulated heater structure 506. In some embodiments, dimension D8 is included in a range of approximately 5 microns to approximately 10 microns. Values ​​less than approximately 5 microns for dimension D8 may result in the extension portion 510b being unable to withstand the processing temperatures required to form the extension portion 510b. Values ​​greater than approximately 10 microns for dimension D8 may result in insufficient resistance in the heater ring 514, and thus the heater ring 514 may not be able to adequately heat the optical modulator structure 502. However, ranges other than approximately 5 microns to approximately 10 microns for dimension D8 may be used and are within the scope of embodiments of the present invention.

[0091] Thus, the semiconductor device 500 may include: a first dielectric layer (e.g., dielectric layer 522), an etch stop layer (e.g., etch stop layer 526) located on the first dielectric layer, a second dielectric layer (e.g., dielectric layer 524) located on the etch stop layer, an optical modulator structure 502 located in the first dielectric layer, and a modulated heater structure 506 located above the optical modulator structure 502 and included in the second dielectric layer. The modulated heater structure 506 may include: a heater ring 514 located directly above the optical modulator structure 502, a heater pad (e.g., heater pads 518a and / or 518b) coupled to the heater ring 514, and a contact region (e.g., contact region 520a and / or 520b) coupled to the heater pad. The semiconductor device 500 may further include: a BEOL interconnect layer 508 located on and coupled to the contact region of the modulated heater structure 506, and a BEOL extension layer (e.g., extension layer 510) located on and coupled to the heater pad.

[0092] Various cross-section lines Figure 5 In the combination shown and referenced FIG. 6A to FIG. 6UCross-sectional line AA is in a second direction (e.g., y-direction) in semiconductor device 500 and extends along modulated heater structure 506. Cross-sectional line BB is in a first direction (e.g., x-direction) in semiconductor device 500 and extends across heater ring 514 of modulated heater structure 506. Cross-sectional line CC is in a first direction (e.g., x-direction) in semiconductor device 500 and extends across heater pad 518a of modulated heater structure 506.

[0093] As mentioned above, Figure 5 are provided as examples. Other examples may be used with Figure 5 Different from what is described.

[0094] FIG. 6A to FIG. 6U 6 is a diagram of an example implementation 600 that forms a semiconductor device 500 (or a portion of a semiconductor device 500) described in an embodiment of the present invention. In some implementations, one or more of the semiconductor processing operations described in connection with the example implementation 600 may be performed using one or more of the semiconductor processing tools (102-114) and / or by a wafer / die transport tool 116. In some implementations, one or more of the semiconductor processing operations described in connection with the example implementation 600 may be performed using another semiconductor processing tool.

[0095] Go to Fig. 6A , a substrate 602 may be provided. The substrate 602 may include an SOI substrate, the SOI substrate including a semiconductor substrate 604 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a dielectric layer 606 (e.g., a BOX layer and / or another type of insulator layer) located on and / or on the semiconductor substrate 604, and a semiconductor layer 608 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) located on and / or on the dielectric layer 606. Alternatively, the semiconductor substrate 604 may be provided as a semiconductor wafer, and the dielectric layer 606 may be formed on and / or on the semiconductor substrate 604 using a deposition tool 102, and the semiconductor layer 608 may be formed on and / or on the dielectric layer 606 using another deposition tool 102. The deposition tool 102 may be used to form the dielectric layer 606 using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. The deposition tool 102 may be used to form the semiconductor layer 608 using a CVD technique, a PVD technique, an epitaxial technique, and / or another type of deposition technique.

[0096] like Figure 6B and Figure 6C As shown in FIG. 6 , an optical modulator structure 502 and a waveguide structure 504 may be formed in a semiconductor layer 608. Figure 6C As shown in FIG, a contact structure 610 may also be formed in the semiconductor layer 608. The contact structure 610 may be formed adjacent to the optical modulator structure 502 and may be used to provide an electrical input to the optical modulator structure 502 for generating a modulated optical signal.

[0097] In some implementations, the semiconductor layer 608 is etched using a pattern in a masking layer (e.g., a hard mask layer, a photoresist layer) to form the optical modulator structure 502, the waveguide structure 504, and / or the contact structure 610. The masking layer can be formed on the semiconductor layer 608 using a deposition tool 102 (e.g., using a CVD technique, a PVD technique, and / or another type of deposition technique). Portions of the masking layer can be removed using an exposure tool 104 and an etching tool 108 to form a pattern in the masking layer. Then, an etching operation can be performed using an etching tool 108 to etch the semiconductor layer 608 based on the pattern in the masking layer to form the optical modulator structure 502, the waveguide structure 504, and / or the contact structure 610. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool is used to remove the remaining portion of the masking layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a planarization tool 110 is used to remove the remaining portions of the masking layer using a CMP technique and / or another type of planarization technique.

[0098] like Fig.6D and Fig. 6E , dielectric material may be deposited over dielectric layer 606 to encapsulate optical modulator structure 502, waveguide structure 504, and / or contact structure 610 in dielectric layer 522 of semiconductor device 500. Deposition tool 102 may be used to deposit dielectric material using CVD technique, PVD technique, oxidation technique (e.g., thermal oxidation technique), and / or another type of deposition technique. In some implementations, one or more additional semiconductor processing operations may be performed to deposit additional material for dielectric layer 522. For example, deposition tool 102 may be used to perform an STI liner oxidation operation and / or an HDP deposition operation to deposit dielectric material for dielectric layer 522. As another example, planarization tool 110 may be used to perform a CMP operation and / or another type of planarization operation to planarize dielectric layer 522 after the dielectric material is deposited. The CMP operation may expose the top surface of the optical modulator structure 502 , the top surface of the waveguide structure 504 , and / or the top surface of the contact structure 610 through the dielectric layer 522 .

[0099] In some implementations, one or more portions of the optical modulator structure 502 may then be doped with one or more types of dopants to form one or more doped regions in the optical modulator structure 502. For example, an ion implantation tool 114 may be used (e.g., using an ion implantation technique and / or another type of doping technique) to implant one or more portions of the optical modulator structure 502 with p-type ions to form one or more p-type regions in the optical modulator structure 502. As another example, an ion implantation tool 114 may be used (e.g., using an ion implantation technique and / or another type of doping technique) to implant one or more portions of the optical modulator structure 502 with n-type ions to form one or more n-type regions in the optical modulator structure 502.

[0100] like Fig. 6F and Figure 6G As shown in , one or more additional layers can be formed over and / or on the dielectric layer 522 after forming the optical modulator structure 502, after forming the waveguide structure 504, and / or after forming the contact structure 610. For example, an etch stop layer 526 can be formed over and / or on the dielectric layer 522. As another example, a dielectric layer 524 can be formed over and / or on the etch stop layer 526. As another example, an etch stop layer 612 can be formed over and / or on the dielectric layer 524.

[0101] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The etch stop layer 526, the dielectric layer 524, and / or the etch stop layer 612 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some implementations, after the deposition tool 102 deposits the etch stop layer 526, the dielectric layer 524, and / or the etch stop layer 612, the planarization tool 110 planarizes the etch stop layer 526, the dielectric layer 524, and / or the etch stop layer 612.

[0102] like Figure 6GAs further shown in FIG. 1 , in some embodiments, a silicide layer 614 can be formed on and / or on the top surface of the contact structure 610 before forming the one or more additional layers. The silicide layer 614 can include a metal silicide layer that is included to achieve a relatively low contact resistance of the contact structure 610 and / or reduce the possibility of forming a native oxide on the top surface of the contact structure 610. The silicide layer 614 can be deposited using a deposition tool 102 using a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some embodiments, a pre-cleaning operation can be performed using the deposition tool 102 to remove oxide (e.g., native oxide) from the top surface of the contact structure 610 before forming the silicide layer 614.

[0103] like Figure 6H and Fig.6I As shown in FIG. 1 , a masking layer 616 may be formed over and / or on the etch stop layer 612. The masking layer 616 may include a hard mask layer, a photoresist layer, and / or another type of masking layer. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The masking layer 616 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. A pattern can then be formed in the masking layer 616. In some implementations, the pattern can be formed by etching the masking layer 616 using the etching tool 108 to remove portions of the masking layer 616.

[0104] like Figure 6J and Figure 6K As shown in , a shielding layer 616 can be used to etch through the etch stop layer 612 and into a portion of the dielectric layer 524 to form a recess 618 in the dielectric layer 524. The recess 618 can be formed to a depth corresponding to the dimension D5. The etching operation can be performed using an etching tool 108 to etch the etch stop layer 612 and the dielectric layer 524 to form the recess 618. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the shielding layer 616 (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a planarization tool 110 is used to remove the remaining portion of the shielding layer 616 using a CMP technique and / or another type of planarization technique.

[0105] like Figure 6LAs shown in FIG. 1 , a masking layer 620 may be formed above and / or on the etch stop layer 612 and in the recess 618 such that the recess 618 is covered by the masking layer 620. The masking layer 620 may include a hard mask layer, a photoresist layer, and / or another type of masking layer. The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, or a combination thereof. Figure 1 The shielding layer 620 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. A pattern can then be formed in the shielding layer 620. In some implementations, the pattern can be formed by etching the shielding layer 620 using an etching tool 108 to remove portions of the shielding layer 620 that are located above the contact structure 610.

[0106] like Figure 6M As shown in , the etch stop layer 612, the dielectric layer 524, and the etch stop layer 526 can be etched using the pattern in the shielding layer 620 to form a recess 622 on the contact structure 610. The silicide layer 614 located on the top surface of the contact structure 610 can be exposed through the recess. The etching operation can be performed using the etching tool 108 to etch the etch stop layer 612, the dielectric layer 524, and the etch stop layer 526 to form the recess 622. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the shielding layer 620 (for example, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a planarization tool 110 is used to remove the remaining portion of the shielding layer 620 using a CMP technique and / or another type of planarization technique.

[0107] like Figure 6N and Fig.6O As shown in FIG. 6 , a conductive material layer 624 may be formed in the recess 618 and in the recess 622. The conductive material layer 624 may land on the silicide layer 614 located on the top surface of the contact structure 610. The conductive material layer 624 may include tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), cobalt (Co), and / or another conductive material. The deposition tool 102 and / or the plating tool 112 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1 Conductive material layer 624 is deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some implementations, a seed layer is deposited first, and conductive material layer 624 is deposited on the seed layer.

[0108] like Figure 6P and Figure 6Q , material may be removed from the conductive material layer 624. The remaining portion of the conductive material layer 624 may correspond to the main portion 510a of the modulated heater structure 506 (the main portion 510a may be formed in the recess 618) and the interconnect structure 626 (the interconnect structure 626 may be formed in the recess 622 above the contact structure 610). The conductive material layer 624 may be planarized using a planarization tool 110 to remove material from the conductive material layer 624.

[0109] like Figure 6R and Figure 6S As shown in , a portion of the BEOL region of the semiconductor device 500 can be formed over the FEOL region of the semiconductor device 500. For example, a dielectric layer 528 can be formed over and / or on the dielectric layer 524 and over and / or on the main portion 510a of the modulated heater structure 506. The BEOL interconnect layer 508 can be formed in the dielectric layer 528. The BEOL interconnect layer 508 can be formed over and / or on the modulated heater structure 506 and over and / or on the interconnect structure 626, as well as at other examples. The BEOL interconnect layer 508 can be approximately coplanar and can be referred to as a first metal (M1) layer of the BEOL region.

[0110] Additionally, as part of the BEOL region formation process, an extension portion 510b of the modulated heater structure 506 may be formed in the dielectric layer 528 and on the modulated heater structure 506 (e.g., on the heater pads 518a and / or 518b of the modulated heater structure 506). The extension portion 510b may be formed in the same set of one or more M1 layer semiconductor processing operations as the BEOL interconnect layer 508. The extension portion 510b may be formed to a thickness corresponding to dimension D6 such that the total thickness of the heater pads 518a and / or 518b corresponds to dimension D7.

[0111] The deposition tool 102 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, a combination of Figure 1 The dielectric layer 528 may be deposited in one or more deposition operations of another type described herein and / or one or more deposition operations of another type. The deposition tool 102 and / or the plating tool 112 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1The BEOL interconnect layer 508 and / or the extension portion 510b are deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some embodiments, a seed layer is deposited first, and the BEOL interconnect layer 508 and / or the extension portion 510b are deposited on the seed layer. A CMP operation and / or another type of planarization operation can be performed using the planarization tool 110 to planarize the BEOL interconnect layer 508 and / or the extension portion 510b.

[0112] like Figure 6T and Figure 6U As shown in , additional metallization layers of the BEOL region can be formed over and / or on the BEOL interconnect layer 508. For example, a BEOL interconnect layer 628 (e.g., a first via layer) can be formed over and / or on the BEOL interconnect layer 508. As another example, a BEOL interconnect layer 630 (e.g., a second metal or M2 layer) can be formed over and / or on the BEOL interconnect layer 628. As another example, a BEOL interconnect layer 632 (e.g., a second via layer) can be formed over and / or on the BEOL interconnect layer 630. As another example, a BEOL interconnect layer 634 (e.g., a third metal or M3 layer) can be formed over and / or on the BEOL interconnect layer 632.

[0113] The deposition tool 102 and / or the plating tool 110 may be used in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more electroplating operations, a combination of Figure 1 The BEOL interconnect layers 628 to 634 are deposited in one or more deposition operations of another type and / or one or more deposition operations of another type as described. In some implementations, a seed layer is deposited first, and the BEOL interconnect layers 628 to 634 are deposited on the seed layer. A CMP operation and / or another type of planarization operation can be performed using the planarization tool 110 to planarize the BEOL interconnect layers 628 to 634.

[0114] As mentioned above, FIG. 6A to FIG. 6U are provided as examples. Other examples may be used with FIG. 6A to FIG. 6U Different from what is described.

[0115] Figure 7is a diagram of example components of apparatus 700 described in an embodiment of the present invention. In some implementations, one or more of the semiconductor processing tools (102-114) and / or the wafer / die transport tool 116 may include one or more apparatuses 700 and / or one or more components of apparatus 700. Figure 7 As shown in , device 700 may include a bus 710 , a processor 720 , a memory 730 , an input component 740 , an output component 750 , and / or a communication component 760 .

[0116] The bus 710 may include one or more components that enable wired and / or wireless communications between components of the device 700. The bus 710 may include: Figure 7 The two or more components shown are coupled together, for example, by operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 710 may include electrical connectors (such as wiring, traces and / or leads) and / or wireless buses. Processor 720 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit and / or another type of processing component. Processor 720 can be implemented in hardware, firmware or a combination of hardware and software. In some embodiments, processor 720 may include one or more processors, which can be programmed to implement one or more operations or processes described elsewhere in embodiments of the present utility model.

[0117] The memory 730 may include volatile memory and / or non-volatile memory. For example, the memory 730 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 730 may include internal memory (e.g., RAM, ROM, or hard drive) and / or removable memory (e.g., removable via a universal serial bus connector). The memory 730 may be a non-transitory computer-readable medium. The memory 730 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 700. In some embodiments, the memory 730 may include, for example, one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 720) via bus 710. The communicative coupling between the processor 720 and the memory 730 may enable the processor 720 to read and / or process information stored in the memory 730 and / or store information in the memory 730.

[0118] Input components 740 may enable device 700 to receive input, such as user input and / or sensed input. For example, input components 740 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 750 may enable device 700 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication components 760 may enable device 700 to communicate with other devices via wired connections and / or wireless connections. For example, communication components 760 may include a receiver, a transmitter, a transceiver, a modem, a network card, and / or an antenna.

[0119] The device 700 can implement one or more operations or processes described in the embodiments of the present utility model. For example, a non-transitory computer-readable medium (such as a memory 730) can store a set of instructions (such as one or more instructions or codes) for execution by the processor 720. The processor 720 can execute the set of instructions to implement one or more operations or processes described in the embodiments of the present utility model. In some embodiments, the execution of the set of instructions by one or more processors 720 causes the one or more processors 720 and / or the device 700 to implement one or more operations or processes described in the embodiments of the present utility model. In some embodiments, a hardwired circuit system (hardwired circuitry) can be used instead of instructions or in combination with instructions to implement one or more operations or processes described in the embodiments of the present utility model. In addition or as another option, the processor 720 can be configured to implement one or more operations or processes described in the embodiments of the present utility model. Therefore, the implementation scheme described in the embodiments of the present utility model is not limited to any specific combination of hardware circuit system and software.

[0120] Figure 7 The number and arrangement of components shown in are provided as examples. The device 700 may include Figure 7 Components shown in the additional components, fewer components, and Figure 7 Additionally or alternatively, one set of components (eg, one or more components) of device 700 may perform one or more functions described as being performed by another set of components of device 700.

[0121] Figure 8 8 is a flow chart of an exemplary process 800 associated with forming a semiconductor photonic device described in an embodiment of the present invention. In some implementations, one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools (102-114)) are used to perform Figure 8 Additionally or alternatively, Figure 8 One or more of the process blocks shown may be implemented using one or more components of the apparatus 700 , such as the processor 720 , the memory 730 , the input component 740 , the output component 750 , and / or the communication component 760 .

[0122] like Figure 8 As shown in , process 800 may include forming an optical modulator structure and a waveguide structure adjacent to the optical modulator structure in a semiconductor layer located above a first dielectric layer (block 810). For example, an optical modulator structure (e.g., optical modulator structure 202, optical modulator structure 502) and a waveguide structure adjacent to the optical modulator structure (e.g., waveguide structure 204, waveguide structure 504) may be formed in a semiconductor layer (e.g., semiconductor layer 408, semiconductor layer 608) located above a first dielectric layer (e.g., dielectric layer 406, dielectric layer 606) using one or more of semiconductor processing tools (102-114), as described in embodiments of the present invention.

[0123] like Figure 8 As further shown in FIG. 8 , process 800 may include forming an etch stop layer over the first dielectric layer, over the optical modulator structure, and over the waveguide structure (block 820). For example, the etch stop layer (e.g., etch stop layer 226, etch stop layer 526) may be formed over the first dielectric layer, over the optical modulator structure, and over the waveguide structure using one or more of the semiconductor processing tools (102-114), as described in embodiments of the present invention.

[0124] like Figure 8 As further shown in FIG. 8 , process 800 may include forming a second dielectric layer over the etch stop layer (block 830). For example, the second dielectric layer (e.g., dielectric layer 224, dielectric layer 524) may be formed over the etch stop layer using one or more of the semiconductor processing tools (102-114), as described in embodiments of the present invention.

[0125] like Figure 8As further shown in FIG. 8 , process 800 may include forming a modulated heater structure in the second dielectric layer (block 840). For example, a modulated heater structure (e.g., modulated heater structure 206, modulated heater structure 506) may be formed in the second dielectric layer using one or more of the semiconductor processing tools (102-114), as described in embodiments of the present invention. In some implementations, a heater ring (e.g., heater ring 214, heater ring 514) of the modulated heater structure is formed over the optical modulator structure. In some implementations, heater pads (e.g., heater pad 218a, heater pad 218b, heater pad 518a, heater pad 518b) of the modulated heater structure coupled to the heater ring extend laterally outward from the heater ring. In some implementations, a thickness (e.g., dimension D3, dimension D7) of the heater pad is larger relative to a thickness (e.g., dimension D1, dimension D5) of the heater ring.

[0126] Process 800 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere in the embodiments of the present invention.

[0127] In a first embodiment, forming a modulated heater structure includes: using a first shielding layer (e.g., shielding layer 416) in a first etching operation to etch a groove (e.g., groove 418) in a second dielectric layer to a first depth (e.g., dimension D1) in the second dielectric layer; etching the second dielectric layer using a second shielding layer (e.g., shielding layer 420) over a first portion of the groove (e.g., portion 418a) in a second etching operation after the first etching operation to increase the first depth to a second depth (e.g., dimension D3) in a second portion of the groove (e.g., portion 418a), wherein the first portion remains at the first depth due to the second shielding layer being over the first portion; depositing a conductive material layer (e.g., conductive material layer 426) in the groove after the second etching operation; and planarizing the conductive material layer to form a modulated heater structure.

[0128] In a second embodiment, either alone or in combination with the first embodiment, a first portion of the recess is located above the waveguide structure and the optical modulator structure.

[0129] In a third embodiment, alone or in combination with one or more of the first and second embodiments, a heater ring is formed in a first portion of the groove, and a heater pad is formed in a second portion of the groove.

[0130] In a fourth embodiment, forming a modulated heater structure, alone or in combination with one or more of the first to third embodiments, includes: etching a groove (e.g., groove 618) in a second dielectric layer using a masking layer (e.g., masking layer 616) during an etching operation; depositing a conductive material layer (e.g., conductive material layer 624) in the groove after the etching operation; planarizing the conductive material layer to form a modulated heater structure; and forming an extension layer (e.g., extension portion 510b) of a heater pad on the modulated heater structure.

[0131] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 800 includes: forming a third dielectric layer (e.g., dielectric layer 528) above the second dielectric layer, wherein forming an extension layer for a heater pad includes forming an extension layer for a heater pad in the third dielectric layer.

[0132] although Figure 8 Example blocks of process 800 are shown, but in some embodiments, process 800 includes Figure 8 The blocks shown in the figure are additional blocks, fewer blocks, and Figure 8 The blocks shown in the process 800 may be different blocks or blocks arranged differently. Additionally or alternatively, two or more of the blocks in the process 800 may be performed in parallel.

[0133] In this way, the modulated heater structure may include multiple zones with different thicknesses. For example, a heater ring of the modulated heater structure may have a first thickness. A heater pad of the modulated heater structure configured to provide current to the heater ring may have a second thickness that is greater than the first thickness. The smaller thickness of the heater ring of the modulated heater structure provides a high resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat, which can be provided to stabilize the operating temperature of the optical modulator structure. The larger thickness of the heater pad provides a low resistance in the second zone, which enables current to be efficiently provided to the heater ring through the heater pad, while heat dissipation in the heater pad is reduced due to the lower current dissipation in the heater pad. This enables the modulated heater structure to operate more efficiently and consume less current to provide a similar amount of heat to the optical modulator relative to other modulated heater structure configurations.

[0134] As described in more detail above, some embodiments described in the embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first dielectric layer. The semiconductor device includes an etch stop layer located above the first dielectric layer. The semiconductor device includes a second dielectric layer located above the etch stop layer. The semiconductor device includes an optical modulator structure located in the first dielectric layer. The semiconductor device includes a modulation heater structure, which is located above the optical modulator structure and is included in the second dielectric layer, wherein the modulation heater structure includes: a heater ring located directly above the optical modulator structure and a heater pad coupled to the heater ring, wherein the thickness of the heater pad is greater than the thickness of the heater ring.

[0135] In some embodiments, the modulated heater structure further includes a first heater portion and a second heater portion, the first heater portion extending between a contact area of ​​the modulated heater structure and a connection area of ​​the modulated heater structure, the connection area coupling the heater ring and the heater pad, and the second heater portion extending between the contact area and the heater ring. In some embodiments, the first heater portion includes an overhanging section extending laterally outward from an end of the second heater portion. In some embodiments, the semiconductor device further includes a waveguide structure located in the first dielectric layer and adjacent to the optical modulator structure, wherein the overhanging section is located above the optical modulator structure and the waveguide structure. In some embodiments, a bottom surface of the heater pad is closer to the etch stop layer than a bottom surface of the heater ring.

[0136] As described in more detail above, some embodiments described in the embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first dielectric layer. The semiconductor device includes an etch stop layer located above the first dielectric layer. The semiconductor device includes a second dielectric layer located above the etch stop layer. The semiconductor device includes an optical modulator structure located in the first dielectric layer. The semiconductor device includes a modulation heater structure, which is located above the optical modulator structure and is included in the second dielectric layer, wherein the modulation heater structure includes: a heater ring located directly above the optical modulator structure, a heater pad coupled to the heater ring, and a contact area coupled to the heater pad. The semiconductor device includes a BEOL internal wiring layer, which is located on the contact area of ​​the modulation heater structure and coupled to the contact area. The semiconductor device includes a BEOL extension layer, which is located on the heater pad and coupled to the heater pad.

[0137] In some embodiments, the thickness of the combination of the heater pad and the back-end process extension layer is greater than the thickness of the heater ring. In some embodiments, the back-end process extension layer and the modulated heater structure include different material compositions. In some embodiments, there is a material interface between the back-end process extension layer and the heater pad of the modulated heater structure. In some embodiments, the modulated heater structure includes an extension section extending outward in a lateral direction from an end of the back-end process extension layer. In some embodiments, the semiconductor device further includes a waveguide structure located in the first dielectric layer and adjacent to the optical modulator structure, wherein the extension section is located above the optical modulator structure and the waveguide structure. In some embodiments, the top surface of the back-end process extension layer and the top surface of the back-end process interconnect layer are approximately coplanar in the semiconductor device. In some embodiments, the back-end process extension layer is electrically coupled to the back-end process interconnect layer through the modulated heater structure. In some embodiments, the back-end process interconnect layer and the back-end process extension layer are included in a third dielectric layer located above the second dielectric layer.

[0138] As described in more detail above, some embodiments described in the examples of the present invention provide a method. The method includes: forming an optical modulator structure and a waveguide structure adjacent to the optical modulator structure in a semiconductor layer located above a first dielectric layer. The method includes: forming an etch stop layer above the first dielectric layer, above the optical modulator structure, and above the waveguide structure. The method includes: forming a second dielectric layer above the etch stop layer. The method includes: forming a modulated heater structure in the second dielectric layer, wherein a heater ring of the modulated heater structure is formed above the optical modulator structure, wherein a heater pad of the modulated heater structure coupled to the heater ring extends outwardly from the heater ring in a lateral direction, and wherein the thickness of the heater pad is larger than the thickness of the heater ring.

[0139] In some embodiments, forming the modulated heater structure includes: etching a groove in the second dielectric layer to a first depth in the second dielectric layer using a first shielding layer in a first etching operation; etching the second dielectric layer using a second shielding layer over a first portion of the groove in a second etching operation after the first etching operation to increase the first depth to a second depth in a second portion of the groove, wherein the first portion remains at the first depth due to the second shielding layer being over the first portion; depositing a conductive material layer in the groove after the second etching operation; and planarizing the conductive material layer to form the modulated heater structure. In some embodiments, the first portion of the groove is over the waveguide structure and the optical modulator structure. In some embodiments, the heater ring is formed in the first portion of the groove, wherein the heater pad is formed in the second portion of the groove. In some embodiments, forming the modulated heater structure includes: etching a groove in the second dielectric layer using a masking layer in an etching operation; depositing a conductive material layer in the groove after the etching operation; planarizing the conductive material layer to form the modulated heater structure; and forming an extension layer of the heater pad on the modulated heater structure. In some embodiments, the method further includes forming a third dielectric layer on the second dielectric layer, wherein forming the extension layer of the heater pad includes forming the extension layer of the heater pad in the third dielectric layer.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: a first dielectric layer; An etch stop layer, located on the first dielectric layer; a second dielectric layer, located on the etch stop layer; an optical modulator structure located in the first dielectric layer; as well as A modulated heater structure, located above the optical modulator structure, is included in the second dielectric layer, the modulated heater structure comprising: a heater ring located directly above the optical modulator structure; as well as A heater pad is coupled to the heater ring, wherein a thickness of the heater pad is greater than a thickness of the heater ring.

2. The semiconductor device according to claim 1, wherein: The modulated heater structure further comprises: a first heater portion extending between a contact region of the modulated heater structure and a connection region of the modulated heater structure, the connection region coupling the heater ring and the heater pad; and A second heater portion extends between the contact area and the heater ring.

3. The semiconductor device according to claim 2, wherein: The first heater portion includes an overhanging section extending laterally outward from an end of the second heater portion.

4. The semiconductor device according to claim 1, wherein: The bottom surface of the heater pad is closer to the etch stop layer than the bottom surface of the heater ring.

5. A semiconductor device, characterized in that: include: a first dielectric layer; An etch stop layer, located on the first dielectric layer; a second dielectric layer, located on the etch stop layer; an optical modulator structure located in the first dielectric layer; A modulated heater structure, located above the optical modulator structure, is included in the second dielectric layer, the modulated heater structure comprising: a heater ring located directly above the optical modulator structure; a heater pad coupled to the heater ring; and a contact region coupled to the heater pad; a back-end interconnect layer located on and coupled to the contact region of the modulated heater structure; and The back-end process extension layer is located on the heater pad and coupled with the heater pad.

6. The semiconductor device according to claim 5, wherein: The thickness of the combination of the heater pad and the back-end process extension layer is greater than the thickness of the heater ring.

7. The semiconductor device according to claim 5, wherein: A material interface exists between the back-end process extension layer and the heater pad of the modulated heater structure.

8. The semiconductor device according to claim 5, wherein: The modulated heater structure includes an extension section extending outwardly from an end of the back-end process extension layer in a lateral direction.

9. The semiconductor device according to claim 5, wherein: The back-end process extension layer is electrically coupled to the back-end process interconnect layer through the modulated heater structure.

10. The semiconductor device according to claim 5, wherein: The back-end-of-line interconnect layer and the back-end-of-line extension layer are included in a third dielectric layer located above the second dielectric layer.

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