Reference clock frequency multiplication assembly, quantum calculation measurement and control system and quantum computer

Abstract

The utility model discloses a reference clock frequency multiplication assembly, a quantum computing measurement and control system and a quantum computer, and the reference clock frequency multiplication assembly comprises a frequency multiplication module which is used for carrying out frequency multiplication processing on a first reference clock signal to obtain a second reference clock signal; the power division module is used for performing power division on the second reference clock signal into multiple paths of third reference clock signals; the frequency multiplication module comprises a plurality of first amplifiers which are connected in series and signal processing units between any two adjacent first amplifiers, and at least one signal processing unit comprises a frequency multiplication element and a filter which are connected in series; each first amplifier is used for performing power amplification processing on an input signal; each frequency multiplication element is used for carrying out frequency amplification processing on the signal after power amplification processing, and the filter is used for carrying out filtering processing on the signal after frequency amplification processing. According to the reference clock frequency multiplication assembly, one path of first reference clock signal can be multiplied into multiple paths of third reference clock signals with high spurious suppression and low phase noise.

Description

Technical Field

[0001] The utility model relates to the technical field of quantum computers, in particular to a reference clock frequency multiplication component, a quantum computing measurement and control system and a quantum computer. Background Art

[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information, and include quantum chips and quantum measurement and control machines. Both radio frequency transmission and acquisition in quantum measurement and control machines require a high-frequency reference clock signal. As the number of quantum bits integrated on a quantum chip increases, more high-frequency reference clock signals are required. The homologous reference clock signal of a quantum measurement and control machine is a low-frequency signal (e.g., a 100MHz clock signal). Therefore, it is urgent to design a frequency multiplication component to multiply the low-frequency clock signal to the high-frequency reference clock signal required by multiple channels.

[0003] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0004] The utility model aims to provide a reference clock frequency multiplication component, which can multiply a low-frequency clock signal to multiple high-frequency reference clock signals required.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] The first aspect of the utility model provides a reference clock frequency multiplication component comprising:

[0007] A frequency multiplication module, used for multiplying the first reference clock signal to obtain a second reference clock signal, wherein the frequency of the second reference clock signal is greater than the frequency of the first reference clock signal;

[0008] and a power division module, configured to power divide the second reference clock signal into multiple third reference clock signals;

[0009] Among them, the frequency multiplication module includes a plurality of first amplifiers connected in series and a signal processing unit between any two adjacent first amplifiers, at least one of the signal processing units includes a frequency multiplication element and a filter connected in series; each of the first amplifiers is used to perform power amplification processing on the input signal; each of the frequency multiplication elements is used to perform frequency amplification processing on the signal after power amplification processing, and the filter is used to perform filtering processing on the signal after frequency amplification processing.

[0010] The reference clock frequency multiplication component as described above, further, the frequency multiplication module comprises a plurality of the signal processing units, wherein at least two of the signal processing units comprise a frequency multiplication element and a bandpass filter connected in series;

[0011] The operating frequency bands of the frequency multiplication elements are different; the operating frequency bands of the filters are different.

[0012] As the reference clock frequency multiplication component as described above, further, any of the frequency multiplication elements includes a comb spectrum generator or a frequency multiplier.

[0013] The reference clock frequency multiplication component as described above, further, the power division module comprises:

[0014] A power division and amplification unit, configured to power-amplify the second reference clock signal and power-divide it into multiple paths and power-amplify the power-divided signals to obtain multiple paths of fourth reference clock signals;

[0015] A power division unit is used to power divide each of the fourth reference clock signals into multiple third reference clock signals.

[0016] The reference clock frequency multiplication component as described above, further, the power division amplification unit comprises a power divider, a second amplifier connected to the input end of the power divider, and a third amplifier connected to the output end of the power divider;

[0017] The input end of the second amplifier is electrically connected to the frequency multiplication module, and the output end of the third amplifier is electrically connected to the power division unit.

[0018] The reference clock frequency multiplication component as described above, further, the power division unit comprises a power divider;

[0019] Alternatively, the power division unit includes a plurality of cascaded power dividers.

[0020] In the reference clock frequency multiplication component as described above, further, the filter is a surface acoustic wave filter or a bandpass filter.

[0021] The second aspect of the utility model provides a quantum computing measurement and control system, comprising the above-mentioned reference clock frequency multiplication component and a signal generation module, wherein the signal generation module outputs a measurement and control signal based on a third reference clock signal provided by the reference clock frequency multiplication component.

[0022] The third aspect of the utility model provides a quantum computer, comprising the above-mentioned quantum computing measurement and control system and a quantum chip, wherein the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.

[0023] The beneficial effects of the utility model are:

[0024] The reference clock frequency multiplication component of the present application performs frequency multiplication processing through a frequency multiplication module and performs power division processing through a power division module, so as to realize frequency multiplication of a first reference clock signal (for example, a 100MHz reference clock signal) into a third reference clock signal required by multiple channels. Specifically, the frequency multiplication module includes a plurality of first amplifiers connected in series, and a signal processing unit of any two adjacent first amplifiers, and at least one of the signal processing units includes a frequency multiplication element and a bandpass filter connected in series; the input signal is power amplified by the first amplifier; the signal after power amplification is frequency amplified by the frequency multiplication element, and the signal after frequency amplification is filtered by the filter, so that the spurious suppression of the third reference clock signal required by multiple channels is high and the phase noise is low.

[0025] The quantum computing measurement and control system and quantum computer provided by the utility model both include the above-mentioned reference clock frequency multiplication component, and therefore have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural block diagram of a reference clock frequency multiplication component provided in an embodiment of the utility model;

[0027] Figure 2 A first circuit diagram of a frequency multiplication module provided by an embodiment of the utility model;

[0028] Figure 3 A second circuit diagram of the frequency multiplication module provided by an embodiment of the utility model;

[0029] Figure 4 A circuit diagram of a power division amplifier unit provided in an embodiment of the utility model;

[0030] Figure 5 A circuit diagram of a power division unit provided in an embodiment of the utility model;

[0031] In the accompanying drawings: 10, frequency multiplication module; 11, first amplifier; 12, frequency multiplication element; 121, frequency multiplier; 122, comb spectrum generator; 13, filter; 20, power division module; 21, power division amplification unit; 22, power division unit; 23, power divider; 24, second amplifier; 25, third amplifier. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0033] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0035] Figure 1 The structural block diagram of the reference clock frequency multiplication component provided by the embodiment of the utility model is as follows: Figure 1 As shown: An embodiment of the present application discloses a reference clock multiplication component, comprising: a multiplication module 10, used to multiply a first reference clock signal to obtain a second reference clock signal, the frequency of the second reference clock signal being greater than the frequency of the first reference clock signal; and a power division module 20, used to power divide the second reference clock signal into multiple third reference clock signals; wherein the multiplication module 10 comprises a plurality of first amplifiers 11 connected in series and a signal processing unit between any two adjacent first amplifiers 11, at least one of the signal processing units comprises a frequency multiplication element 12 and a filter 13 connected in series; each of the first amplifiers 11 is used to power amplify an input signal; each of the frequency multiplication elements 12 is used to frequency amplify the signal after power amplification, and the filter 13 is used to filter the signal after frequency amplification.

[0036] The reference clock frequency multiplication component of the present application performs a frequency multiplication process on the signal through a frequency multiplication module and performs a power division process on the signal through a power division module 20, so as to realize frequency multiplication of a first reference clock signal (for example, a 100MHz reference clock signal) into multiple third reference clock signals required (for example, 24 6GHz reference clock signals). Specifically, the frequency multiplication module 10 includes a plurality of first amplifiers 11 connected in series, a signal processing unit between any two adjacent first amplifiers 11, and at least one of the signal processing units includes a frequency multiplication element 12 and a bandpass filter 13 connected in series; the input signal is power amplified by the first amplifier 11; the signal after power amplification is frequency amplified by the frequency multiplication element 12, and the signal after frequency amplification is filtered by the filter 13, so that the spurious suppression of the multiple third reference clock signals required is high and the phase noise is low.

[0037] In this embodiment, the plurality of first amplifiers 11 means that the number of the first amplifiers 11 is at least 2, and the specific number is not limited, for example, 3, 4, 5, etc. are all acceptable.

[0038] In this embodiment, the number of signal processing units is related to the number of first amplifiers 11, that is, there is a signal processing unit between any two adjacent first amplifiers 11; for example, when there are two first amplifiers 11, there is one signal processing unit, and when there are three first amplifiers 11, there are two signal processing units.

[0039] In this embodiment, at least one of the signal processing units includes a frequency multiplication element 12 and a filter 13 connected in series, which means that: when there is one signal processing unit, the signal processing unit includes a frequency multiplication element 12 and a filter 13 connected in series; when there are multiple signal processing units, for example, two, one or two signal processing units may include a frequency multiplication element 12 and a filter 13 connected in series.

[0040] In some implementations of this embodiment, the frequency multiplication module 10 includes multiple signal processing units, wherein at least two of the signal processing units include a frequency multiplication element 12 and a bandpass filter 13 connected in series; the operating frequency bands of each of the frequency multiplication elements 12 are different; and the operating frequency bands of each of the filters 13 are different.

[0041] In this embodiment, the frequency multiplication module 10 includes at least two frequency multiplication elements 12 and at least two filters 13, which can filter and multiply the signal in stages. Specifically, the operating frequency bands of each of the frequency multiplication elements 12 are different, that is, the design of each frequency multiplication element 12 can focus on a specific frequency range to improve performance and accuracy. For example, when there are two frequency multiplication elements 12, the first frequency multiplication element 12 can extract the frequency multiplication of the basic frequency from the input signal, and then further multiply it through the second frequency multiplication element 12 to achieve a higher frequency multiplication factor. This hierarchical processing can reduce error accumulation and improve the overall frequency multiplication accuracy and performance. Similarly, the operating frequency bands of each of the filters 13 are different, which can achieve more accurate frequency selectivity, filter out noise or interference in a specific frequency band, and retain the signal quality within the target frequency range.

[0042] In some implementations of this embodiment, at least one signal processing unit includes a filter 13. Exemplarily, when there are multiple signal processing units, for example, two, one of the signal processing units is a frequency multiplication element 12 and a filter 13 connected in series, and the other signal processing unit is a filter 13.

[0043] In this embodiment, the specific type of the frequency multiplication element 12 is not limited, and according to actual needs, a comb spectrum generator 122 or a frequency multiplier 121 can be selected. Among them, the comb spectrum generator 122 has a low cost, and the number of frequency multiplication is flexible and adjustable, and the circuit needs to be debugged according to needs; the frequency multiplier 121 has a simple circuit and does not need to be debugged, and the number of frequency multiplication is fixed and cannot be changed.

[0044] In this embodiment, the specific type of the filter 13 is not limited. Exemplarily, the filter 13 is a surface acoustic wave filter 13 or a bandpass filter 13. Specifically, when the reference clock frequency multiplication component contains multiple filters 13, they can all be surface acoustic wave filters 13, or they can all be bandpass filters 13. Some filters 13 can also be bandpass filters 13, and the other part of filters 13 can be surface acoustic wave filters 13. The combination of bandpass filters 13 and surface acoustic wave filters 13 can optimize frequency selection performance, improve filtering efficiency, enhance system flexibility, and reduce system noise and interference. Two specific examples of the frequency multiplication module 10 are given below.

[0045] Example 1: Figure 2 The first circuit diagram of the frequency multiplication module 10 provided in the embodiment of the utility model; Figure 2 As shown, the frequency multiplication module 10 includes the following devices connected in series in sequence.

[0046] The first amplifier 11 is used to amplify the low-frequency signal (ie, the first reference clock signal) so as to drive the frequency multiplier 121 to work.

[0047] The frequency multiplier 121 is used for performing a first frequency multiplication on the low frequency signal.

[0048] The filter 13 is used to suppress the adjacent spurious signals of the desired signal frequency band. Specifically, according to the signal frequency band required for frequency doubling, a suitable bandpass filter 13 or surface acoustic wave filter 13 is selected to suppress the adjacent spurious signals.

[0049] The first amplifier 11 is used to amplify the required signal.

[0050] The filter 13 is used to suppress the adjacent spurious signals of the desired signal frequency band. Specifically, according to the signal frequency band required for frequency doubling, a suitable bandpass filter 13 or surface acoustic wave filter 13 is selected to suppress the adjacent spurious signals.

[0051] The first amplifier 11 is used to amplify the signal and is capable of driving the comb spectrum generator 122 .

[0052] The comb spectrum generator 122 is used to perform a second frequency multiplication on the signal after the first frequency multiplication so as to meet the requirement of the output signal frequency.

[0053] The filter 13 is used to filter out stray signals.

[0054] The first amplifier 11 is used to amplify the signal to obtain a second reference clock signal.

[0055] Example 2: Figure 3 The second circuit diagram of the frequency multiplication module 10 provided in the embodiment of the utility model; Figure 3 As shown, the frequency multiplication module 10 includes the following devices connected in series in sequence.

[0056] The first amplifier 11 is used to amplify the low-frequency signal (ie, the first reference clock signal) so as to drive the comb spectrum generator 122 to work.

[0057] The comb spectrum generator 122 is used to perform a first frequency multiplication on the low-frequency signal.

[0058] The filter 13 is used to suppress the adjacent spurious signals of the desired signal frequency band. Specifically, according to the signal frequency band required for frequency doubling, a suitable bandpass filter 13 or surface acoustic wave filter 13 is selected to suppress the adjacent spurious signals.

[0059] The first amplifier 11 is used to amplify the required signal.

[0060] The filter 13 is used to suppress the adjacent spurious signals of the desired signal frequency band. Specifically, according to the signal frequency band required for frequency doubling, a suitable bandpass filter 13 or surface acoustic wave filter 13 is selected to suppress the adjacent spurious signals.

[0061] The first amplifier 11 is used to amplify the signal and is capable of driving the comb spectrum generator 122 .

[0062] The comb spectrum generator 122 is used to perform a second frequency multiplication on the signal after the first frequency multiplication so as to meet the requirement of the output signal frequency.

[0063] The filter 13 is used to filter out stray signals.

[0064] The first amplifier 11 is used to amplify the signal to obtain a second reference clock signal.

[0065] In some implementations of this embodiment, the power division module 20 includes: a power division amplifier unit 21, used to power amplify the second reference clock signal and power divide it into multiple paths and power amplify the power divided signal to obtain multiple fourth reference clock signals; a power division unit 22, used to power divide each of the fourth reference clock signals into multiple third reference clock signals.

[0066] By setting up a power division amplifier unit 21 and performing power division processing on the signal before the input power division unit 22, it can be ensured that the multi-channel input signals entering the power division unit 22 have sufficient strength and stability, thereby ensuring the normal operation of the power division unit 22 and the power balance between the output ports, and further ensuring the stability of the final multi-channel third reference clock signal performance.

[0067] In some implementations of this embodiment, the power division amplifier unit 21 includes a power divider 23, a second amplifier 24 connected to the input end of the power divider 23, and a third amplifier 25 connected to the output end of the power divider 23; the input end of the second amplifier 24 is electrically connected to the frequency multiplication module 10, and the output end of the third amplifier 25 is electrically connected to the power division unit 22.

[0068] The power divider amplification unit 21 in this embodiment is provided with a second amplifier 24. Amplification processing is performed before the signal is input into the power divider 23 to ensure that the input signal has sufficient strength and stability, thereby ensuring the normal operation of the power divider 23 and the power balance between the output ports. This method of pre-amplifying the signal can improve the overall performance of the system, reduce the loss of the signal inside the power divider 23, and ensure that the required power level is obtained at each output port of the power divider 23; by providing a third amplifier 25 at the output port of the power divider 23, it is ensured that the signal output to the power divider unit 22 has sufficient strength, thereby ensuring the normal operation of the power divider unit 22.

[0069] In this embodiment, the type of the power divider 23 in the power divider amplifier unit 21 is not specifically limited, and can be one of a two-divider, a three-divider, a four-divider, a six-divider, etc. For example, Figure 4The circuit diagram of the power division amplifier unit 21 provided in the embodiment of the utility model; Figure 4 As shown, the power division amplification unit 21 includes a second amplifier 24, a power divider 23 and a third amplifier 25 connected in series in sequence, wherein the power divider 23 is a four-divider, and each output port thereof is connected to a third amplifier 25.

[0070] Figure 5 The circuit diagram of the power division unit 22 provided in the embodiment of the utility model; Figure 5 As shown, in some implementations of this embodiment, the power division unit 22 includes a power divider 23; or, the power division unit 22 includes a plurality of cascaded power dividers 23; the type of the power divider 23 is not specifically limited here, and can be one of a two-divider, a three-divider, a four-divider, a six-divider, etc.; for example, Figure 5 As shown, the power division unit 22 includes a cascaded two-way divider and a three-way divider, thereby achieving a one-to-six effect.

[0071] Based on the same application concept, an embodiment of the present application also proposes a quantum computing measurement and control system, including the above-mentioned reference clock frequency multiplication component, and a signal generation module, wherein the signal generation module outputs a measurement and control signal based on a third reference clock signal provided by the reference clock frequency multiplication component.

[0072] The quantum computing measurement and control system of the present application includes the above-mentioned reference clock frequency multiplication component, and therefore has the same beneficial effects as the above-mentioned reference clock frequency multiplication component, which will not be repeated here.

[0073] Based on the same application concept, an embodiment of the present application also proposes a quantum computer, including the above-mentioned quantum computing measurement and control system and a quantum chip, wherein the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.

[0074] The quantum computer of the present application includes the above-mentioned reference clock frequency multiplication component, and therefore has the same beneficial effects as the above-mentioned reference clock frequency multiplication component, which will not be described in detail here.

[0075] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0076] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A reference clock frequency multiplication component, characterized in that: include: A frequency multiplication module, used for multiplying the first reference clock signal to obtain a second reference clock signal, wherein the frequency of the second reference clock signal is greater than the frequency of the first reference clock signal; and a power division module, configured to power divide the second reference clock signal into multiple third reference clock signals; Among them, the frequency multiplication module includes a plurality of first amplifiers connected in series and a signal processing unit between any two adjacent first amplifiers, at least one of the signal processing units includes a frequency multiplication element and a filter connected in series; each of the first amplifiers is used to perform power amplification processing on the input signal; each of the frequency multiplication elements is used to perform frequency amplification processing on the signal after power amplification processing, and the filter is used to perform filtering processing on the signal after frequency amplification processing.

2. The reference clock frequency multiplication component according to claim 1, characterized in that: The frequency multiplication module comprises a plurality of the signal processing units, wherein at least two of the signal processing units comprise a frequency multiplication element and a bandpass filter connected in series; The operating frequency bands of the frequency multiplication elements are different; the operating frequency bands of the filters are different.

3. The reference clock frequency multiplication component according to claim 1, characterized in that: Any of the frequency multiplication elements described herein may include a comb generator or a frequency multiplier.

4. The reference clock frequency multiplication component according to claim 1, characterized in that: The power division module comprises: A power division and amplification unit, configured to power-amplify the second reference clock signal and power-divide it into multiple paths and power-amplify the power-divided signals to obtain multiple paths of fourth reference clock signals; A power division unit is used to power divide each of the fourth reference clock signals into multiple third reference clock signals.

5. The reference clock frequency multiplication component according to claim 4, characterized in that: The power divider amplification unit includes a power divider, a second amplifier connected to the input end of the power divider, and a third amplifier connected to the output end of the power divider; The input end of the second amplifier is electrically connected to the frequency multiplication module, and the output end of the third amplifier is electrically connected to the power division unit.

6. The reference clock frequency multiplication component according to claim 4, characterized in that: The power division unit includes a power divider.

7. The reference clock frequency multiplication component according to claim 4, characterized in that: The power division unit includes a plurality of cascaded power dividers.

8. The reference clock frequency multiplication component according to claim 1, characterized in that: The filter is a surface acoustic wave filter or a bandpass filter.

9. A quantum computing measurement and control system, characterized in that: It comprises a reference clock frequency multiplication component as described in any one of claims 1 to 8, and a signal generation module, wherein the signal generation module outputs a measurement and control signal based on a third reference clock signal provided by the reference clock frequency multiplication component.

10. A quantum computer, characterized in that: It includes the quantum computing measurement and control system and quantum chip as described in claim 9, and the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.

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