Hardware driving circuit for reconfigurable antenna or reflective surface array

Abstract

The utility model discloses a hardware drive circuit of a reconfigurable antenna or a reflective surface array, which is connected with a reconfigurable antenna unit or a reflective surface array unit, and comprises a plurality of displacement buffers with serial input and parallel output, the plurality of displacement buffers are connected in a manner that front-stage serial output pins are connected with rear-stage serial input pins, and the displacement buffers are connected with the reconfigurable antenna unit or the reflective surface array unit. Each displacement buffer comprises a plurality of parallel output pins, and the reconfigurable antenna unit or the reflective surface array unit is connected with the plurality of parallel output pins in the same displacement buffer through a direct current bias interface. The circuit can be applied to a reconfigurable antenna or reflective surface array driving device based on diode control, a control circuit board is improved, the occupation of IO ports is greatly reduced by using a serial-to-parallel circuit, so that the occupation of a core processor is reduced, an expensive FPGA (Field Programmable Gate Array) can be replaced by a low-price single chip microcomputer, and the cost is reduced. Therefore, the cost of the hardware driving device of the reconfigurable antenna or the reflective surface array is greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of hardware driving circuits, and in particular to a hardware driving circuit of a reconfigurable antenna or a reflective surface array. Background Art

[0002] At present, most reconfigurable antenna or reflective surface array driving circuits, especially those based on diode control, drive each reconfigurable antenna unit or reflective surface array unit with two bias lines. Due to the need for multiple IO ports, the voltage and current required for each unit of the reconfigurable antenna or reflective surface array are obtained by directly outputting or simply processing the IO port of the FPGA. Although this control method is simple, taking a 9*92-bits reflective surface array as an example, each unit requires 2 bias lines for control, a total of 144 control lines are required, and at least 144 IO ports are required, resulting in a large waste of controller resources. Therefore, the cost of the hardware control device of the reconfigurable antenna or reflective surface array remains high and is not conducive to fault debugging in large-scale reconfigurable antennas or reflective surface arrays. Summary of the invention

[0003] In view of the above problems, the utility model provides a hardware driving circuit for a reconfigurable antenna or a reflective surface array, especially a reconfigurable antenna array (such as a pixel array antenna) or a reconfigurable intelligent surface (such as a RIS) driving circuit based on diode control, which aims to improve the control circuit board and use a serial-to-parallel circuit to greatly reduce the occupancy of IO ports, thereby reducing the occupancy of the core processor.

[0004] The utility model provides a hardware driving circuit of a reconfigurable antenna or a reflecting surface array, which is connected to a reconfigurable antenna unit or a reflecting surface array unit, and includes: a plurality of displacement buffers with serial input and parallel output, wherein the plurality of displacement buffers are connected in a manner of accessing a front-stage serial output pin to a rear-stage serial input pin, each displacement buffer includes a plurality of parallel output pins, and the reconfigurable antenna unit or the reflecting surface array unit is connected to a plurality of parallel output pins in the same displacement buffer via a DC bias interface.

[0005] A further technical solution of the utility model is: the displacement buffer is a 74HC595 chip.

[0006] A further technical solution of the utility model is that each parallel output pin of the displacement buffer is connected in series with a current limiting resistor and then connected to the reconfigurable antenna unit or the reflective surface array unit.

[0007] A further technical solution of the utility model is: the value range of the current limiting resistor is 820Ω~1200Ω.

[0008] A further technical solution of the utility model is: the 74HC595 chip is powered by 4V.

[0009] A further technical solution of the utility model is that the GND end of the reconfigurable antenna unit or the reflecting surface array unit is connected to a 1.5V bias power supply.

[0010] The utility model provides a hardware driving circuit for a reconfigurable antenna or a reflective surface array, which can be applied to a reconfigurable antenna array (such as a pixel array antenna) or a reflective surface array (such as a RIS) driving device based on diode control, improves a control circuit board, uses a serial-to-parallel circuit to greatly reduce the occupation of IO ports, thereby reducing the occupation of a core processor, and can replace an expensive FPGA with a low-priced single-chip microcomputer (such as Ardunio mega 2560), thereby greatly reducing the cost of the hardware driving device for the reconfigurable antenna or reflective surface array.

[0011] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present utility model, and together with the description are used to explain the principle of the present utility model.

[0013] Figure 1 It is a principle block diagram of a hardware driving circuit of a reconfigurable antenna or reflective surface array provided by an embodiment of the utility model;

[0014] Figure 2 It is a schematic diagram of a hardware driving circuit of a reconfigurable antenna or a reflective surface array provided by an embodiment of the utility model;

[0015] Figure 3 This is a schematic diagram of an interface for connecting a reflective surface array unit and a hardware driving circuit provided by an embodiment of the utility model;

[0016] Figure 4 It is a schematic diagram of an interface for connecting a reconfigurable antenna unit and a hardware driving circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0018] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0019] like Figure 1 to Figure 4 As shown, the hardware driving circuit of the reconfigurable antenna or reflective surface array proposed by the present invention has the following embodiments:

[0020] like Figure 1 As shown, the hardware driving circuit of the reconfigurable antenna or the reflective surface array is connected to the reflective surface array unit or the reconfigurable antenna unit, and includes: n displacement buffers with serial input and parallel output, the n displacement buffers are connected in a manner of connecting the front-stage serial output pin to the rear-stage serial input pin, and each displacement buffer includes at least two parallel output pins ( Figure 1 The parallel output pins are Q1~Qm), such as Figure 3 , Figure 4 As shown, the reflective surface array unit or the reconfigurable antenna unit ( Figure 1 The first embodiment (not shown) is connected to multiple parallel output pins in the same displacement buffer through a DC bias interface (Bias1 to Bias n), Figure 1 The STCP pin is the output memory latch clock line, the SHCP pin is the data input clock line, the DS pin is the serial data input, and the QS pin is the serial data output.

[0021] like Figure 2 As shown, in a preferred embodiment, the displacement buffer is a 74HC595 chip.

[0022] like Figure 2 As shown, in a preferred embodiment, each parallel output pin of the displacement register is connected in series with a current limiting resistor and then connected to the reflective surface array unit ( Figure 2 An example is a RIS unit) connection.

[0023] like Figure 2 As shown, in a preferred embodiment, the value range of the current limiting resistor is 820Ω to 1200Ω.

[0024] like Figure 2 As shown, in a preferred embodiment, the 74HC595 chip is powered by 4V.

[0025] like Figure 3As shown, in a preferred embodiment, the GND terminal of the RIS unit is connected to a 1.5V bias power supply.

[0026] like Figure 4 As shown, in a preferred embodiment, the GND terminals of other diode-controlled reconfigurable antenna arrays are connected to an external power supply.

[0027] During the specific implementation process, by reasonably optimizing the hardware control circuit of the existing reconfigurable antenna or reflective surface array, a serial-to-parallel digital circuit is used to uniformly control multiple units of the reconfigurable antenna or reflective surface array, thereby reducing the demand for IO ports and achieving the effect of reducing costs and increasing efficiency.

[0028] In the specific implementation process, Figure 2 , Figure 3 , Figure 4 As shown, the embodiment takes the 74HC595 chip as an example, and realizes the cascading of multiple chips by connecting the front-stage serial output pin with the rear-stage serial input pin, realizing the serial-to-parallel mode of single input-multiple output, greatly reducing the required IO ports, and after completing the shift assignment of all output ports, the output is fixed with a latch clock, thereby realizing a driving circuit with a minimum of only 3 IO ports. Considering the low phase switching rate of the actual reconfigurable antenna or reflective surface array and the demand for very few IO ports, the core controller is changed from multiple FPGAs to a single microcontroller, which greatly reduces the hardware cost.

[0029] In the implementation process, taking the 74HC595 chip as an example, each 74HC595 chip has eight parallel output pins. Each unit of the reconfigurable antenna or reflecting surface array requires two DC bias lines, Bias1 and Bias2, respectively. Therefore, each chip can correspond to 4 reconfigurable antenna units or reflecting surface array units.

[0030] To avoid excessive output current, each parallel pin output needs to be connected in series with a current limiting resistor. At the same time, since the output current of the 74HC595 chip is small, when the current limiting resistor is too small, it may cause the GND potential on the reconfigurable antenna or reflective surface array board to be pulled up / down. Taking all the above into consideration, the value range of each current limiting resistor is approximately 820 ohms to 1200 ohms.

[0031] The datasheet of the 74HC595 chip shows that the 74HC595 chip has a minimum voltage requirement. Combined with the voltage and current required by the diode in the reconfigurable antenna unit or the reflective surface array unit, the 74HC595 chip is powered by 4V, and the voltage of the parallel output end after loading is approximately 0V and 3V; at the same time, the bias voltage required for the single diode control in the reflective surface array unit is approximately symmetrical positive and negative 1.5V, so when using this circuit for power supply, it is also necessary to connect the GND end on the reflective surface array to the +1.5V bias power supply to obtain symmetrical positive and negative DC bias voltages.

[0032] The hardware driving circuit of a reconfigurable antenna or a reflective surface array provided in the above embodiments can be applied to a driver of a reconfigurable antenna array (such as a pixel array antenna) or a reflective surface array (such as a RIS) based on diode control. The control circuit board is improved, and a serial-to-parallel circuit is used to greatly reduce the occupancy of the IO port, thereby reducing the occupancy of the core processor, and the expensive FPGA can be replaced with a lower-priced single-chip microcomputer (such as Ardunio mega 2560), thereby greatly reducing the cost of the hardware driving device of the reconfigurable antenna or reflective surface array.

[0033] In this document, the terms "comprises," "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, such that a step or method that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such step or method.

[0034] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A hardware driving circuit of a reconfigurable antenna or a reflective surface array, connected to a reconfigurable antenna unit or a reflective surface array unit, characterized in that: include: A plurality of displacement buffers with serial input and parallel output, wherein the plurality of displacement buffers are connected by connecting a front-stage serial output pin to a rear-stage serial input pin, each displacement buffer comprises a plurality of parallel output pins, and the reconfigurable antenna unit or the reflection surface array unit is connected to the plurality of parallel output pins in the same displacement buffer via a DC bias interface.

2. The hardware driving circuit of the reconfigurable antenna or reflective surface array according to claim 1, characterized in that: The displacement buffer is a 74HC595 chip.

3. The hardware driving circuit of the reconfigurable antenna or reflective surface array according to claim 2, characterized in that: Each parallel output pin of the displacement register is connected in series with a current limiting resistor and then connected to the reconfigurable antenna unit or the reflective surface array unit.

4. The hardware driving circuit of the reconfigurable antenna or reflective surface array according to claim 3, characterized in that: The value range of the current limiting resistor is 820Ω~1200Ω.

5. The hardware driving circuit of the reconfigurable antenna or reflective surface array according to claim 4, characterized in that: The 74HC595 chip is powered by 4V.

6. The hardware driving circuit of the reconfigurable antenna or reflective surface array according to claim 1, characterized in that: The GND terminal of the reflective surface array unit is connected to a 1.5V bias power supply.

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