Symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure

Abstract

The utility model relates to the technical field of silicon carbide, in particular to a symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure, which comprises two symmetrically arranged substrates, the inner sides of the substrates are connected with DBC copper plates, the inner sides of the DBC copper plates are connected with AlN ceramic plates, the AlN ceramic plates are connected with power terminals through the DBC copper plates, and the power terminals are connected with the power terminals through the DBC copper plates. The DBC copper plate on the upper side is connected with a buffer layer molybdenum column, the buffer layer molybdenum column is connected with a chip through a nano-silver sintering layer, the middle part of the DBC copper plate is provided with a SiC MOSFET grid electrode copper column, the SiC MOSFET grid electrode copper column is connected with the chip, the SiC MOSFET grid electrode copper column is connected with a SiC MOSFET grid electrode wiring terminal, the center of the SiC MOSFET grid electrode copper column is provided with an NTC temperature sensor, and the NTC temperature sensor is connected with the chip through a nano-silver sintering layer. And the NTC temperature sensor is connected with the NTC temperature sensor connecting terminal. The silicon carbide multi-chip packaging structure can reduce the thermal coupling effect between the chips of the existing silicon carbide multi-chip packaging structure, reduces the thermal resistance of the power module, and is beneficial to multi-chip junction temperature monitoring.

Description

Technical Field

[0001] The utility model relates to the technical field of silicon carbide, in particular to a symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure. Background Art

[0002] With the rapid development of new energy vehicles, high power density and high reliability double-sided heat dissipation silicon carbide power modules have received widespread attention. Compared with traditional silicon-based devices, silicon carbide devices have wider bandgap width, higher temperature resistance, better thermal conductivity, smaller on-resistance, higher carrier saturation rate and smaller chip area, and are widely used in high-voltage, high-frequency and high-power density applications of new energy vehicles.

[0003] Due to the integration and miniaturization of power modules, high power density leads to increasingly serious thermal coupling effects between chips, which leads to a sharp increase in the junction temperature of the chip. Long-term high-temperature operation will bring severe challenges to the reliability and safety of power devices. At present, the packaging of traditional silicon carbide power modules mostly adopts the form of single-sided heat dissipation. The bottom surface of the chip is welded on the DBC substrate, the top surface electrode of the chip is connected by bonding wires, and the chip is protected by encapsulation sealant on the top surface. In this method, the chip has insufficient heat dissipation in the case of multi-chip parallel connection, high temperature, and high power density, and the junction temperature is high, and long-term operation lacks certain reliability. Even though different double-sided heat dissipation packaging structures have been proposed, the thermal coupling effect between multi-chip parallel connection still has an important impact on the increase of chip junction temperature. The miniaturization of the packaging structure also poses certain challenges to the monitoring of chip junction temperature. Summary of the invention

[0004] The technical problem to be solved by the utility model is to provide a symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure.

[0005] The utility model solves the above technical problem by providing a symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure, comprising two symmetrically arranged substrates, the inner side of the substrate is connected with a DBC copper plate, the inner side of the DBC copper plate is connected with an AlN ceramic plate, the AlN ceramic plate is connected with a power terminal through the DBC copper plate, the upper DBC copper plate is connected with a buffer layer molybdenum column, the buffer layer molybdenum column is connected to the chip through a nano silver sintering layer, a SiC MOSFET gate copper column is provided in the middle of the DBC copper plate, the SiC MOSFET gate copper column is connected to the chip, the SiC MOSFET gate copper column is connected to the SiC MOSFET gate wiring terminal, an NTC temperature sensor is provided in the center of the SiC MOSFET gate copper column, and the NTC temperature sensor is connected to the NTC temperature sensor connection terminal.

[0006] As a preferred technical solution of the present utility model, the substrate is made of copper.

[0007] As a preferred technical solution of the utility model, the outer sides of the substrates are respectively connected to the heat sinks.

[0008] As a preferred technical solution of the utility model, the substrate, the AlN ceramic plate, the DBC copper plate, the buffer layer molybdenum column, the chip, and the NTC temperature sensor are all connected by a nano-silver sintered layer.

[0009] As a preferred technical solution of the utility model, there are 6 molybdenum pillars in the buffer layer, which are arranged at equal intervals.

[0010] As a preferred technical solution of the utility model, the angle between the center of the adjacent buffer layer molybdenum columns and the center of the NTC temperature sensor is 60°.

[0011] As a preferred technical solution of the present invention, the chip is a SiC MOSFET or FRD chip, and the power terminal is a SiC MOSFET or FRD chip power terminal.

[0012] As a preferred technical solution of the utility model, the substrate, AlN ceramic plate, DBC copper plate and chip are all packaged in a ceramic housing and sealed with epoxy resin.

[0013] Since the utility model adopts such a structure, it has the following beneficial effects:

[0014] 1. The utility model adopts a double-sided heat dissipation structure. Based on the heat transfer mechanism within and between different material layers, the minimum distance between chips is set on the basis of fully saving materials to avoid the thermal coupling effect between chips and improve the heat dissipation performance of the chip;

[0015] 2. The utility model adopts a truncated cone structure design for each material layer, which can avoid the generation of a high electric field strength at the tip of each layer and improve the reliability of the power module;

[0016] 3. The utility model adopts a dot-symmetrical structure and uses an NTC temperature sensor to establish a thermal impedance network model, which minimizes the thermal coupling effect between chips when monitoring the junction temperature of the power module chip, has a smaller thermal resistance, and improves the accuracy of the power module junction temperature monitoring;

[0017] 4. The utility model can optimize the spatial position of the chip according to the requirements of different numbers of multi-chip parallel connection. The packaging method can package a larger number of parallel chips, which is conducive to improving the current level of the power module;

[0018] 5. The utility model adopts a buffer layer molybdenum column structural design on both sides of the chip to balance the thickness of different chips so that different chips can be packaged in the same module. The buffer layer molybdenum column can reduce the stress caused by thermal expansion of the chip and improve the reliability of the power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the single chip packaging structure of the utility model.

[0020] Figure 2 It is a right side view of the single chip package of the utility model.

[0021] Figure 3 It is an explosion schematic diagram of the utility model.

[0022] Figure 4 It is a schematic diagram of the substrate structure of the utility model.

[0023] Figure 5 It is a top view of the substrate structure of the present utility model.

[0024] In the figure: 1 is a chip, 2 is a buffer layer molybdenum column, 3 is an AlN ceramic plate, 4 is a nano-silver sintered layer, 5 is a DBC copper plate, 6 is a SiC MOSFET gate copper column, 7 is an NTC temperature sensor, 8 is a SiC MOSFET gate terminal, 9 is an NTC temperature sensor terminal, 10 is a substrate, and 11 is a power terminal. DETAILED DESCRIPTION

[0025] The utility model is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like Figures 1 to 5As shown, a symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure of the utility model includes two symmetrically arranged substrates 10, a DBC copper plate 5 is connected to the inner side of the substrate 10, an AlN ceramic plate 3 is connected to the inner side of the DBC copper plate 5, the AlN ceramic plate 3 is connected to a power terminal 11 through the DBC copper plate 5, the upper DBC copper plate 5 is connected to a buffer layer molybdenum column 2, the buffer layer molybdenum column 2 is connected to the chip 1 through a nano silver sintering layer 4, a SiC MOSFET gate copper column 6 is provided in the middle of the DBC copper plate 5, the SiC MOSFET gate copper column 6 is connected to the chip 1, the SiC MOSFET gate copper column 6 is connected to the SiC MOSFET gate terminal 8, an NTC temperature sensor 7 is provided in the center of the SiC MOSFET gate copper column 6, the NTC temperature sensor 7 is connected to the NTC temperature sensor connection terminal 9, the chip 1 is a SiC MOSFET or FRD chip, and the power terminal 11 is a SiC MOSFET or FRD chip power terminal. The utility model adopts a dot-symmetric structure and uses an NTC temperature sensor 7 to establish a thermal impedance network model, which minimizes the impact of thermal coupling between chips when monitoring the junction temperature of the power module chip, has a smaller thermal resistance, and improves the accuracy of the power module junction temperature monitoring; each material layer adopts a truncated cone structure design, which can avoid the generation of a high electric field strength at the tip of each layer, thereby improving the reliability of the power module.

[0027] In the present invention, the substrate 10 is made of copper, and the outer sides of the substrate 10 are connected to the heat sinks. The substrate 10 made of copper adopts a double-sided heat dissipation structure, and based on the heat transfer mechanism within and between different material layers, the minimum distance between the chips is set on the basis of fully saving materials, so as to avoid the thermal coupling effect between the chips and improve the heat dissipation performance of the chips.

[0028] Furthermore, in the present invention, the substrate 10, the AlN ceramic plate 3, the DBC copper plate 5, the buffer layer molybdenum column 2, the chip 1, and the NTC temperature sensor 7 are all connected by a nano-silver sintered layer.

[0029] The utility model further has 6 buffer layer molybdenum pillars 2, which are arranged at equal intervals, and the angle between the center of the adjacent buffer layer molybdenum pillars 2 and the center of the NTC temperature sensor 7 is 60°. There are 6 corresponding chips 1, and the chip distribution structure of the silicon carbide multi-chip parallel connection adopts circular point symmetry, and the substrate size is adjusted according to the different number of parallel chips. Figure 4 It is a 6-chip parallel structure, including 3 SiC MOSFETs and 3 FRD chips, and the angle between the centers of adjacent chips and the dots is 60 degrees.

[0030] In the present invention, the substrate 10, the AlN ceramic plate 3, the DBC copper plate 5 and the chip 1 are all packaged in a ceramic housing and sealed with epoxy resin.

[0031] The description and application of the utility model here are illustrative and are not intended to limit the scope of the utility model to the above-described embodiments. Variations and changes of the embodiments disclosed here are possible, and the actual replacement of the embodiments and the various components equivalent to those of ordinary skill in the art are well known. It should be clear to those skilled in the art that the utility model can be implemented in other forms, structures, arrangements, proportions, and with other elements, materials, and components without departing from the spirit or essential features of the utility model. Other variations and changes can be made to the embodiments disclosed here without departing from the spirit or essential features of the utility model.

Claims

1. A symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure, characterized by: The invention comprises two symmetrically arranged substrates (10), wherein a DBC copper plate (5) is connected to the inner side of the substrate (10), wherein an AlN ceramic plate (3) is connected to the inner side of the DBC copper plate (5), wherein the AlN ceramic plate (3) is connected to a power terminal (11) via the DBC copper plate (5), wherein the upper DBC copper plate (5) is connected to a buffer layer molybdenum column (2), wherein the buffer layer molybdenum column (2) is connected to a chip (1) via a nano silver sintered layer (4), wherein a SiC MOSFET gate copper column (6) is provided in the middle of the DBC copper plate (5), wherein the SiC MOSFET gate copper column (6) is connected to the chip (1), wherein the SiC MOSFET gate copper column (6) is connected to a SiC MOSFET gate wiring terminal (8), wherein an NTC temperature sensor (7) is provided in the middle of the SiC MOSFET gate copper column (6), wherein the NTC temperature sensor (7) is connected to an NTC temperature sensor connection terminal (9).

2. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 1 is characterized by: The substrate (10) is made of copper.

3. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 1 is characterized by: The outer sides of the substrates (10) are respectively connected to heat sinks.

4. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 1 is characterized by: The substrate (10), the AlN ceramic plate (3), the DBC copper plate (5), the buffer layer molybdenum column (2), the chip (1), and the NTC temperature sensor (7) are all connected by a nano-silver sintering layer.

5. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 1 is characterized by: There are six buffer layer molybdenum columns (2), which are arranged at equal intervals.

6. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 5 is characterized by: The angle between the center of the adjacent buffer layer molybdenum column (2) and the center of the NTC temperature sensor (7) is 60°.

7. The symmetrical double-sided heat dissipation silicon carbide multi-chip parallel packaging structure according to claim 1 is characterized by: The chip (1) is a SiC MOSFET or FRD chip, and the power terminal (11) is a SiC MOSFET or FRD chip power terminal.

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