SiC VDMOSFET device for power amplifier device battery management
By plugging U-shaped sheets and sheets into SiC VDMOSFET devices for heat conduction and convective heat dissipation, the problem of insufficient heat dissipation of the device is solved and the stability and service life of the device are improved.
Patent Information
- Application Number
- CN202421751416.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-23
AI Technical Summary
In the battery management of amplifier equipment, the reliability of SiC VDMOSFET devices is affected due to insufficient heat dissipation, the increase in temperature leads to a decrease in resistance, shortened service life, aging of materials, and damage to components.
By inserting U-shaped sheets and thin sheets in the long grooves on both sides of the N-drift region and the N+ substrate, fixing them with thermal conductivity, aluminum foil thermal conductivity gaskets with high thermal conductivity perform heat conduction and convection heat dissipation, improving the heat dissipation effect of the device.
It effectively improves the heat dissipation effect of SiC VDMOSFET devices, maintains the stability of the device, extends the service life, and improves safety and reliability.
Smart Images
Figure CN222867671U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of VDMOSFET devices, and more specifically discloses a SiC VDMOSFET device for battery management of power amplifier equipment. Background Art
[0002] With the development of microelectronic semiconductor technology, the world has ushered in the era of "cores". With the explosion of the IC industry, electronic technology science will enter a new chapter. In recent years, new devices have emerged in an endless stream and played a huge role in various fields. Metal oxide semiconductor vertical double channel field effect transistor (VDMOSFET for short). VDMOSFET is a product that emerged in response to market demand and is used in the driving circuits of power switching devices and power amplifier devices. The SiC VDMOSFET structure is closely related to the characteristics of silicon carbide (SiC) materials. As a typical representative of the third generation of semiconductor materials, SiC has the characteristics of wide bandgap, high frequency, and high power.
[0003] Nowadays, with the increasing proportion of power amplifier equipment in the market, the performance and reliability requirements of SiC VDMOSFET devices are getting higher and higher. The reliability of SiC VDMOSFET devices is related to the safety of power amplifier equipment. Since SiC VDMOSFET devices used in power amplifier equipment battery management do not convert 100% of the injected current into output photoelectrons when working, part of it will be lost as energy in the form of heat. If a large amount of heat continues to accumulate and cannot be removed in time, it will have many adverse effects on the performance of components. Generally speaking, the resistance value decreases with the increase of temperature, which reduces the service life of the device, deteriorates the performance, ages the material, and damages the components; in addition, high temperature will also cause stress deformation of the material, reduce reliability, and cause device malfunction. Summary of the invention
[0004] The utility model provides a SiC VDMOSFET device for battery management of power amplifier equipment, which can solve the problem that the reliability of the SiC VDMOSFET device is affected due to insufficient heat dissipation.
[0005] In order to solve the above technical problems, according to one aspect of the utility model, more specifically, a SiC for battery management of power amplifier equipment A VDMOSFET device comprises an N+ substrate, a gate and a source, wherein the N+ substrate is made of silicon carbide, a buffer layer is grown on the upper surface of the N+ substrate, an N-drift region is epitaxially grown on the upper surface of the buffer layer, a second long groove is provided on the left and right sides of the N-drift region, a first long groove is provided on the left and right sides of the N+ substrate, and a U-shaped sheet is inserted into the inner side walls of the first long groove and the second long groove on the same side, and the U-shaped sheet is fixed to the first long groove and the second long groove by heat dissipation silicone grease, a plurality of thin sheets are welded and formed on the inner side of the U-shaped sheet, a P body region is low-doped inside the N-drift region, and N+ regions are highly doped on the left and right sides of the P body region, a P+ region is doped inside the P body region near the two N+ regions, and the depth of the P+ region is greater than the depth of the N+ region, the source is provided on the upper surface of the N-drift region, a silicon dioxide oxide insulating layer is embedded inside the source, and the gate is wrapped inside the silicon dioxide oxide insulating layer.
[0006] In some embodiments, as a preferred technical solution, the N+ region, the P+ region, and the P body region are short-circuited with the source at the same time.
[0007] In some embodiments, as a preferred technical solution, the thin sheet and the U-shaped sheet are made of the same material, both are aluminum foil thermal pads, but have different shapes.
[0008] In some embodiments, as a preferred technical solution, the thickness of the buffer layer is 3 microns.
[0009] In some embodiments, as a preferred technical solution, a drain is etched on the back side of the N+ substrate.
[0010] In some embodiments, as a preferred technical solution, the buffer layer is a highly doped P+ region, and the buffer layer forms a PN junction with the N+ substrate.
[0011] In some embodiments, as a preferred technical solution, the corners of the P body region have curvatures.
[0012] The beneficial effects of the SiC VDMOSFET device for battery management of power amplifier equipment in the utility model are:
[0013] In the utility model, a U-shaped sheet is inserted into the long grooves on both sides of the N-drift region and the N+ substrate, a part of the U-shaped sheet is in the VDMOSFET device, and the other part is exposed to the outside, and a plurality of thin sheets with equal thickness are arranged on the inner side of the U-shaped sheet. The thin sheets and the U-shaped sheet are specifically aluminum foil thermal conductive pads, which have excellent thermal conductivity and high thermal conductivity. Then, when used in the VDMOSFET device, the heat in the device is conducted to the U-shaped sheet and the thin sheet, and a part of the U-shaped sheet is exposed, and the thin sheet is exposed to the outside, which is not in direct contact with the device. The U-shaped sheet and the thin sheet can exchange heat by natural convection, and the heat dissipation effect is good, which is beneficial to the stable performance of the semiconductor device, the increased service life, and the improved safety.
[0014] In the utility model, the buffer layer is a highly doped P+ region, and the buffer layer forms a PN junction with the N+ substrate, so that when the VDMOSFET device is turned on, minority carriers are emitted from the buffer layer to the N-drift region, thereby modulating the conductivity of the drift region, so that the device has a strong current-carrying capacity, and solves the contradiction between the pursuit of high withstand voltage and the pursuit of low on-state resistance in the N-drift region that cannot be solved in the power VDMOSFET. In addition, the on-current of the device is weakened, reducing heat dissipation, and can improve the reliability and stability of the VDMOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0016] Figure 1 It is a structural schematic diagram of the utility model.
[0017] In the figure: 1, N+ region; 2, P+ region; 3, source; 4, silicon dioxide oxide insulating layer; 5, gate; 6, P body region; 7, N-drift region; 8, buffer layer; 9, N+ substrate; 10, drain; 11, second long groove; 12, U-shaped sheet; 13, thin sheet; 14, first long groove. DETAILED DESCRIPTION
[0018] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.
[0019] According to the attached Figure 1, a SiC VDMOSFET device for battery management of power amplifier equipment is provided, comprising an N+ substrate 9, a gate 5 and a source 3, the N+ substrate 9 is made of silicon carbide, a buffer layer 8 is grown on the upper surface of the N+ substrate 9, an N-drift region 7 is epitaxially grown on the upper surface of the buffer layer 8, a second long groove 11 is opened on the left and right sides of the N-drift region 7, a first long groove 14 is opened on the left and right sides of the N+ substrate 9, and a U-shaped piece 12 is inserted into the inner side wall of the first long groove 14 and the second long groove 11 on the same side, and the U-shaped piece 12 is connected to the first long groove 14 and the second long groove 11 1 is fixed by heat dissipation silicone grease, a plurality of thin sheets 13 are welded on the inner side of the U-shaped sheet 12, the inside of the N-drift region 7 is lowly doped with a P body region 6, and the left and right sides of the inside of the P body region 6 are highly doped with N+ regions 1, the inside of the P body region 6 is doped with a P+ region 2 near the two N+ regions 1, and the depth of the P+ region 2 is greater than the depth of the N+ region 1, the upper surface of the N-drift region 7 is provided with a source 3, the inside of the source 3 is embedded with a silicon dioxide oxide insulating layer 4, and the inside of the silicon dioxide oxide insulating layer 4 is wrapped with a gate 5.
[0020] The thickness of the sheet 13 is 0.5 mm, and the length and width are 3 mm and 2 cm respectively. The larger the area of the sheet 13 and the smaller the thickness of the material, the greater the thermal conductivity coefficient can be, which is conducive to heat conduction.
[0021] In this embodiment, the N+ region 1 , the P+ region 2 , and the P body region 6 are short-circuited with the source 3 at the same time.
[0022] In this embodiment, the thin sheet 13 and the U-shaped sheet 12 are made of the same material, both of which are aluminum foil thermal pads, but have different shapes. The thin sheet 13 and the U-shaped sheet 12 have excellent thermal conductivity and high thermal conductivity. The heat on the device can be quickly transferred to the U-shaped sheet 12, and then the heat on the U-shaped sheet 12 is transferred to the thin sheet 13, and then the heat is dissipated by convection, which can help maintain the stability of the VDMOSFET device and avoid the influence of heat on the device.
[0023] In this embodiment, the thickness of the buffer layer 8 is 3 micrometers. The buffer layer 8 can prevent substrate defects (dislocation, microcracks) from being transmitted to the upper structure, thereby improving the crystal quality of the upper material.
[0024] In this embodiment, a drain 10 is etched on the back side of the N+ substrate 9 .
[0025] In this embodiment, the buffer layer 8 is a highly doped P+ region, and the buffer layer 8 forms a PN junction with the N+ substrate 9, so that when the VDMOSFET device is turned on, minority carriers are emitted from the buffer layer 8 to the N-drift region 7, thereby modulating the conductivity of the drift region, so that the device has a strong current-carrying capacity, and solves the contradiction between the pursuit of high withstand voltage and the pursuit of low on-state resistance of the N-drift region 7 that VDMOSFET cannot solve in battery management.
[0026] In this embodiment, the corners of the P body region 6 have a curvature, and the curvature is designed to reduce electric field accumulation.
[0027] The working principle of this device is:
[0028] A buffer layer 8 is grown on the upper surface of the N+ substrate 9, and an N-drift region 7 is epitaxially grown on the upper surface of the buffer layer 8. The buffer layer is a highly doped P+ region, and the buffer layer forms a PN junction with the N+ substrate. A second long groove 11 is opened on the left and right sides of the N-drift region 7, and a first long groove 14 is opened on the left and right sides of the N+ substrate 9. The long groove is used to place a U-shaped sheet 12. By inserting the U-shaped sheet 12 inside the long groove, a part of the U-shaped sheet 12 is in the VDMOSFET device, and the other part is exposed to the outside. There are several thin sheets 13 of equal thickness on the inner side of the U-shaped sheet 12. The heat in the device is conducted to the U-shaped sheet 12 and the thin sheet 13, and the thermal conductivity is good. In addition, a part of the U-shaped sheet 12 is exposed, and the thin sheet 13 is exposed to the outside. It is not in direct contact with the device, and heat is exchanged through natural convection, which is beneficial to the stable performance of the semiconductor device.
[0029] The electrical components that appear in this article are all electrical components that exist in reality.
[0030] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.
Claims
1. A SiC VDMOSFET device for battery management of power amplifier equipment, comprising an N+ substrate (9), a gate (5) and a source (3), characterized in that: The N+ substrate (9) is made of silicon carbide, a buffer layer (8) is grown on the upper surface of the N+ substrate (9), an N-drift region (7) is epitaxially grown on the upper surface of the buffer layer (8), a second long groove (11) is opened on the left and right sides of the N-drift region (7), a first long groove (14) is opened on the left and right sides of the N+ substrate (9), and a U-shaped sheet (12) is inserted into the inner side walls of the first long groove (14) and the second long groove (11) on the same side, and the U-shaped sheet (12) is fixed to the first long groove (14) and the second long groove (11) by heat dissipation silicone grease, and the U-shaped sheet (12) 2) is welded to form a plurality of thin sheets (13) on the inner side, the N-drift region (7) is lowly doped with a P body region (6), and the P body region (6) is highly doped with N+ regions (1) on both sides, the P body region (6) is doped with a P+ region (2) between the two N+ regions (1), and the depth of the P+ region (2) is greater than the depth of the N+ region (1), the source electrode (3) is arranged on the upper surface of the N-drift region (7), a silicon dioxide oxide insulating layer (4) is embedded in the source electrode (3), and the gate electrode (5) is wrapped in the silicon dioxide oxide insulating layer (4).
2. A SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: The N+ region (1), the P+ region (2), and the P body region (6) are simultaneously short-circuited with the source (3).
3. The SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: The thin sheet (13) and the U-shaped sheet (12) are made of the same material, both are aluminum foil thermal conductive pads, but they have different shapes.
4. The SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: The thickness of the buffer layer (8) is 3 micrometers.
5. The SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: A drain (10) is etched on the back side of the N+ substrate (9).
6. The SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: The buffer layer (8) is a highly doped P+ region, and the buffer layer (8) forms a PN junction with the N+ substrate (9).
7. The SiC VDMOSFET device for battery management of power amplifier equipment according to claim 1, characterized in that: The corners of the P body region (6) are curved.