Substrate structure
By designing a substrate structure with a line width in the crystal-setting region greater than the outer line in the substrate structure, the problem of chip rupture caused by too concentrated conductor reaction force in the semiconductor structure during the thermal pressing process is solved, and the effect of reducing the risk of chip rupture and improving manufacturing yield is achieved.
Patent Information
- Application Number
- CN202421610799.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-02
- Filing Date
- 2024-07-09
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-09
AI Technical Summary
In the molding or hot pressing process of existing semiconductor structures, the reaction force of the conductor is too concentrated, resulting in a high risk of chip rupture.
A substrate structure is designed in which the second line in the crystal region has a wider second conductive trace with a width greater than the width of the first line outside the crystal region and is meandered or multiple conductive traces through the lines in the crystal region to increase the contact area.
By increasing the contact area between the chip and the line, dispersing the reaction force, reducing the risk of chip rupture during the hot pressing process, and improving the manufacturing yield of semiconductor components.
Smart Images
Figure CN222867683U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a substrate structure, and more particularly to a substrate structure for a semiconductor device. Background Art
[0002] With the rapid development of portable electronic products in recent years, the development of various related products is also moving towards high density, high performance, light, thin, short and small. To this end, the semiconductor industry has also developed various integrated multifunctional packaging embodiments to meet the requirements of light, thin, short and high density of electronic products. Under the influence of this trend, the width of the wires on the substrate used for semiconductor components is also shrinking day by day, so that more circuits and components can be accommodated on the same area of the substrate.
[0003] However, if Figure 1 As shown, when the conventional semiconductor structure 1 is subjected to a molding or hot pressing process, the mold or hot pressing jig (not shown) will apply a downward pressure on the chip 10 in the direction of the substrate 11, and the chip 10 will press the wire 12 in the circuit of the substrate below downward after being pressed downward, so that the wire 12 applies a reaction force to the chip 10. Since the line width of the wire 12 in the existing circuit is extremely small, the contact surface between it and the chip 10 is also extremely small, resulting in a very concentrated reaction force or stress applied by the wire 12 to the chip 10. In particular, the position where the chip 10 contacts those long straight wires 12. As a result, the chip 10 is prone to cracking at the corresponding positions during the molding or hot pressing process.
[0004] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Utility Model Content
[0005] In view of the various deficiencies of the above-mentioned prior art, the present application provides a substrate structure, including: an insulating layer, whose upper surface is defined as a chip placement area for setting a chip; and a circuit structure, which is arranged on the upper surface of the insulating layer and includes a first circuit located outside the chip placement area and having a first conductive trace and a second circuit located within the chip placement area and having a second conductive trace, wherein the first circuit is connected to the second circuit, and the width of the area covered by the second circuit is greater than the width of the first circuit.
[0006] In the aforementioned substrate structure, the width of the second conductive trace is greater than the width of the first conductive trace.
[0007] In the aforementioned substrate structure, the second conductive trace meanders through the die-placement region.
[0008] In the aforementioned substrate structure, the second circuit includes a plurality of second conductive traces.
[0009] In the aforementioned substrate structure, the second circuit further includes at least one third conductive trace, and the third conductive trace may or may not have an electrical function.
[0010] In the aforementioned substrate structure, the second circuit further includes at least one extension portion, and the extension portion is connected to the second conductive trace.
[0011] The present application also provides a substrate structure, including: an insulating layer, whose upper surface is defined as a crystal placement area for setting a chip; a circuit structure, which is arranged on the upper surface of the insulating layer and includes a first circuit arranged outside the crystal placement area, two second circuits arranged in the crystal placement area and a third circuit arranged on the lower surface of the insulating layer, wherein one end of each of the second circuits is located in the crystal placement area at intervals, and the other end is connected to the first circuit; and a plurality of conductive through holes, which are formed in the insulating layer, and the two second circuits are electrically connected to the third circuit through the plurality of conductive through holes.
[0012] In the aforementioned substrate structure, each of the second circuits has a single conductive trace or a plurality of conductive traces.
[0013] From the above, it can be seen that the present application increases the contact area between the chip and the circuit by widening the area covered by the circuit structure passing through the crystal placement area on the insulating layer in the substrate structure to a width greater than the width of the circuit outside the crystal placement area, thereby dispersing the reaction force from the circuit that the chip is subjected to during the hot pressing process, thereby reducing the risk of chip damage during the hot pressing process and improving the manufacturing yield of semiconductor components with this substrate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 A partial cross-sectional schematic diagram of a conventional semiconductor package;
[0015] Figure 2A It is a partial top view schematic diagram of the first embodiment of the substrate structure of the present application;
[0016] FIG. 2B to FIG. 2E It is a partial top view schematic diagram of various different variations of the first embodiment of the present application;
[0017] Figure 2D-1 for Figure 2D A partial top view schematically showing different variations of embodiments;
[0018] Figure 2E-1 to Figure 2E-4 for Figure 2E A partial top view schematically showing different variations of embodiments;
[0019] Figure 3A and Figure 3B They are respectively a partial top view and a partial bottom view of a second embodiment of a substrate structure of the present application;
[0020] Figure 3A-1 and Figure 3B-1 They are respectively a partial top view and a partial bottom view of a variation of the second embodiment of the present application;
[0021] Figure 3C It is a partial cross-sectional schematic diagram of the second embodiment of the substrate structure of the present application.
[0022] Main component symbols
[0023] 1 Semiconductor structure
[0024] 10 Chip
[0025] 11 base plate
[0026] 12 Wire
[0027] 2,3 Substrate Structure
[0028] 20 Insulation layer
[0029] 30 Line structure
[0030] 31 First Line
[0031] 32 Second Line
[0032] 32e Expansion
[0033] 33 Third Line
[0034] 34 Conductive vias
[0035] A: Crystal placement area
[0036] t1 First conductive trace
[0037] t2 Second conductive trace
[0038] t3 third conductive trace. DETAILED DESCRIPTION
[0039] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0040] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "one", "first", and "second" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical content.
[0041] Figure 2A FIG. 1 is a partial top view of the first embodiment of the substrate structure of the present application. Figure 2A As shown, the substrate structure 2 includes: an insulating layer 20, whose upper surface defines a die placement area A for arranging a chip; and a circuit structure 30. The insulating layer 20 is made of a dielectric material, such as polybenzoxazole (PBO), polyimide (PI), prepreg, etc. However, it can also be any other insulating material that meets the requirements, and this embodiment has no particular limitation on this.
[0042] The chip placement area A is used to place a chip (not shown), such as an active or passive semiconductor element. Similarly, this embodiment has no limitation to this.
[0043] The circuit structure 30 includes a plurality of circuits. In the present embodiment, the circuit structure 30 includes a first circuit 31 located outside the crystal placement area A, and a second circuit 32 located inside the crystal placement area A, and the first circuit 31 and the second circuit 32 are electrically connected to each other to form the circuit structure 30 together. The first circuit 31 includes a first conductive trace t1, and the second circuit 32 includes a second conductive trace t2. Generally speaking, the first conductive trace t1 and the second conductive trace t2 are formed of materials with better conductivity such as copper or copper-containing alloys. The width of the area covered by the second circuit 32 is greater than the width of the first circuit 31. For example, the second circuit 32 may contain only one second conductive trace t2, and the width of the second conductive trace t2 is greater than the width of the first conductive trace t1 of the first circuit 31 connected to the second circuit 32. That is, the circuit structure 30 is formed by extending the first conductive trace t1 with a narrower width outside the crystal placement area A into the crystal placement area A, and then transforming into the second conductive trace t2 with a wider width. In this way, when a chip (not shown) is placed in the crystal placement area A, the second circuit 32 composed of the second conductive trace t2 with a wider width contacts the bottom of the chip. When the hot pressing or compression molding process is subsequently performed, the second conductive trace t2 in the second circuit 32 has a wider contact surface with the bottom surface of the chip, so that the reaction force or stress applied by the second conductive trace t2 in the second circuit 32 to the bottom surface of the chip can be dispersed in a larger area, thereby effectively reducing the risk of the chip breaking at that location, thereby improving the manufacturing yield of the semiconductor device or electronic package having this substrate structure 2.
[0044] It should be noted that although the present embodiment is based on a single-layer single-sided substrate structure 2 having only one insulating layer and one circuit structure 30, in some other embodiments, one or more insulating layers (not shown) may be added below the insulating layer 20, and at least one added-layer circuit structure (not shown) may be provided between any two adjacent insulating layers, thereby forming a multi-layer structure, and the present embodiment has no particular limitation on this. However, since there is no mechanical connection between these added insulating layers and added-layer circuit structures and the chip disposed in the die-laying region A, no force will be directly applied to the chip during the hot pressing process, and therefore, no further description of these added structures will be given here.
[0045] In addition to the above-mentioned embodiments, Figure 2BIn a variation of the embodiment shown, the second conductive trace t2 in the second circuit 32 meanders through the crystal placement area A. In this way, the width of the area covered by the second circuit 32 can be greater than the width of the first circuit 31, so that the second circuit 32 and the chip (not shown) arranged in the crystal placement area A have a wider / larger contact surface, thereby avoiding excessive concentration of reaction force or stress applied by the second circuit 32 in the circuit structure 30 on the bottom surface of the chip during the hot pressing process, which may cause the chip to crack and be damaged.
[0046] Or maybe Figure 2C As shown, in another variation of the embodiment, the second circuit 32 located in the die-placement region A includes a plurality of second conductive traces t2, so that the width of the area covered by the second circuit 32 having the plurality of second conductive traces t2 is greater than the width of the first circuit 31 located outside the die-placement region A. Therefore, the reaction force or stress caused by the second circuit 32 on the chip (not shown) disposed thereon can also be dispersed in the subsequent thermal pressing process.
[0047] For example Figure 2D As shown, in another embodiment, the second circuit 32 further includes at least one third conductive trace t3. Here, an embodiment in which three second conductive traces t2 and two third conductive traces t3 are provided in the second circuit 32 is taken as an example. The third conductive trace t3 can be a conductive trace with electrical function, for example, connected in parallel with the second conductive trace t2; or, the third conductive trace t3 can also be connected to the second conductive trace t2 at only one end and the other end is open circuit or even as Figure 2D The two ends of the dummy conductive trace are open circuited and have no electrical function. However, regardless of whether it has electrical function or not, adding a third conductive trace t3 in the second circuit 32 can also achieve the same effect as the above-mentioned embodiments, so it will not be repeated here.
[0048] In addition, if Figure 2D-1 As shown, the second circuit 32 may also include only one second conductive trace t2 electrically connected to the first circuit 31 and at least one third conductive trace t3 ( Figure 2D-1 The embodiment in FIG. 1 has two third conductive traces t3). This embodiment can be regarded as Figure 2D The embodiment shown is a variation of the embodiment shown, so no further explanation will be given here.
[0049] In addition, if Figure 2E , Figure 2E-1 to Figure 2E-4As shown, the second circuit 32 may further include at least one extension portion 32e. The extension portion 32e may be a metal block disposed on the surface of the insulating layer 20 and electrically connected to the second conductive trace t2, or, in a multi-layer circuit structure, the extension portion 32e may also be a conductive through hole (not shown) connecting the second circuit 32 on the upper surface of the insulating layer 20 with other layers of circuits (not shown). Figure 2E , Figure 2E-1 to Figure 2E-4 In the example shown, the second circuit 32 includes two second conductive traces t2 and three extensions 32e connected across the two second conductive traces t2. The difference is only in the shape of the extensions 32e. Figure 2E Each expansion portion 32e in the embodiment is a diamond-shaped, Figure 2E-1 Each expansion portion 32e in the embodiment is a trapezoidal shape. Figure 2E-2 Each expansion portion 32e in the embodiment is circular. Figure 2E-3 Each expansion portion 32e in the embodiment includes two overlapping circles, Figure 2E-4 Of course, the expansion portion 32e can also be any other shape, as long as the width of the second line 32 covering the range is greater than the width of the first line 31.
[0050] Figure 3A and Figure 3B They are respectively a partial top view and a partial bottom view of the second embodiment of the present application, Figure 3C FIG. 2 is a partial cross-sectional view of the second embodiment of the present application. Figure 3A , Figure 3B and Figure 3C As shown, the present application also provides a substrate structure 3, including: an insulating layer 20, whose upper surface is defined with a chip placement area A for setting the chip; a circuit structure 30, which includes a first circuit 31 arranged outside the chip placement area A on the upper surface of the insulating layer 20, two second circuits 32 arranged in the chip placement area A and a third circuit 33 arranged on the lower surface of the insulating layer 20, wherein each of the second circuits 32 has only a single conductive trace, one end of which is spaced apart from another second circuit 32 and located in the chip placement area A, and the other end is connected to the first circuit 31; and a plurality of conductive through holes 34, which are arranged in the insulating layer 20, and the two second circuits 32 are electrically connected to the third circuit 33 through the plurality of conductive through holes 34. That is, the substrate structure 3 shown in the present embodiment shortens the length of the second circuit 32 that will subsequently exert a reaction force on the bottom of the chip (not shown) by switching the layers of the second circuit 32 arranged in the crystal placement area A, thereby reducing the reaction force or stress on the bottom surface of the chip. This can also reduce the risk of the chip breaking due to the force on the bottom during the hot pressing process.
[0051] Again, in Figure 3A-1 and Figure 3B-1In a variation of the embodiment shown, the circuit structure 30 includes two second circuits 32 spaced apart in the crystal placement area A, each second circuit 32 is divided into two conductive traces to increase the width of the area covered by the second circuit 32, and at the same time, each conductive trace in each second circuit 32 is electrically connected to a third circuit 33 disposed on the lower surface of the insulating layer 20 via a conductive through hole 34 penetrating the insulating layer 20. In this way, the length of the second circuit 32 that will subsequently exert a reaction force on the bottom of the chip (not shown) can be shortened by changing the layer layout of the second circuit 32 disposed in the crystal placement area A, and the reaction force or stress on the bottom surface of the chip can be reduced, thereby reducing the risk of the chip being broken due to the force on the bottom during, for example, a hot pressing process.
[0052] In summary, the present application increases the contact area between the chip and the circuit by widening the area covered by the circuit structure passing through the crystal placement area on the insulating layer of the substrate structure to a width greater than the width of the circuit outside the crystal placement area, thereby dispersing the reaction force from the circuit that the chip is subjected to during the hot pressing process, thereby reducing the risk of chip damage during the hot pressing process and improving the manufacturing yield of semiconductor components with this substrate structure.
[0053] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be as set forth in the attached claims.
Claims
1. A substrate structure, characterized in that: include: The insulating layer has an upper surface defining a chip placement area for arranging a chip; as well as A circuit structure is arranged on the upper surface of the insulating layer and includes a first circuit located outside the crystal placement area and having a first conductive trace and a second circuit located within the crystal placement area and having a second conductive trace, wherein the first circuit is connected to the second circuit, and the width of the area covered by the second circuit is greater than the width of the first circuit.
2. The substrate structure according to claim 1, characterized in that: The width of the second conductive trace is greater than the width of the first conductive trace.
3. The substrate structure according to claim 1, characterized in that: The second conductive trace meanders through the die-stack region.
4. The substrate structure according to claim 1, characterized in that: The second circuit includes a plurality of second conductive traces.
5. The substrate structure according to claim 1, characterized in that: The second circuit further includes at least one third conductive trace, and the third conductive trace has or does not have an electrical function.
6. The substrate structure according to claim 1, characterized in that: The second circuit further includes at least one extended portion, and the extended portion is connected to the second conductive trace.
7. A substrate structure, characterized in that: include: The insulating layer has an upper surface defining a chip placement area for arranging a chip; A circuit structure is disposed on the upper surface of the insulating layer and includes a first circuit disposed outside the crystal placement area, two second circuits disposed in the crystal placement area, and a third circuit disposed on the lower surface of the insulating layer, wherein one end of each of the second circuits is spaced apart and disposed in the crystal placement area, and the other end is connected to the first circuit; as well as A plurality of conductive through holes are formed in the insulating layer, and the two second circuits are electrically connected to the third circuit through the plurality of conductive through holes.
8. The substrate structure according to claim 7, characterized in that: Each of the second circuits has a single conductive trace.
9. The substrate structure according to claim 7, characterized in that: Each of the second circuits has a plurality of conductive traces.