Substrate structure
By adopting a layered structure of the core layer, the first line layer and the second line layer in the substrate structure, and the production is synchronous and separately, the process extension and low yield problems caused by the increase of the line layer of the substrate structure in the prior art are solved, and more efficient production and higher yields are achieved.
Patent Information
- Application Number
- CN202421629276.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-01
- Filing Date
- 2024-07-10
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-10
AI Technical Summary
When the existing substrate structure increases the number of lines, it leads to longer process, extended delivery time, low utilization rate of plates, and increases the risk of low yield. At the same time, when abnormalities are found on the outermost line layer, it needs to be remade, which takes twice the process time.
The layered structure of the core layer, the first line layer and the second line layer are adopted. Through synchronous production and separate production, the number of layering processes is reduced, the accumulated offset of the line layer or conductive blind holes is reduced, and the yield of the substrate structure is improved.
The process time of the substrate structure is shortened, the risk of low yield is reduced, the production efficiency and yield of the substrate structure is improved, and the cumulative offset is reduced.
Smart Images
Figure CN222867684U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a manufacturing technology of a substrate structure, and in particular to a substrate structure with a circuit build-up layer. Background Art
[0002] As the number of input / output (I / O) of electronic products increases, the substrate structure (or substrate) needs to increase the number of circuit layers and increase the unit size to provide sufficient layout space.
[0003] However, increasing the number of circuit layers in the substrate structure will lengthen the manufacturing process and delivery time, and the larger the unit size of the substrate structure, the lower the panel utilization rate. In addition, increasing the number of circuit layers in the substrate structure will continue to accumulate defective conditions, which will also increase the risk of low yield of the substrate structure.
[0004] In addition, if unfortunately the entire batch of abnormalities in the substrate structure are discovered when the outermost circuit layer of the substrate structure is completed, the substrate structure must be remade, which consumes twice the process time, and the alignment of the substrate structure will also increase as the number of circuit layers increases, resulting in a greater cumulative offset of the circuit layer or its conductive blind hole.
[0005] Figures 1A to 1F It is a cross-sectional schematic diagram of a manufacturing method of a substrate structure 1 in the prior art, and the substrate structure 1 may include at least ten layers (such as ten layers, twelve layers, fourteen layers or more than sixteen layers) of circuit layers.
[0006] Taking the manufacture of a substrate structure 1 including ten circuit layers as an example, it is necessary to manufacture a first circuit build-up layer 20 including five circuit layers and a second circuit build-up layer 30 including five circuit layers, and a total of five build-up processes need to be performed, such as the first build-up process to the fifth build-up process listed below.
[0007] like Figure 1A As shown, a core layer 10 having a first side 10a and a second side 10b opposite to each other is provided.
[0008] The first layer build-up process: Figure 1B As shown, a first circuit layer 21 and a second circuit layer 31 are respectively added on the first side 10a and the second side 10b of the core layer 10.
[0009] Second layer build-up process: Figure 1C As shown, a third circuit layer 22 and a fourth circuit layer 32 are added on the first circuit layer 21 and the second circuit layer 31 respectively.
[0010] The third layer build-up process: Figure 1DAs shown, a fifth circuit layer 23 and a sixth circuit layer 33 are added on the third circuit layer 22 and the fourth circuit layer 32 respectively.
[0011] The fourth layer build-up process: Figure 1E As shown, a seventh circuit layer 24 and an eighth circuit layer 34 are added on the fifth circuit layer 23 and the sixth circuit layer 33 respectively.
[0012] The fifth layer build-up process: Figure 1F As shown, a ninth circuit layer 25 and a tenth circuit layer 35 are added on the seventh circuit layer 24 and the eighth circuit layer 34 respectively.
[0013] Thus, a substrate structure 1 including ten circuit layers can be obtained, and the first circuit build-up layer 20 and the second circuit build-up layer 30 of the substrate structure 1 both include five circuit layers. That is, the first circuit build-up layer 20 includes a first circuit layer 21, a third circuit layer 22, a fifth circuit layer 23, a seventh circuit layer 24, and a ninth circuit layer 25, and the second circuit build-up layer 30 includes a second circuit layer 31, a fourth circuit layer 32, a sixth circuit layer 33, an eighth circuit layer 34, and a tenth circuit layer 35.
[0014] Assuming that one build-up process will cause one circuit layer of the first circuit build-up layer 20 or the second circuit build-up layer 30 or its conductive blind via to have an offset of, for example, 25 microns (μm) from the inside to the outside, then five build-up processes will cause five circuit layers of the first circuit build-up layer 20 or the second circuit build-up layer 30 or its conductive blind via to have a total cumulative offset M of, for example, 125 microns (μm) from the inside to the outside.
[0015] Furthermore, laminating and manufacturing the circuit layers of the first circuit build-up layer 20 and the second circuit build-up layer 30 layer by layer from the core layer 10 will cause the process of the substrate structure 1 to be lengthy, and the higher the number of circuit layers of the first circuit build-up layer 20 and the second circuit build-up layer 30, the larger the size of the substrate structure 1 and the higher the risk of low yield.
[0016] In addition, as the number of circuit layers of the substrate structure 1 increases, the number of times the substrate structure 1 undergoes layer-adding processes increases, the process becomes longer, and the delivery time becomes longer. This will also cause the alignment of the substrate structure 1 to increase as the number of circuit layers increases, resulting in a greater cumulative offset M of the circuit layers or their conductive blind holes, and will also increase the risk of low yield of the substrate structure 1.
[0017] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0018] In view of the deficiencies of the above-mentioned prior art, the present application provides a substrate structure, including: a core layer, which has a first side and a second side opposite to each other, a plurality of first connection pads and a plurality of second connection pads, and the plurality of first connection pads and the plurality of second connection pads of the core layer are formed on the first side and the second side respectively; a first circuit build-up layer, which includes a plurality of first bonding pads bonded to the plurality of first connection pads of the core layer, wherein the first circuit build-up layer is located on the first side of the core layer, and a first gap is provided between the first side of the core layer and the first circuit build-up layer; and a second circuit build-up layer, which includes a plurality of second bonding pads bonded to the plurality of second connection pads of the core layer, wherein the second circuit build-up layer is located on the second side of the core layer, and a second gap is provided between the second side of the core layer and the second circuit build-up layer.
[0019] The present application also provides a method for manufacturing a substrate structure, including: providing a core layer having a first side and a second side opposite to each other, a plurality of first connection pads and a plurality of second connection pads, wherein the plurality of first connection pads and the plurality of second connection pads of the core layer are formed on the first side and the second side respectively; bonding a plurality of first bonding pads of a first circuit build-up layer to a plurality of first connection pads of the core layer, so that the first circuit build-up layer is located on the first side of the core layer, and a first gap is formed between the first side of the core layer and the first circuit build-up layer; and bonding a plurality of second bonding pads of a second circuit build-up layer to a plurality of second connection pads of the core layer, so that the second circuit build-up layer is located on the second side of the core layer, and a second gap is formed between the second side of the core layer and the second circuit build-up layer.
[0020] In the aforementioned substrate structure, the core layer may have a plurality of conductive through holes that penetrate through the first side and the second side of the core layer to electrically connect the plurality of first connection pads and the plurality of second connection pads.
[0021] In the aforementioned substrate structure and manufacturing method thereof, the first circuit build-up layer and the second circuit build-up layer both include at least five circuit layers, and the number of circuit layers of the first circuit build-up layer is the same as the number of circuit layers of the second circuit build-up layer.
[0022] In the aforementioned substrate structure and manufacturing method thereof, the first circuit build-up layer and the second circuit build-up layer both include at least five circuit layers, and the number of circuit layers of the first circuit build-up layer is different from the number of circuit layers of the second circuit build-up layer.
[0023] In the aforementioned substrate structure and its manufacturing method, the substrate structure may include a first covering layer and a second covering layer, the first covering layer is formed in a first gap between a first side of the core layer and a first circuit adding layer to cover a plurality of first connection pads and a plurality of first bonding pads, and the second covering layer is formed in a second gap between a second side of the core layer and a second circuit adding layer to cover a plurality of second connection pads and a plurality of second bonding pads.
[0024] In the aforementioned substrate structure and its manufacturing method, the first circuit build-up layer and the second circuit build-up layer may respectively include a first insulating protective layer having multiple first openings and a second insulating protective layer having multiple second openings, and the first insulating protective layer and the second insulating protective layer are respectively formed on the outermost circuit layer of the first circuit build-up layer and the outermost circuit layer of the second circuit build-up layer.
[0025] In the aforementioned substrate structure and its manufacturing method, the substrate structure may include multiple first conductors and multiple second conductors, for the multiple first bonding pads of the first circuit growth layer to be bonded to the multiple first connection pads of the core layer through the multiple first conductors, and for the multiple second bonding pads of the second circuit growth layer to be bonded to the multiple second connection pads of the core layer through the multiple second conductors.
[0026] In the aforementioned substrate structure and its manufacturing method, multiple first connection pads, multiple second connection pads, multiple first bonding pads and multiple second bonding pads all have metal materials, the metal materials of multiple first bonding pads are directly bonded to the metal materials of multiple first connection pads, and the metal materials of multiple second bonding pads are directly bonded to the metal materials of multiple second connection pads.
[0027] In the aforementioned substrate structure and manufacturing method thereof, the first circuit build-up layer and the second circuit build-up layer respectively have a first curved shape and a second curved shape facing different directions.
[0028] In the aforementioned substrate structure and manufacturing method thereof, the first circuit build-up layer and the second circuit build-up layer respectively have a first curved shape and a second curved shape facing the same direction.
[0029] In the manufacturing method of the aforementioned substrate structure, when manufacturing the first circuit build-up layer and the second circuit build-up layer, a first circuit layer of the first circuit build-up layer and a second circuit layer of the second circuit build-up layer are first manufactured; then, a third circuit layer and a fourth circuit layer of the first circuit build-up layer are respectively manufactured by adding layers, stacking or symmetrically manufacturing on opposite sides of the first circuit layer, and a fifth circuit layer and a sixth circuit layer of the second circuit build-up layer are respectively manufactured by adding layers, stacking or symmetrically manufacturing on opposite sides of the second circuit layer; then, a seventh circuit layer and an eighth circuit layer of the first circuit build-up layer are respectively manufactured by adding layers, stacking or symmetrically manufacturing on the third circuit layer and the fourth circuit layer, and a ninth circuit layer and a tenth circuit layer of the second circuit build-up layer are respectively manufactured by adding layers, stacking or symmetrically manufacturing on the fifth circuit layer and the sixth circuit layer.
[0030] From the above, it can be seen that in the substrate structure and its manufacturing method of the present application, the substrate structure is mainly divided into a core layer, a first circuit increase layer and a second circuit increase layer for synchronous (simultaneous) manufacturing, which is beneficial to shorten the process or manufacturing time of the substrate structure, speed up the delivery time of the substrate structure, and improve the manufacturing yield of the substrate structure.
[0031] Furthermore, the present application can manufacture the core layer, the first circuit build-up layer and the second circuit build-up layer separately, so as to reduce the number of build-up processes of the first circuit build-up layer and the second circuit build-up layer, and can also effectively reduce the cumulative offset of multiple circuit layers or their conductive blind holes of the first circuit build-up layer and the second circuit build-up layer.
[0032] In addition, the present application can simultaneously produce a first circuit build-up layer including at least five circuit layers and a second circuit build-up layer including at least five circuit layers in a separate, synchronous and / or symmetrical manner, which is beneficial for the first circuit build-up layer and the second circuit build-up layer. When the number of circuit layers is greater, the efficiency of the substrate structure's build-up process can be higher. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figures 1A to 1F It is a cross-sectional schematic diagram of a method for manufacturing a substrate structure in the prior art.
[0034] FIG. 2A to FIG. 2H It is a cross-sectional schematic diagram of a method for manufacturing a substrate structure of the present application.
[0035] Figure 3 Another cross-sectional schematic diagram of the substrate structure of the present application.
[0036] 4A to 4D The following are simplified schematic diagrams of different embodiments of the substrate structure of the present application.
[0037] Main component symbols
[0038] 1,2 Substrate structure
[0039] 10,40 Core Layer
[0040] 10a,40a First side
[0041] 10b,40b Second side
[0042] 20,50 First line increase layer
[0043] 21,51 First circuit layer
[0044] 22,52 Third circuit layer
[0045] 23,62 Fifth circuit layer
[0046] 24,54 Seventh circuit layer
[0047] 25,64 Ninth circuit layer
[0048] 30,60 Second line increase layer
[0049] 31,61 Second circuit layer
[0050] 32,53 Fourth circuit layer
[0051] 33,63 Sixth circuit layer
[0052] 34,55 The eighth circuit layer
[0053] 35,65 Tenth circuit layer
[0054] 41 First connection pad
[0055] 42 Second connection pad
[0056] 43 Conductive vias
[0057] 511 First Line
[0058] 512 First conductive blind via
[0059] 513 First Dielectric Material
[0060] 521 Third Line
[0061] 522 The third conductive blind hole
[0062] 523 Third dielectric material
[0063] 531 Fourth Line
[0064] 532 Fourth conductive blind via
[0065] 533 Fourth dielectric material
[0066] 541 Seventh Line
[0067] 542 Seventh conductive blind via
[0068] 543 Seventh dielectric material
[0069] 551 Route 8
[0070] 552 Eighth Conductive Blind Via
[0071] 553 Eighth dielectric material
[0072] 56 First bonding pad
[0073] 57 First insulation protection layer
[0074] 571 First Opening
[0075] 611 Second Line
[0076] 612 Second conductive blind hole
[0077] 613 Second dielectric material
[0078] 621 Fifth Line
[0079] 622 Fifth conductive blind via
[0080] 623 Fifth dielectric material
[0081] 631 Sixth Line
[0082] 632 Sixth conductive blind via
[0083] 633 Sixth dielectric material
[0084] 641 Route 9
[0085] 642 Ninth Conductive Blind Via
[0086] 643 Ninth dielectric material
[0087] 651 Route 10
[0088] 652 Tenth conductive blind via
[0089] 653 Tenth dielectric material
[0090] 66 Second bonding pad
[0091] 67 Second insulation protection layer
[0092] 671 Second Opening
[0093] 71 First Conductor
[0094] 72 Second Conductor
[0095] 81 First coating layer
[0096] 82 Second coating layer
[0097] A The first bearing member
[0098] A1 First Release Film
[0099] B Second bearing member
[0100] B1 Second release film
[0101] D1 First direction
[0102] D2 Second direction
[0103] H1 First Distance
[0104] H2 Second distance
[0105] H3 Third Distance
[0106] H4 Fourth Distance
[0107] G1 First Gap
[0108] G2 Second gap
[0109] M,N Cumulative offset. DETAILED DESCRIPTION
[0110] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0111] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that can be produced by this application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "one", "two", "first", "second", "third", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship, without substantially changing the technical content, should also be regarded as the scope of the implementation of this application.
[0112] FIG. 2A to FIG. 2H The cross-sectional view of the manufacturing method of the substrate structure 2 of the present application is shown in FIG. The substrate structure 2 may include a core layer 40, a first circuit build-up layer 50 and a second circuit build-up layer 60, and the first circuit build-up layer 50 and the second circuit build-up layer 60 may include circuit layers of the same number or different numbers.
[0113] For example, the substrate structure 2 may include at least ten (e.g., ten, twelve, fourteen or sixteen or more) circuit layers, and the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 may both include at least five (e.g., five, seven or nine or more) circuit layers.
[0114] Taking the manufacture of a substrate structure 2 including ten circuit layers as an example, it is necessary to manufacture a first circuit build-up layer 50 including five circuit layers and a second circuit build-up layer 60 including five circuit layers. However, the present application only requires performing three build-up processes, namely the following first build-up process to the third build-up process.
[0115] like Figure 2AAs shown, a core layer 40 is provided having a relative first side 40a and a second side 40b, a plurality of first connection pads 41, a plurality of second connection pads 42 and a plurality of conductive through holes 43, wherein the plurality of first connection pads 41 and the plurality of second connection pads 42 of the core layer 40 can be formed on the first side 40a and the second side 40b, respectively, and the plurality of conductive through holes 43 can penetrate the first side 40a and the second side 40b of the core layer 40 to electrically connect the plurality of first connection pads 41 and the plurality of second connection pads 42.
[0116] In one embodiment, the substrate structure 2 may be a semiconductor substrate structure, etc., the main body or core portion of the core layer 40 may be a core board, the first connection pad 41 or the second connection pad 42 may be a bonding pad, a metal pad, a conductive pad, etc., the material of the first connection pad 41 or the second connection pad 42 may be a metal material or a conductive material, etc., and the conductive through hole 43 may be a silicon through-hole, etc., but is not limited to this.
[0117] The first build-up process mainly involves building up or stacking a first circuit layer 51 and a second circuit layer 61 on the first carrier A and the second carrier B respectively at the same time.
[0118] like Figure 2B As shown, a first carrier A having a first release film A1 is provided, so as to add or stack a first circuit layer 51 on the first release film A1 of the first carrier A. At the same time, a second carrier B having a second release film B1 is provided, so as to add or stack a second circuit layer 61 on the second release film B1 of the second carrier B. For example, the first carrier A and the second carrier B are both removable carriers, carrier boards, etc., and the first release film A1 or the second release film B1 can be a film coated with a release agent, etc.
[0119] In one embodiment, the first circuit layer 51 may have at least one first circuit 511, a plurality of first conductive blind vias 512, and a first dielectric material 513, etc. The plurality of first conductive blind vias 512 may be electrically connected to the first circuit 511, and the first dielectric material 513 may combine the first circuit 511 and the plurality of first conductive blind vias 512. Meanwhile, the second circuit layer 61 may have at least one second circuit 611, a plurality of second conductive blind vias 612, and a second dielectric material 613, etc. The plurality of second conductive blind vias 612 may be electrically connected to the second circuit 611, and the second dielectric material 613 may combine the second circuit 611 and the plurality of second conductive blind vias 612.
[0120] In one embodiment, at least one third circuit 521 and a fourth dielectric material 533 may be formed on opposite sides of the first circuit layer 51, respectively. The fourth dielectric material 533 may be located between the first release film A1 of the first carrier A and the first circuit layer 51, and the third circuit 521 may be electrically connected to the plurality of first conductive blind vias 512. At the same time, at least one fifth circuit 621 and a sixth dielectric material 633 may be formed on opposite sides of the second circuit layer 61, respectively. The sixth dielectric material 633 may be located between the second release film B1 of the second carrier B and the second circuit layer 61, and the fifth circuit 621 may be electrically connected to the plurality of second conductive blind vias 612.
[0121] like Figure 2C As shown, a third dielectric material 523 is formed on the third circuit 521 to combine (cover) the third circuit 521 , and a fifth dielectric material 623 is formed on the fifth circuit 621 to combine (cover) the fifth circuit 621 .
[0122] The second layer-building process: mainly, a third circuit layer 52 and a fourth circuit layer 53 can be added, stacked or symmetrically produced on opposite sides of the first circuit layer 51, and a fifth circuit layer 62 and a sixth circuit layer 63 can be added, stacked or symmetrically produced on opposite sides of the second circuit layer 61.
[0123] like Figure 2D As shown, a plurality of third conductive blind vias 522 are formed in the third dielectric material 523 to electrically connect the third circuit 521, so that the third circuit 521, the plurality of third conductive blind vias 522 and the third dielectric material 523 form a third circuit layer 52. Figure 2C The fourth dielectric material 533 is exposed outside the first carrier A and the first release film A1 thereof, and a plurality of fourth conductive blind holes 532 are formed in the fourth dielectric material 533. At least one fourth circuit 531 is formed on the fourth dielectric material 533 to electrically connect the plurality of fourth conductive blind holes 532, so that the fourth circuit 531, the plurality of fourth conductive blind holes 532 and the fourth dielectric material 533 constitute a fourth circuit layer 53.
[0124] At the same time, a plurality of fifth conductive blind vias 622 are formed in the fifth dielectric material 623 to electrically connect the fifth circuit 621, so that the fifth circuit 621, the plurality of fifth conductive blind vias 622 and the fifth dielectric material 623 form a fifth circuit layer 62. Figure 2C The sixth dielectric material 633 is exposed outside the second carrier B and its second release film B1, and a plurality of sixth conductive blind holes 632 are formed in the sixth dielectric material 633. At least one sixth circuit 631 is formed on the sixth dielectric material 633 to electrically connect the plurality of sixth conductive blind holes 632, so that the sixth circuit 631, the plurality of sixth conductive blind holes 632 and the sixth dielectric material 633 constitute a sixth circuit layer 63.
[0125] In one embodiment, at least one seventh circuit 541 may be formed on the third dielectric material 523 of the third circuit layer 52 to electrically connect the plurality of third conductive blind vias 522 , and at least one ninth circuit 641 may be formed on the fifth dielectric material 623 of the fifth circuit layer 62 to electrically connect the plurality of fifth conductive blind vias 622 .
[0126] The third layer-building process: mainly, a seventh circuit layer 54 and an eighth circuit layer 55 can be added, stacked or symmetrically produced on the third circuit layer 52 and the fourth circuit layer 53 respectively, and a ninth circuit layer 64 and a tenth circuit layer 65 can be added, stacked or symmetrically produced on the fifth circuit layer 62 and the sixth circuit layer 63 respectively.
[0127] like Figure 2E As shown, a seventh dielectric material 543 is formed on the third wiring layer 52 to combine (cover) the seventh wiring 541, and then a plurality of seventh conductive blind vias 542 are formed in the seventh dielectric material 543 to electrically connect the seventh wiring 541, so that the seventh wiring 541, the plurality of seventh conductive blind vias 542 and the seventh dielectric material 543 constitute a seventh wiring layer 54. Moreover, an eighth dielectric material 553 is formed on the fourth wiring layer 53 to combine (cover) the fourth wiring 531, and a plurality of eighth conductive blind vias 552 are formed in the eighth dielectric material 553 to electrically connect the fourth wiring 531, and then at least one eighth wiring 551 is formed on the eighth dielectric material 553 to electrically connect the plurality of eighth conductive blind vias 552, so that the eighth wiring 551, the plurality of eighth conductive blind vias 552 and the eighth dielectric material 553 constitute an eighth wiring layer 55.
[0128] At the same time, a ninth dielectric material 643 is formed on the fifth circuit layer 62, and a plurality of ninth conductive blind vias 642 are formed in the ninth dielectric material 643 to electrically connect the ninth circuit 641, so that the ninth circuit 641, the plurality of ninth conductive blind vias 642 and the ninth dielectric material 643 constitute a ninth circuit layer 64. Moreover, a tenth dielectric material 653 is formed on the sixth circuit layer 63, and a plurality of tenth conductive blind vias 652 are formed in the tenth dielectric material 653 to electrically connect the sixth circuit 631, and at least one tenth circuit 651 is formed on the tenth dielectric material 653, so that the tenth circuit 651, the plurality of tenth conductive blind vias 652 and the tenth dielectric material 653 constitute a tenth circuit layer 65.
[0129] Therefore, the present application can make the first circuit layer 51, the third circuit layer 52, the fourth circuit layer 53, the seventh circuit layer 54 and the eighth circuit layer 55 form a first circuit build-up layer 50 through the above-mentioned three layer build-up processes (i.e., the first layer build-up process to the third layer build-up process), and make the second circuit layer 61, the fifth circuit layer 62, the sixth circuit layer 63, the ninth circuit layer 64 and the tenth circuit layer 65 form a second circuit build-up layer 60.
[0130] Furthermore, in the first circuit build-up layer 50 and the second circuit build-up layer 60 of the present application, a plurality of first bonding pads 56 may be formed on the seventh circuit layer 54 to electrically connect the plurality of seventh conductive blind vias 542 , and a plurality of second bonding pads 66 may be formed on the ninth circuit layer 64 to electrically connect the plurality of ninth conductive blind vias 642 .
[0131] In one embodiment, the first dielectric material 513 to the tenth dielectric material 653 can all be insulating materials, etc., the first bonding pad 56 or the second bonding pad 66 can be a connecting pad, a metal pad, a conductive pad, etc., and the material of the first bonding pad 56 or the second bonding pad 66 can be a metal material or a conductive material, etc.
[0132] In addition, if multiple first circuit build-up layers 50 and multiple second circuit build-up layers 60 are manufactured at one time or in batches, the present application can also select first circuit build-up layers 50 and second circuit build-up layers 60 with higher yields to combine with the core layer 40, so as to improve the yield of the substrate structure 2, thereby reducing the risk of low yield.
[0133] like Figure 2F As shown, after the first circuit build-up layer 50 and the second circuit build-up layer 60 are formed, the first circuit build-up layer 50 and the second circuit build-up layer 60 are bonded to the first side 40 a and the second side 40 b of the core layer 40 , respectively.
[0134] In one embodiment, the first bonding pads 56 of the first circuit build-up layer 50 may be bonded to the first connection pads 41 of the core layer 40, and the second bonding pads 66 of the second circuit build-up layer 60 may be bonded to the second connection pads 42 of the core layer 40. At the same time, a first gap G1 may be provided between the first circuit build-up layer 50 (such as the seventh circuit layer 54) and the first side 40a of the core layer 40, and a second gap G2 may be provided between the second circuit build-up layer 60 (such as the ninth circuit layer 64) and the second side 40b of the core layer 40.
[0135] In one embodiment, the first bonding pads 56 of the first circuit build-up layer 50 may be bonded or electrically connected to the first connection pads 41 of the core layer 40 through the first conductors 71, and the second bonding pads 66 of the second circuit build-up layer 60 may be bonded or electrically connected to the second connection pads 42 of the core layer 40 through the second conductors 72. However, in other embodiments (see Figure 3 ), the multiple first bonding pads 56 of the first circuit build-up layer 50 can also be directly bonded or electrically connected to the multiple first connection pads 41 of the core layer 40, and the multiple second bonding pads 66 of the second circuit build-up layer 60 can also be directly bonded or electrically connected to the multiple second connection pads 42 of the core layer 40.
[0136] like Figure 2GAs shown, a first covering layer 81 is formed in a first gap G1 between a first side 40a of the core layer 40 and a first circuit build-up layer 50 (such as a seventh circuit layer 54) to cover a plurality of first connection pads 41 of the core layer 40, a plurality of first bonding pads 56 of the first circuit build-up layer 50, and a plurality of first conductors 71, and a second covering layer 82 is formed in a second gap G2 between a second side 40b of the core layer 40 and a second circuit build-up layer 60 (such as a ninth circuit layer 64) to cover a plurality of second connection pads 42 of the core layer 40, a plurality of second bonding pads 66 of the second circuit build-up layer 60, and a plurality of second conductors 72.
[0137] In one embodiment, the first conductor 71 or the second conductor 72 may be a conductive element, a conductive bump, a metal ball (such as a tin ball), a solder ball, etc., and the first coating layer 81 or the second coating layer 82 may be a packaging layer, a filling layer, an underfill, etc.
[0138] In addition, assuming that a single build-up process will cause a circuit layer of the first circuit build-up layer 50 or the second circuit build-up layer 60 or its conductive blind via to have an offset (or displacement) of, for example, 25 micrometers (μm) from the inside to the outside, the three-build-up process of the present application will only cause the five circuit layers of the first circuit build-up layer 50 or the second circuit build-up layer 60 or its conductive blind via to have a total cumulative offset N of, for example, 75 micrometers (μm) from the inside to the outside, but the five-build-up process of the prior art will cause the five circuit layers or their conductive blind vias to have a total cumulative offset of, for example, 125 micrometers (μm) from the inside to the outside, so the cumulative offset N of the three-build-up process of the present application will be significantly smaller than the cumulative offset of the five-build-up process of the prior art.
[0139] like Figure 2H As shown, the first circuit build-up layer 50 and the second circuit build-up layer 60 may respectively include a first insulating protection layer 57 having a plurality of first openings 571 and a second insulating protection layer 67 having a plurality of second openings 671 .
[0140] That is, a first insulating protective layer 57 may be formed on the eighth circuit layer 55 (e.g., the outermost circuit layer) of the first circuit build-up layer 50, and a portion of the eighth circuit 551 of the eighth circuit layer 55 is exposed through a plurality of first openings 571 of the first insulating protective layer 57. At the same time, a second insulating protective layer 67 may be formed on the tenth circuit layer 65 (e.g., the outermost circuit layer) of the second circuit build-up layer 60, and a portion of the tenth circuit 651 of the tenth circuit layer 65 is exposed through a plurality of second openings 671 of the second insulating protective layer 67.
[0141] Figure 3 is another cross-sectional schematic diagram of the substrate structure 2 of the present application, and Figure 3 The main differences from the substrate structure 2 of FIG. 2 are as follows, and the rest of the technical contents are the same as those of the above FIG. 2A to FIG. 2H The detailed description will not be repeated here.
[0142] exist Figure 3 In the embodiment, the first bonding pads 56 of the first circuit build-up layer 50 can be directly bonded or electrically connected to the first connection pads 41 of the core layer 40, and the second bonding pads 66 of the second circuit build-up layer 60 can be directly bonded or electrically connected to the second connection pads 42 of the core layer 40.
[0143] For example, the plurality of first connection pads 41, the plurality of second connection pads 42, the plurality of first bonding pads 56, and the plurality of second bonding pads 66 all have metal materials, so that the metal materials of the plurality of first bonding pads 56 are directly bonded to the metal materials of the plurality of first connection pads 41 by metal-to-metal bonding, and the metal materials of the plurality of second bonding pads 66 are directly bonded to the metal materials of the plurality of second connection pads 42 by metal-to-metal bonding, thereby eliminating the need for Figure 2H The first conductor 71 and the second conductor 72 in the embodiment.
[0144] It should be noted that in the above FIG. 2A to FIG. 2H and Figure 3 In the embodiment of the present application, the substrate structure 2 includes ten circuit layers, and the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 both include the same number of circuit layers (such as five circuit layers) as an example. However, in other embodiments, the substrate structure 2 may also include fewer or more circuit layers (such as twelve, fourteen or sixteen layers or more), and the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 may also include different numbers of circuit layers.
[0145] For example, the substrate structure 2 may include twelve circuit layers, and the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 include five circuit layers and seven circuit layers, respectively. Alternatively, the substrate structure 2 may include fourteen circuit layers, and the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 both include the same number of seven circuit layers. Alternatively, the substrate structure 2 may include sixteen circuit layers, and the first circuit build-up layer 50 and the second circuit build-up layer 60 include nine circuit layers and seven circuit layers, respectively.
[0146] 4A to 4D 1 is a simplified schematic diagram of different embodiments of the substrate structure 2 of the present application. At the same time, the first circuit build-up layer 50 and the second circuit build-up layer 60 of the substrate structure 2 may have a first deformation tendency and a second deformation tendency, respectively. For example, the first circuit build-up layer 50 and the second circuit build-up layer 60 may have a first bending shape and a second bending shape facing different directions, respectively, or the first circuit build-up layer 50 and the second circuit build-up layer 60 may have a first bending shape and a second bending shape facing the same direction, respectively.
[0147] like Figure 4A As shown in the embodiment of the present invention, the first circuit build-up layer 50 may have a first curved shape toward a first direction D1 (such as an upward direction), and the second circuit build-up layer 60 may have a second curved shape toward a second direction D2 (such as a downward direction) different from the first direction D1. At the same time, the first distance H1 at the center of the first circuit build-up layer 50 and the core layer 40 is greater than the second distance H2 at the edge of the first circuit build-up layer 50 and the core layer 40, and the third distance H3 at the center of the second circuit build-up layer 60 and the core layer 40 is greater than the fourth distance H4 at the edge of the second circuit build-up layer 60 and the core layer 40.
[0148] like Figure 4B As shown in the embodiment of the present invention, the first circuit build-up layer 50 may have a first curved shape toward the second direction D2 (such as the downward direction), and the second circuit build-up layer 60 may have a second curved shape toward the first direction D1 (such as the upward direction) different from the second direction D2. At the same time, the first distance H1 at the center of the first circuit build-up layer 50 and the core layer 40 is smaller than the second distance H2 at the edge of the first circuit build-up layer 50 and the core layer 40, and the third distance H3 at the center of the second circuit build-up layer 60 and the core layer 40 is smaller than the fourth distance H4 at the edge of the second circuit build-up layer 60 and the core layer 40.
[0149] like Figure 4C As shown in the embodiment of the present invention, the first circuit build-up layer 50 may have a first curved shape toward the first direction D1 (such as the upward direction), and the second circuit build-up layer 60 may have a second curved shape toward the same first direction D1 (such as the upward direction). At the same time, the first distance H1 at the center of the first circuit build-up layer 50 and the core layer 40 is greater than the second distance H2 at the edge of the first circuit build-up layer 50 and the core layer 40, and the third distance H3 at the center of the second circuit build-up layer 60 and the core layer 40 is less than the fourth distance H4 at the edge of the second circuit build-up layer 60 and the core layer 40.
[0150] like Figure 4D As shown in the embodiment of the present invention, the first circuit build-up layer 50 may have a first curved shape toward the second direction D2 (such as the downward direction), and the second circuit build-up layer 60 may have a second curved shape toward the same second direction D2 (such as the downward direction). At the same time, the first distance H1 at the center of the first circuit build-up layer 50 and the core layer 40 is smaller than the second distance H2 at the edge of the first circuit build-up layer 50 and the core layer 40, and the third distance H3 at the center of the second circuit build-up layer 60 and the core layer 40 is larger than the fourth distance H4 at the edge of the second circuit build-up layer 60 and the core layer 40.
[0151] The present application also provides a substrate structure 2, including: a core layer 40, which has a first side 40a and a second side 40b opposite to each other, a plurality of first connection pads 41 and a plurality of second connection pads 42, and the plurality of first connection pads 41 and the plurality of second connection pads 42 of the core layer 40 are formed on the first side 40a and the second side 40b respectively; a first circuit build-up layer 50, which includes a plurality of first bonding pads 56 bonded to the plurality of first connection pads 41 of the core layer 40, wherein the first circuit build-up layer 50 is located on the first side 40a of the core layer 40, and a first gap G1 is provided between the first side 40a of the core layer 40 and the first circuit build-up layer 50; and a second circuit build-up layer 60, which includes a plurality of second bonding pads 66 bonded to the plurality of second connection pads 42 of the core layer 40, wherein the second circuit build-up layer 60 is located on the second side 40b of the core layer 40, and a second gap G2 is provided between the second side 40b of the core layer 40 and the second circuit build-up layer 60.
[0152] In one embodiment, the core layer 40 may have a plurality of conductive vias 43 that penetrate the first side 40 a and the second side 40 b of the core layer 40 to electrically connect the plurality of first connection pads 41 and the plurality of second connection pads 42 .
[0153] In one embodiment, both the first circuit build-up layer 50 and the second circuit build-up layer 60 include at least five circuit layers, and the number of circuit layers of the first circuit build-up layer 50 is the same as the number of circuit layers of the second circuit build-up layer 60 .
[0154] In one embodiment, both the first circuit build-up layer 50 and the second circuit build-up layer 60 include at least five circuit layers, and the number of circuit layers of the first circuit build-up layer 50 is different from the number of circuit layers of the second circuit build-up layer 60 .
[0155] In one embodiment, the substrate structure 2 may include a first encapsulation layer 81 and a second encapsulation layer 82, wherein the first encapsulation layer 81 is formed in a first gap G1 between the first side 40a of the core layer 40 and the first circuit build-up layer 50 to encapsulate a plurality of first connection pads 41 and a plurality of first bonding pads 56, and the second encapsulation layer 82 is formed in a second gap G2 between the second side 40b of the core layer 40 and the second circuit build-up layer 60 to encapsulate a plurality of second connection pads 42 and a plurality of second bonding pads 66.
[0156] In one embodiment, the first circuit build-up layer 50 and the second circuit build-up layer 60 may respectively include a first insulating protection layer 57 having a plurality of first openings 571 and a second insulating protection layer 67 having a plurality of second openings 671, and the first insulating protection layer 57 and the second insulating protection layer 67 are respectively formed on the outermost circuit layer of the first circuit build-up layer 50 and the outermost circuit layer of the second circuit build-up layer 60.
[0157] In one embodiment, the substrate structure 2 may include a plurality of first conductors 71 and a plurality of second conductors 72, wherein a plurality of first bonding pads 56 of the first circuit build-up layer 50 are bonded to a plurality of first connection pads 41 of the core layer 40 through a plurality of first conductors 71, and a plurality of second bonding pads 66 of the second circuit build-up layer 60 are bonded to a plurality of second connection pads 42 of the core layer 40 through a plurality of second conductors 72.
[0158] In one embodiment, the plurality of first connection pads 41, the plurality of second connection pads 42, the plurality of first bonding pads 56 and the plurality of second bonding pads 66 all have metal material, the metal material of the plurality of first bonding pads 56 is directly bonded to the metal material of the plurality of first connection pads 41, and the metal material of the plurality of second bonding pads 66 is directly bonded to the metal material of the plurality of second connection pads 42.
[0159] In one embodiment, the first circuit build-up layer 50 and the second circuit build-up layer 60 respectively have a first curved shape and a second curved shape facing different directions.
[0160] In one embodiment, the first circuit build-up layer 50 and the second circuit build-up layer 60 respectively have a first curved shape and a second curved shape facing the same direction.
[0161] In summary, the substrate structure 2 and the manufacturing method thereof of the present application have at least the following characteristics, advantages or technical effects.
[0162] 1. The present application can divide the substrate structure 2 into a core layer 40, a first circuit build-up layer 50 and a second circuit build-up layer 60 for synchronous (simultaneous) production, which is beneficial to shorten the process or production time of the substrate structure 2, speed up the delivery time of the substrate structure 2, and improve the production yield of the substrate structure 2.
[0163] 2. The present application can manufacture the core layer 40, the first circuit build-up layer 50 and the second circuit build-up layer 60 separately, so as to reduce the number of build-up processes of the first circuit build-up layer 50 and the second circuit build-up layer 60, and can also effectively reduce the cumulative offset N (such as the stacking cumulative offset) of multiple circuit layers or their conductive blind holes of the first circuit build-up layer 50 and the second circuit build-up layer 60.
[0164] 3. The present application can simultaneously manufacture a first circuit build-up layer 50 including at least five circuit layers and a second circuit build-up layer 60 including at least five circuit layers in a separate, synchronous and / or symmetrical manner, which is advantageous in that the more circuit layers the first circuit build-up layer 50 and the second circuit build-up layer 60 have, the higher the efficiency of the build-up process of the substrate structure 2 can be.
[0165] Fourth, when the present application completes the production of a plurality of first circuit build-up layers 50 and second circuit build-up layers 60, the first circuit build-up layers 50 and second circuit build-up layers 60 with higher yields can be combined with the core layer 40 to improve the yield of the substrate structure 2, thereby reducing the risk of low yield.
[0166] 5. Taking the manufacture of a substrate structure 2 including ten circuit layers as an example (such as a first circuit build-up layer 50 including five circuit layers and a second circuit build-up layer 60 including five circuit layers), the present application only needs to perform three build-up processes in total, but the prior art needs to perform five build-up processes. Therefore, the present application can effectively reduce the number of build-up processes of the substrate structure 2, and can also shorten the process or manufacturing time of the substrate structure 2, and can also reduce the cumulative offset N (such as the stacking cumulative offset) of multiple circuit layers or their conductive blind holes of the first circuit build-up layer 50 or the second circuit build-up layer 60.
[0167] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.
Claims
1. A substrate structure, characterized in that: include: A core layer having a first side and a second side opposite to each other, and a plurality of first connection pads and a plurality of second connection pads formed on the first side and the second side respectively; a first circuit build-up layer, comprising a plurality of first bonding pads bonded to the plurality of first connection pads of the core layer, wherein the first circuit build-up layer is located on a first side of the core layer, and a first gap is formed between the first side of the core layer and the first circuit build-up layer; and A second circuit build-up layer includes a plurality of second bonding pads bonded to the plurality of second connection pads of the core layer, wherein the second circuit build-up layer is located on the second side of the core layer, and a second gap is formed between the second side of the core layer and the second circuit build-up layer.
2. The substrate structure according to claim 1, characterized in that: The core layer also has a plurality of conductive through holes which penetrate through the first side and the second side to electrically connect the plurality of first connection pads and the plurality of second connection pads.
3. The substrate structure according to claim 1, characterized in that: The number of circuit layers of the first circuit build-up layer is the same as the number of circuit layers of the second circuit build-up layer.
4. The substrate structure according to claim 1, characterized in that: The number of circuit layers of the first circuit build-up layer is different from the number of circuit layers of the second circuit build-up layer.
5. The substrate structure according to claim 1, characterized in that: The substrate structure also includes a first covering layer and a second covering layer, the first covering layer is formed in the first gap between the first side of the core layer and the first circuit adding layer to cover the plurality of first connection pads and the plurality of first bonding pads, and the second covering layer is formed in the second gap between the second side of the core layer and the second circuit adding layer to cover the plurality of second connection pads and the plurality of second bonding pads.
6. The substrate structure according to claim 1, characterized in that: The first circuit build-up layer and the second circuit build-up layer also respectively include a first insulating protection layer having a plurality of first openings and a second insulating protection layer having a plurality of second openings, and the first insulating protection layer and the second insulating protection layer are respectively formed on the outermost circuit layer of the first circuit build-up layer and the outermost circuit layer of the second circuit build-up layer.
7. The substrate structure according to claim 1, characterized in that: The substrate structure also includes a plurality of first conductors and a plurality of second conductors, through which the plurality of first bonding pads of the first circuit adding layer are bonded to the plurality of first connection pads of the core layer, and the plurality of second bonding pads of the second circuit adding layer are bonded to the plurality of second connection pads of the core layer through the plurality of second conductors.
8. The substrate structure according to claim 1, characterized in that: The first connection pads, the second connection pads, the first bonding pads and the second bonding pads all have metal materials. The metal materials of the first bonding pads are directly bonded to the metal materials of the first connection pads, and the metal materials of the second bonding pads are directly bonded to the metal materials of the second connection pads.
9. The substrate structure according to claim 1, characterized in that: The first circuit build-up layer and the second circuit build-up layer respectively have a first curved shape and a second curved shape facing different directions.
10. The substrate structure according to claim 1, wherein: The first circuit build-up layer and the second circuit build-up layer respectively have a first curved shape and a second curved shape facing the same direction.