Overvoltage protection circuit and electronic equipment

Abstract

The utility model relates to the field of integrated circuits, and discloses an overvoltage protection circuit and electronic equipment. The overvoltage protection circuit comprises a first controlled switch, a second controlled switch, a first resistor and a switching circuit. The control end of the first controlled switch is configured to receive an overvoltage response signal; the first end of the first controlled switch is grounded; the control end of the second controlled switch is configured to receive a first preset reference voltage signal; the first end of the second controlled switch is connected with the second end of the first controlled switch; the first end of the first resistor is connected with the first end of the second controlled switch; the second end of the first resistor is connected with the second end of the second controlled switch; the control end of the switching circuit is connected with the second end of the second controlled switch; the first end of the switching circuit is connected with a preset power supply, and the second end of the switching circuit is configured to be connected with the grid electrode of the power tube. In this way, overvoltage protection can be carried out on components controlled by the power tube. And meanwhile, overvoltage protection can be quickly carried out.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an overvoltage protection circuit and electronic equipment. Background Art

[0002] With the rapid development of electronic technology, electronic devices have covered all aspects of life. However, electronic devices often face various voltage fluctuations and interferences during operation, which may cause overvoltage in some components of electronic devices, thereby damaging these components and causing abnormalities in electronic devices. Therefore, in order to ensure the stable operation of electronic devices, it is necessary to perform overvoltage protection on components when overvoltage occurs.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] The embodiments of the present application provide an overvoltage protection circuit and an electronic device to perform overvoltage protection on components.

[0006] An embodiment of the present application provides an overvoltage protection circuit, including: a first controlled switch, wherein a control end of the first controlled switch is configured to receive an overvoltage response signal; a first end of the first controlled switch is grounded; a second controlled switch, wherein a control end of the second controlled switch is configured to receive a first preset reference voltage signal; a first end of the second controlled switch is connected to a second end of the first controlled switch; a first resistor, wherein a first end of the first resistor is connected to a first end of the second controlled switch; a second end of the first resistor is connected to a second end of the second controlled switch; a switch circuit, wherein a control end of the switch circuit is connected to a second end of the second controlled switch; a first end of the switch circuit is connected to a preset power supply, and a second end of the switch circuit is configured to be connected to a gate of a power tube.

[0007] In the above embodiment, by setting a switch circuit connected to the gate of the power tube, when the component controlled by the power tube is over-voltage, the switch circuit can turn off the power tube, thereby performing over-voltage protection on the component controlled by the power tube. At the same time, since when the voltage at the control end of the second controlled switch is very small, the current will also be very small, and by connecting the first resistor in parallel with the second controlled switch, a current can be generated through the first resistor, thereby improving the response speed of the over-voltage protection circuit, and then quickly performing over-voltage protection.

[0008] Optionally, the switch circuit includes: a third controlled switch, a first end of the third controlled switch is connected to a preset power supply; a second end of the third controlled switch is configured to be connected to a gate of the power tube; a control end of the third controlled switch is connected to the second end of the second controlled switch; a second resistor, a first end of the second resistor is connected to the first end of the third controlled switch; and a second end of the second resistor is connected to the control end of the third controlled switch.

[0009] In the above embodiment, by setting a second resistor connected to the control end of the third controlled switch and the first end of the third controlled switch, when the third controlled switch is turned on, the current flowing from the preset power supply to the control end can be limited, thereby protecting the third controlled switch.

[0010] Optionally, the overvoltage protection circuit further includes: a protection circuit, and the control end of the switch circuit is connected to the second end of the second controlled switch through the protection circuit.

[0011] In the above implementation, the second controlled switch can be protected by providing a protection circuit, thereby reducing the probability of the second controlled switch being damaged, thereby improving the stability of the overvoltage protection circuit.

[0012] Optionally, the protection circuit includes: a fourth controlled switch, a second end of the fourth controlled switch is connected to the control end of the switch circuit; the control end of the fourth controlled switch is configured to receive a second preset reference voltage signal; and a first end of the fourth controlled switch is connected to the second end of the second controlled switch.

[0013] In the above embodiment, the fourth controlled switch will have a voltage drop when it is turned on, so that the voltage at the second end of the second controlled switch will be lower than the voltage when the fourth controlled switch is not connected, thereby reducing the probability of the second controlled switch being damaged and further improving the stability of the overvoltage protection circuit.

[0014] Optionally, the overvoltage protection circuit further includes: a clamping circuit, a first end of the clamping circuit is connected to a preset power supply, and a second end of the clamping circuit is connected to a control end of the switch circuit.

[0015] In the above embodiment, by providing a clamping circuit, the voltage at the control end of the switch circuit can be clamped to a suitable voltage, thereby protecting the switch circuit.

[0016] Optionally, the clamping circuit includes: a plurality of MOS tubes connected in series in a diode connection method.

[0017] In the above embodiment, the diode-connected MOS (MOSFET, metal oxide semiconductor field effect transistor) tube can have a reverse voltage tolerance capability far higher than that of an ordinary diode. In addition, the diode-connected MOS tube does not require a reverse recovery time, and its switching speed is faster. Therefore, the use of a diode-connected MOS tube as a clamping circuit can control the voltage of the control end of the switch circuit to a suitable voltage, while making the circuit more stable.

[0018] Optionally, the multiple MOS tubes connected in series according to the diode connection method are PMOS tubes, and the clamping circuit includes: a first PMOS tube, the source of the first PMOS tube is connected to the preset power supply, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube; a second PMOS tube, the source of the second PMOS tube is connected to the drain of the first PMOS tube, and the gate of the second PMOS tube is connected to the drain of the second PMOS tube; a third PMOS tube, the source of the third PMOS tube is connected to the drain of the second PMOS tube, and the gate of the third PMOS tube is connected to the drain of the third PMOS tube; a fourth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube and the control end of the switch circuit.

[0019] In the above implementation, each diode-connected PMOS tube acts as a diode, and by arranging four diode-connected PMOS tubes in series, the voltage at the control end of the switch circuit can be clamped to a suitable voltage, thereby protecting the switch circuit.

[0020] Optionally, the overvoltage protection circuit further includes: a signal driving circuit, one end of the signal driving circuit is used to receive the overvoltage response signal; and the other end of the signal driving circuit is connected to the control end of the first controlled switch.

[0021] In the above implementation, the driving capability of the overvoltage response signal can be improved by the signal driving circuit, thereby increasing the anti-interference capability of the overvoltage response signal and reducing the signal loss of the overvoltage response signal, thereby enabling the overvoltage protection circuit to operate stably and reliably.

[0022] Optionally, the signal driving circuit includes: a first inverter, an input end of the first inverter is used to receive the overvoltage response signal; a second inverter, an input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter is connected to a control end of the first controlled switch.

[0023] In the above implementation, the driving capability of the overvoltage response signal can be improved by providing two inverters, while keeping the phase of the overvoltage response signal unchanged.

[0024] An embodiment of the present application provides an electronic device, comprising the above-mentioned overvoltage protection circuit.

[0025] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0027] Figure 1 is a structural schematic diagram of a first overvoltage protection circuit provided in an embodiment of the present application;

[0028] Figure 2 is a structural schematic diagram of a second overvoltage protection circuit provided in an embodiment of the present application;

[0029] Figure 3 is a structural schematic diagram of a third overvoltage protection circuit provided in an embodiment of the present application;

[0030] Figure 4 is a structural schematic diagram of a fourth overvoltage protection circuit provided in an embodiment of the present application;

[0031] Figure 5 It is a structural schematic diagram of the fifth overvoltage protection circuit provided in an embodiment of the present application.

[0032] Reference numerals:

[0033] 1: first controlled switch; 2: second controlled switch; 3: first resistor; 4: switch circuit; 5: first NMOS tube; 6: second NMOS tube; 7: fifth PMOS tube; 8: second resistor; 9: third NMOS tube; 10: first PMOS tube; 11: second PMOS tube; 12: third PMOS tube; 13: fourth PMOS tube; 14: first inverter; 15: second inverter. DETAILED DESCRIPTION

[0034] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0035] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0037] Unless otherwise stated, the term "plurality" means two or more.

[0038] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0039] Embodiment 1

[0040] Combination Figure 1 As shown, an overvoltage protection circuit is provided in an embodiment of the present application, comprising: a first controlled switch 1, a second controlled switch 2, a first resistor 3 and a switch circuit 4. The control end of the first controlled switch 1 is configured to receive an overvoltage response signal, and the first end of the first controlled switch 1 is grounded. The control end of the second controlled switch 2 is configured to receive a first preset reference voltage signal, and the first end of the second controlled switch 2 is connected to the second end of the first controlled switch 1. The first end of the first resistor 3 is connected to the first end of the second controlled switch 2, and the second end of the first resistor 3 is connected to the second end of the second controlled switch 2. The control end of the switch circuit 4 is connected to the second end of the second controlled switch 2, the first end of the switch circuit 4 is connected to the preset power supply, and the second end of the switch circuit 4 is configured to be connected to the gate of the power tube.

[0041] Among them, the power tube can be used to control the on and off between the power supply and the load.

[0042] Among them, the first controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, triode, optocoupler, thyristor, etc., which is not limited here.

[0043] Among them, the second controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, triode, optocoupler, thyristor, etc., which is not limited here.

[0044] In some embodiments, the first preset reference voltage signal is a reference voltage signal provided by an external circuit, and the signal may be always high, so that the second controlled switch is always turned on.

[0045] In some embodiments, the switch circuit may include: a third controlled switch and a second resistor. The first end of the third controlled switch is connected to a preset power supply, the second end of the third controlled switch is configured to be connected to the gate of the power tube, and the control end of the third controlled switch is connected to the second end of the second controlled switch. The first end of the second resistor is connected to the first end of the third controlled switch, and the second end of the second resistor is connected to the control end of the third controlled switch.

[0046] Among them, the third controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, triode, optocoupler, thyristor, etc., which is not limited here.

[0047] Exemplarily, the switch circuit may include a third controlled switch and a second resistor. The first controlled switch is a first NMOS transistor, the second controlled switch is a second NMOS transistor, and the third controlled switch is a fifth PMOS transistor. Figure 2As shown, the gate of the first NMOS tube 5 is configured to receive an overvoltage response signal (OVP), the source of the first NMOS tube 5 is grounded, and the drain of the first NMOS tube 5 is connected to the source of the second NMOS tube 6. The gate of the second NMOS tube 6 is configured to receive a first preset reference voltage signal (VBIAS1), and the drain of the second NMOS tube 6 is connected to the gate of the fifth PMOS tube 7. The first end of the first resistor 3 is connected to the source of the second NMOS tube 6, and the second end of the first resistor 3 is connected to the drain of the second NMOS tube 6. The source of the fifth PMOS tube 7 is connected to a preset power supply (VCC), the drain of the fifth PMOS tube 7 serves as the output (VOUT) of the overvoltage protection circuit, and the drain of the fifth PMOS tube 7 is configured to be connected to the gate of the power tube. The first end of the second resistor 8 is connected to the source of the fifth PMOS tube 7, and the second end of the second resistor 8 is connected to the gate of the fifth PMOS tube 7.

[0048] In some embodiments, the overvoltage protection circuit further includes: a protection circuit. The control end of the switch circuit is connected to the second end of the second controlled switch through the protection circuit.

[0049] In an optional manner of the above embodiment, the protection circuit includes: a fourth controlled switch. The second end of the fourth controlled switch is connected to the control end of the switch circuit; the control end of the fourth controlled switch is configured to receive a second preset reference voltage signal; and the first end of the fourth controlled switch is connected to the second end of the second controlled switch.

[0050] In some embodiments, the second preset reference voltage signal may be an enable signal, which is generally high and low only when a fault occurs. The fault may be, for example, that the voltage of the power supply is too low. It is understood that the voltage being too low may be a voltage value lower than a preset voltage value. The preset voltage value may be set by an engineer according to actual needs.

[0051] Exemplarily, the switch circuit may include a third controlled switch and a second resistor. The protection circuit includes a fourth controlled switch. The first controlled switch is a first NMOS transistor, the second controlled switch is a second NMOS transistor, and the third controlled switch is a fifth PMOS transistor. The fourth controlled switch is a third NMOS transistor. Figure 3As shown, the gate of the first NMOS tube 5 is configured to receive an overvoltage response signal, the source of the first NMOS tube 5 is grounded, and the drain of the first NMOS tube 5 is connected to the source of the second NMOS tube 6. The gate of the second NMOS tube 6 is configured to receive a first preset reference voltage signal, and the drain of the second NMOS tube 6 is connected to the source of the third NMOS tube 9. The gate of the third NMOS tube 9 is configured to receive a second preset reference voltage signal (VBIAS2), and the drain of the third NMOS tube 9 is connected to the gate of the fifth PMOS tube 7. The first end of the first resistor 3 is connected to the source of the second NMOS tube 6, and the second end of the first resistor 3 is connected to the drain of the second NMOS tube 6. The source of the fifth PMOS tube 7 is connected to a preset power supply, and the drain of the fifth PMOS tube 7 is configured to be connected to the gate of the power tube. The first end of the second resistor 8 is connected to the source of the fifth PMOS tube 7, and the second end of the second resistor 8 is connected to the gate of the fifth PMOS tube 7.

[0052] In some embodiments, the overvoltage protection circuit may further include: a clamping circuit, wherein a first end of the clamping circuit is connected to a preset power source, and a second end of the clamping circuit is connected to a control end of the switch circuit.

[0053] In the above embodiment, the clamping circuit may include: a plurality of MOS transistors connected in series in a diode connection method.

[0054] It can be understood that the diode connection method can be a source connection method in the diode connection method, that is, the gate and drain of the MOS tube are connected.

[0055] It can be understood that the number of MOS tubes connected in a diode connection method can be set by engineers according to actual usage requirements. For example, two MOS tubes connected in a diode connection method can be connected in series, or three MOS tubes connected in a diode connection method can be connected in series.

[0056] Exemplarily, the multiple MOS tubes connected in series according to the diode connection method are PMOS tubes. The clamping circuit may include: a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube. Among them, the source of the first PMOS tube is connected to a preset power supply, and the gate of the first PMOS tube is connected to the drain of the first PMOS tube. The source of the second PMOS tube is connected to the drain of the first PMOS tube, and the gate of the second PMOS tube is connected to the drain of the second PMOS tube. The source of the third PMOS tube is connected to the drain of the second PMOS tube, and the gate of the third PMOS tube is connected to the drain of the third PMOS tube. The source of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube and the control end of the switch circuit.

[0057] Exemplarily, the switch circuit may include a third controlled switch and a second resistor. The protection circuit may include a fourth controlled switch. The clamp circuit may include: a first PMOS tube, a second PMOS tube, a third PMOS tube, and a fourth PMOS tube. The first controlled switch is a first NMOS tube, the second controlled switch is a second NMOS tube, and the third controlled switch is a fifth PMOS tube. The fourth controlled switch is a third NMOS tube. Figure 4 As shown, the gate of the first NMOS tube 5 is configured to receive an overvoltage response signal, the source of the first NMOS tube 5 is grounded, and the drain of the first NMOS tube 5 is connected to the source of the second NMOS tube 6. The gate of the second NMOS tube 6 is configured to receive a first preset reference voltage signal, and the drain of the second NMOS tube 6 is connected to the source of the third NMOS tube 9. The gate of the third NMOS tube 9 is configured to receive a second preset reference voltage signal, and the drain of the third NMOS tube 9 is connected to the gate of the fifth PMOS tube 7 and the drain of the fourth PMOS tube 13. The first end of the first resistor 3 is connected to the source of the second NMOS tube 6, and the second end of the first resistor 3 is connected to the drain of the second NMOS tube 6. The source of the fifth PMOS tube 7 is connected to a preset power supply, and the drain of the fifth PMOS tube 7 is configured to be connected to the gate of the power tube. The first end of the second resistor 8 is connected to the source of the fifth PMOS tube 7, and the second end of the second resistor 8 is connected to the gate of the fifth PMOS tube 7. The gate of the fourth PMOS tube 13 is connected to the drain of the fourth PMOS tube 13, and the source of the fourth PMOS tube 13 is connected to the drain of the third PMOS tube 12. The gate of the third PMOS tube 12 is connected to the drain of the third PMOS tube 12, and the source of the third PMOS tube 12 is connected to the drain of the second PMOS tube 11. The gate of the second PMOS tube 11 is connected to the drain of the second PMOS tube 11. The source of the second PMOS tube 11 is connected to the drain of the first PMOS tube 10, the gate of the first PMOS tube 10 is connected to the drain of the first PMOS tube 10, and the source of the first PMOS tube 10 is connected to a preset power supply.

[0058] In some embodiments, the overvoltage protection circuit further includes: a signal driving circuit. One end of the signal driving circuit is used to receive the overvoltage response signal; and the other end of the signal driving circuit is connected to the control end of the first controlled switch.

[0059] In the above embodiment, the signal driving circuit includes: a first inverter and a second inverter. The input end of the first inverter is used to receive the overvoltage response signal. The input end of the second inverter is connected to the output end of the first inverter, and the output end of the second inverter is connected to the control end of the first controlled switch.

[0060] Exemplarily, the switch circuit may include a third controlled switch and a second resistor. The protection circuit may include a fourth controlled switch. The clamp circuit may include: a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube. The signal drive circuit may include a first inverter and a second inverter. The first controlled switch is a first NMOS tube, the second controlled switch is a second NMOS tube, and the third controlled switch is a fifth PMOS tube. The fourth controlled switch is a third NMOS tube. Figure 5As shown, the input end of the first inverter 14 is used to receive the overvoltage response signal, the output end of the first inverter 14 is connected to the input end of the second inverter 15, the power supply end of the first inverter 14 is connected to the power supply (VDD), and the ground end of the first inverter 14 is grounded (GND). The output end of the second inverter 15 is connected to the gate of the first NMOS tube 5, the power supply end of the second inverter 15 is connected to the power supply, and the ground end of the second inverter 15 is grounded. The source of the first NMOS tube 5 is grounded, and the drain of the first NMOS tube 5 is connected to the source of the second NMOS tube 6. The gate of the second NMOS tube 6 is configured to receive the first preset reference voltage signal, and the drain of the second NMOS tube 6 is connected to the source of the third NMOS tube 9. The gate of the third NMOS tube 9 is configured to receive the second preset reference voltage signal, and the drain of the third NMOS tube 9 is connected to the gate of the fifth PMOS tube 7 and the drain of the fourth PMOS tube 13. The first end of the first resistor 3 is connected to the source of the second NMOS tube 6, and the second end of the first resistor 3 is connected to the drain of the second NMOS tube 6. The source of the fifth PMOS tube 7 is connected to the preset power supply, and the drain of the fifth PMOS tube 7 is configured to be connected to the gate of the power tube. The first end of the second resistor 8 is connected to the source of the fifth PMOS tube 7, and the second end of the second resistor 8 is connected to the gate of the fifth PMOS tube 7. The gate of the fourth PMOS tube 13 is connected to the drain of the fourth PMOS tube 13, and the source of the fourth PMOS tube 13 is connected to the drain of the third PMOS tube 12. The gate of the third PMOS tube 12 is connected to the drain of the third PMOS tube 12, and the source of the third PMOS tube 12 is connected to the drain of the second PMOS tube 11. The gate of the second PMOS tube 11 is connected to the drain of the second PMOS tube 11. The source of the second PMOS tube 11 is connected to the drain of the first PMOS tube 10, the gate of the first PMOS tube 10 is connected to the drain of the first PMOS tube 10, and the source of the first PMOS tube 10 is connected to the preset power supply. In this way, when overvoltage protection is not required, the overvoltage response signal is a low-level signal, the first NMOS tube is turned off, no current flows through the branch where the first NMOS tube is located, and the voltage at point A is equal to the voltage of the preset power supply. The gate voltage of the fifth PMOS tube is equal to the voltage of the preset power supply, and the source voltage of the fifth PMOS tube is equal to the voltage of the preset power supply, that is, the gate-source voltage of the fifth PMOS tube is 0, the fifth PMOS tube is turned off, and the overvoltage protection circuit has no output to the gate of the power tube, which does not affect the switching state of the power tube.When overvoltage protection is required, the overvoltage response signal is a high-level signal, the first NMOS tube is turned on, and current flows through the branch where the first NMOS tube is located, and the voltage at point A drops. Since four PMOS tubes connected in a diode manner are set as a clamping circuit, the voltage at point A is equal to the voltage of the preset power supply minus the gate-source voltage of the four PMOS tubes in the clamping circuit, thereby preventing the voltage at point A from being too low when the first NMOS tube is turned on, causing the gate-source voltage of the fifth PMOS tube to be too high, thereby damaging the fifth PMOS tube. At this time, the gate voltage of the fifth PMOS tube is equal to the voltage of the preset power supply minus the gate-source voltage of the four PMOS tubes, and the source voltage of the fifth PMOS tube is equal to the voltage of the preset power supply, thereby the gate-source voltage of the fifth PMOS tube is equal to the gate-source voltage of the four PMOS tubes in the clamping circuit, and the fifth PMOS tube is turned on. Because the width-to-length ratio of the fifth PMOS tube is large and the internal resistance is very small, at this time, the drain output voltage of the fifth PMOS tube will be quickly pulled up to the voltage of the preset power supply, achieving a fast overvoltage protection response. At the same time, since the gate-drain breakdown voltage of the second controlled switch is 5V (volts). By setting the fourth controlled switch as an independent device, assuming that the gate input of the fourth controlled switch is a large voltage of 5V, the drain voltage of the second controlled switch is 5-the gate-source voltage of the fourth controlled switch, so that the drain voltage of the second controlled switch is less than 5V, thereby protecting the second controlled switch. By setting the first resistor, when the gate voltage of the second controlled switch and the fourth controlled switch is very small, the current is very small, and a current is generated through the first resistor, and the current is (the voltage at point A-Vod) / the resistance value of the first resistor, so that the circuit response speed is improved. By changing the resistance value of the first resistor, the conduction speed of the power tube can be controlled, thereby changing the response speed of the output. Among them, the voltage of Vod is the sum of the voltage from the drain to the source of the first NMOS tube 5 and the voltage from the drain to the source of the third NMOS tube 9.

[0061] An electronic device is provided in an embodiment of the present application, comprising the above-mentioned overvoltage protection circuit. The electronic device disclosed in the present application is adopted, by setting an overvoltage protection circuit including components such as a first controlled switch, a second controlled switch, a first resistor and a switch circuit in the electronic device, and by setting a switch circuit connected to the gate of the power tube, when an overvoltage occurs in the power tube, the switch circuit can turn off the power tube, thereby performing overvoltage protection on the components in the circuit connected to the power tube. At the same time, since the current is also very small when the control terminal voltage of the second controlled switch is very small, a current can be generated by connecting the first resistor in parallel with the second controlled switch, thereby increasing the response speed of the overvoltage protection circuit, and thus enabling rapid overvoltage protection.

[0062] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An overvoltage protection circuit, characterized in that: include: a first controlled switch, wherein a control terminal of the first controlled switch is configured to receive an overvoltage response signal; A first terminal of the first controlled switch is grounded; a second controlled switch, wherein a control end of the second controlled switch is configured to receive a first preset reference voltage signal; a first end of the second controlled switch is connected to a second end of the first controlled switch; a first resistor, wherein a first end of the first resistor is connected to a first end of the second controlled switch; and a second end of the first resistor is connected to a second end of the second controlled switch; A switch circuit, wherein the control end of the switch circuit is connected to the second end of the second controlled switch; the first end of the switch circuit is connected to a preset power supply, and the second end of the switch circuit is configured to be connected to the gate of the power tube.

2. The overvoltage protection circuit according to claim 1, characterized in that: The switch circuit comprises: a third controlled switch, wherein a first end of the third controlled switch is connected to a preset power source; a second end of the third controlled switch is configured to be connected to a gate of the power tube; and a control end of the third controlled switch is connected to a second end of the second controlled switch; A second resistor, wherein a first end of the second resistor is connected to a first end of the third controlled switch; and a second end of the second resistor is connected to a control end of the third controlled switch.

3. The overvoltage protection circuit according to claim 1, characterized in that: The overvoltage protection circuit further includes: A protection circuit, wherein the control end of the switch circuit is connected to the second end of the second controlled switch through the protection circuit.

4. The overvoltage protection circuit according to claim 3, characterized in that: The protection circuit comprises: A fourth controlled switch, wherein the second end of the fourth controlled switch is connected to the control end of the switch circuit; the control end of the fourth controlled switch is configured to receive a second preset reference voltage signal; and the first end of the fourth controlled switch is connected to the second end of the second controlled switch.

5. The overvoltage protection circuit according to any one of claims 1 to 4, characterized in that: The overvoltage protection circuit further includes: A clamping circuit, wherein a first end of the clamping circuit is connected to a preset power supply, and a second end of the clamping circuit is connected to a control end of the switch circuit.

6. The overvoltage protection circuit according to claim 5, characterized in that: The clamping circuit includes: a plurality of MOS tubes connected in series in a diode connection method.

7. The overvoltage protection circuit according to claim 6, characterized in that: The plurality of MOS tubes connected in series according to the diode connection method are PMOS tubes, and the clamping circuit includes: a first PMOS tube, wherein a source of the first PMOS tube is connected to the preset power supply, and a gate of the first PMOS tube is connected to a drain of the first PMOS tube; a second PMOS tube, wherein a source of the second PMOS tube is connected to a drain of the first PMOS tube, and a gate of the second PMOS tube is connected to a drain of the second PMOS tube; a third PMOS tube, wherein the source of the third PMOS tube is connected to the drain of the second PMOS tube, and the gate of the third PMOS tube is connected to the drain of the third PMOS tube; A fourth PMOS tube, wherein the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube and the control end of the switch circuit.

8. The overvoltage protection circuit according to any one of claims 1 to 4, characterized in that: The overvoltage protection circuit further includes: A signal driving circuit, one end of which is used to receive the overvoltage response signal; and the other end of which is connected to the control end of the first controlled switch.

9. The overvoltage protection circuit according to claim 8, characterized in that: The signal driving circuit comprises: A first inverter, wherein an input terminal of the first inverter is used to receive the overvoltage response signal; A second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the first inverter, and an output terminal of the second inverter is connected to a control terminal of the first controlled switch.

10. An electronic device, characterized in that: The invention comprises an overvoltage protection circuit as claimed in any one of claims 1 to 9.

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