Low-ripple large-current buck-boost device

Abstract

The utility model discloses a low-ripple heavy-current buck-boost device, which relates to the technical field of power supply management and comprises a shell, a buck-boost circuit is arranged in the shell and comprises a switching power supply chip, the switching power supply chip is respectively connected with a high-voltage side buck MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) circuit and a low-voltage side boost MOSFET circuit, and the high-voltage side buck MOSFET circuit is connected with the low-voltage side boost MOSFET circuit. The buck-boost circuit is connected with the power supply input end through the overvoltage protection circuit; the high-voltage side step-down MOSFET circuit and the low-voltage side step-down MOSFET circuit are adopted to automatically replace a step-up mode and a step-down mode, output ripples are reduced, and by arranging the overvoltage protection circuit, the situation that the circuit is damaged due to the fact that too large input voltage is connected is prevented.

Description

Technical Field

[0001] The utility model relates to the technical field of power management, in particular to a low-ripple large-current step-up and step-down device. Background Art

[0002] The efficiency of the switching DC-DC module power supply is high, generally above 80%, and some even reach above 95%. High conversion efficiency is the outstanding advantage of this type of power supply device, making them widely used in various electronic products. However, the output ripple of the switching DC-DC power supply device is large, generally above 100mV. Some improved switching power supply modules can also achieve about 50mV, such as the power supply modules of Vicor Corporation of the United States, which are now widely used in China; the modules produced by domestic manufacturers themselves have a ripple of about 150mV. Due to its large ripple, various filtering measures must be taken in many occasions to ensure the normal operation of electronic equipment and meet the requirements of electromagnetic compatibility testing; in addition, it also limits their application in some occasions where low ripple power supplies are required.

[0003] For example, Chinese patent CN111262434A, published on June 9, 2020, discloses a buck-boost DC-DC converter and control method to achieve smooth switching from the boost mode to the buck-boost mode, and from the buck-boost mode to the buck mode of the DC-DC converter. The buck-boost DC-DC converter is simple to control. It subtracts the inductor current sampling signal from the error voltage signal and combines two slope compensation signals to achieve flip control of the buck comparator and the boost comparator, thereby enabling the converter to operate in different buck-boost modes, and making the converter switch between the boost mode to the buck-boost mode, and from the buck-boost mode to the buck mode smoother, with smaller current ripple and voltage ripple. The ripple of the device still cannot meet the existing use requirements. Utility Model Content

[0004] The technical problem to be solved by the utility model is that the existing switch DC-DC module power supply has high output ripple and low output current. A low ripple and high current buck-boost device is proposed, which can effectively reduce the ripple, has a larger input voltage range and a higher output current.

[0005] In order to solve the above technical problems, the technical solution adopted by the utility model is: a low ripple and large current buck-boost device, including a shell, a buck-boost circuit is arranged in the shell, the buck-boost circuit includes a switching power supply chip, the switching power supply chip is respectively connected to the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit, and the buck-boost circuit is connected to the power input terminal through an overvoltage protection circuit.

[0006] A low-ripple, high-current buck-boost device, a switching power supply chip integrating high-side and low-side gate drivers, can realize the transition between boost mode and buck mode through the high-side buck MOSFET circuit and the low-voltage side boost MOSFET circuit, and improve the value range of the usable input voltage while reducing the output ripple.

[0007] Preferably, the low-voltage side boost MOSFET circuit includes a field effect tube Q2, and the high-voltage side buck MOSFET circuit includes a field effect tube Q3. The magnitude of the input current is detected to control the opening and closing of the field effect tube Q2 and the field effect tube Q3 to realize the transition between the boost mode and the buck mode. The change of the boost mode or the buck mode is controlled by controlling the opening and closing of the field effect tube Q3 and the field effect tube Q2.

[0008] Preferably, the overvoltage protection circuit includes a field effect tube T1, the source of the field effect tube T1 is connected to the power input terminal, the source of the field effect tube T1 is connected to the base and emitter of the triode Q1, the collector of the triode Q1 is connected to the gate of the field effect tube T1, the base of the triode Q1 is connected to the cathode of the voltage zener diode ZD1, and the collector of the triode Q1 is connected to the anode of the voltage zener diode ZD1. The voltage zener diode ZD1 is used to determine whether the voltage is too large, and the circuit is protected by opening and closing the field effect tube T1.

[0009] Preferably, the switching power supply chip is connected to a control circuit, the control circuit includes a capacitor C15, and the control circuit controls the switching power supply chip through a current mode of emulating a current ramp. Emulated current mode control can reduce the noise sensitivity of the pulse width modulation circuit so as to reliably control high input voltages.

[0010] Preferably, the switching power supply chip is connected to an oscillating circuit, and the oscillating circuit includes a resistor R4. The resistor R4 affects the oscillation frequency.

[0011] Preferably, the switching power supply chip is connected to a loop compensation circuit, and the loop compensation circuit includes a capacitor C41 and a capacitor C42. The loop compensation circuit affects the error amplifier.

[0012] Preferably, the switch power supply chip is connected to a soft start circuit, which protects the entire circuit.

[0013] Preferably, the switching power supply chip is connected to the exposed chip connection pad to improve heat dissipation efficiency.

[0014] The substantial effect of the utility model is as follows: the utility model adopts a switching power supply chip with integrated high-side and low-side gate drivers, and adopts a high-side buck MOSFET circuit and a low-voltage side boost MOSFET circuit to automatically switch between boost and buck modes, thereby reducing output ripple and increasing the applicable voltage range; and by setting an overvoltage protection circuit, it prevents the circuit from being damaged by an excessively large input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit diagram of embodiment 1. DETAILED DESCRIPTION

[0016] The specific implementation of the utility model is further described below through specific embodiments and in conjunction with the accompanying drawings.

[0017] Embodiment one:

[0018] A low ripple high current buck-boost device, such as Figure 1 As shown, the device housing contains the circuit shown in the figure, which mainly includes the switch control chip U2, which converts the input voltage in the input range of 3V to 42V into an output voltage of 5V. The switch control chip U2 is a DC-DC buck-boost converter, which adopts simulated peak current mode control and can smoothly switch between buck and boost modes. The switching frequency can be programmed to 500kHz at most, and it has an oscillator synchronization function. A high-voltage bias regulator is set internally, integrating high-side and low-side gate drivers. Programmable soft start time, ultra-low shutdown current, enable input, wide-bandwidth error amplifier, 1.5% feedback reference accuracy, and thermal shutdown function.

[0019] The switch control chip U2 and the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit control the transition between the boost mode and the buck mode of the switch control chip U2 through the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit. The pin HS of the switch control chip U2 is connected to the source of the field effect tube Q3, the pin HO of the switch control chip U2 is connected to the gate of the field effect tube Q3, and the drain of the field effect tube Q3 is connected to the power input terminal, thereby forming a high-voltage side buck MOSFET circuit. The pin LO of the switch control chip U2 is connected to the gate of the field effect tube Q2, the source of the field effect tube Q2 is connected to the pin VCC of the switch control chip U2, and the drain of the field effect tube Q2 is connected to the pin HS of the switch control chip U2, thereby forming a low-voltage side boost MOSFET circuit. The transition between the boost mode and the buck mode is controlled by controlling the opening and closing of the field effect tube Q2 and the field effect tube Q3.

[0020] The pins CS and CSG of the switch control chip U2 are connected to the current sensing circuit to detect whether the current after the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit are boosted or bucked meets the requirements. Its main structure includes two zener diodes D2 and D3 connected in parallel. The output end of the zener diode D2 is connected to one end of the resistor R17 and the resistor R14, respectively, and the other end of the resistor R17 is connected to the pin CSG of the switch control chip U2 and the source of the field effect tube Q2. The other end of the resistor R14 is connected to the pin CS of the switch control chip U2 and one end of the capacitor C23, respectively. The other end of the capacitor C23 is connected to the pin CSG of the switch control chip U2. The input end of the zener diode D3 is connected to the source of the field effect tube Q3, and the output end of the zener diode D3 is connected to one end of the capacitor C18 and the capacitor C19 in parallel, and the other end is connected to the pin CSG of the switch control chip U2.

[0021] The pin VIN of the switch control chip U2 is connected to the power output terminal, and a capacitor C14 is connected in series to the pin VIN as a filter capacitor. The pin UVLO of the switch control chip U2 is connected to one end of the resistor R3 and one end of the resistor R8 respectively, the other end of the resistor R8 is connected to the power input terminal, the other end of the resistor R3 is grounded, and a capacitor C13 is connected in parallel to the resistor R3. If the UVLO pin is lower than 1.23V, the regulator will be in standby mode (VCC regulator is running and the switching regulator is disabled). When the UVLO pin exceeds 1.23V, the regulator enters normal operating mode. An external voltage divider can be used to set the undervoltage shutdown threshold. The UVLO pin outputs a fixed 5-μA current. If the current limit condition exists for 256 consecutive switching cycles, the internal switch pulls the UVLO pin together and then releases it. The pin RT of the switch control chip U2 is connected to the oscillation circuit, which includes a resistor R4. The size of the resistor R4 affects the internal oscillation frequency of the switch control chip U2. The frequency range is 50kHz to 500kHz. In this embodiment, the frequency is set to 100kHz. The pin EN of the switch control chip U2 is connected to the power input terminal through the resistor R2. If the EN pin is lower than 0.5V, the regulator will be in a low power state and VIN is less than 10μa. EN must be increased to more than 3V to operate normally.

[0022] The RAMP pin of the switch control chip U2 is connected to one end of the capacitor C15, and the other end of the capacitor C15 is grounded. The slope of the current mode of the simulated current ramp is controlled according to the size of the capacitor C15, thereby controlling the operation of the switch control chip U2. The simulated current mode control can reduce the noise sensitivity of the pulse width modulation circuit so that high input voltages can be reliably controlled, and the duty cycle required in the application is extremely small.

[0023] Pin SS of the switch control chip U2 is connected to the soft start circuit. An external capacitor and an internal 10μA current source set the rise time of the error amplifier reference. The SS pin remains low when VCC is below the VCC undervoltage threshold (less than 3.7V), the UVLO pin is low (less than 1.23V), EN is low (less than 0.5V), or the thermal shutdown is activated. The soft start circuit includes capacitor C16, one end of which is connected to pin SS of the switch control chip U2, and the other end of capacitor C16 is grounded.

[0024] Pin FB of the switch control chip U2 is connected to one end of the resistor R16, and the other end of the resistor R16 is grounded. Pin FB of the switch control chip U2 is connected to the inverting input of the internal error amplifier, and a feedback signal is input to control the transition of the boost mode or buck mode. Pin COMP of the switch control chip U2 is connected to the loop compensation circuit. The loop compensation circuit includes capacitor C41 and capacitor C42. Pin COMP of the switch control chip U2 is connected to one end of the resistor R9 and capacitor C42 respectively, the other end of the resistor R9 is connected to one end of the capacitor C41, and the other end of the capacitor C41 and the other end of the capacitor C42 are connected to pin FB of the switch control chip U2. Capacitor C42 introduces an additional pole to eliminate high-frequency switching noise. If the crossover frequency is much lower than the right half plane zero frequency, the error amplifier zero offsets the modulator pole, leaving a single attitude response at the crossover frequency of the loop gain. The single-pole response at the crossover frequency produces a very stable loop with a 90-degree phase margin. The error amplifier zero should be chosen at a frequency close to the modulator pole and well below the target crossover frequency. This limits the product of resistor R9 and capacitor C41 for the required compensation network zero. Increasing resistor R9 while proportionally reducing capacitor C41 increases the error amplifier gain. Conversely, decreasing resistor R9 while proportionally increasing capacitor C41 decreases the error amplifier gain. The total loop gain can be predicted as the sum of the modulator gain and the error amplifier gain in dB. If a network analyzer is available, the modulator gain can be measured and the error amplifier gain configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed according to the guidelines given. Step load transient testing can be performed to verify acceptable performance. The step load goal is to achieve minimum overshoot with a damped response.

[0025] The pin VOUT of the switch control chip U2 is connected to the regulated output voltage monitoring circuit. The pin VOUT of the switch control chip U2 is respectively connected to one end of the resistor R29 and one end of the capacitor C24, the other end of the resistor E29 is connected to one end of the resistor R28, and the other end of the resistor R28 and the other end of the capacitor C24 are connected to the pin FB of the switch control chip U2.

[0026] Embodiment 2:

[0027] The switch control chip U2 in this embodiment is connected to the high-side buck MOSFET circuit and the low-side boost MOSFET circuit, and the transition between the boost mode and the buck mode of the switch control chip U2 is controlled by the high-side buck MOSFET circuit and the low-side boost MOSFET circuit. The pin HS of the switch control chip U2 is connected to the source of the field effect tube Q3, the pin HO of the switch control chip U2 is connected to the gate of the field effect tube Q3, and the drain of the field effect tube Q3 is connected to the power input terminal, thereby forming a high-side buck MOSFET circuit. The pin LO of the switch control chip U2 is connected to the gate of the field effect tube Q2, the source of the field effect tube Q2 is connected to the pin VCC of the switch control chip U2, and the drain of the field effect tube Q2 is connected to the pin HS of the switch control chip U2, thereby forming a low-voltage side boost MOSFET circuit. The transition between the boost mode and the buck mode is controlled by controlling the opening and closing of the field effect tube Q2 and the field effect tube Q3.

[0028] The pins CS and CSG of the switch control chip U2 are connected to the current sensing circuit to detect whether the current after the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit are boosted or bucked meets the requirements. Its main structure includes two zener diodes D2 and D3 connected in parallel. The output end of the zener diode D2 is connected to one end of the resistor R17 and the resistor R14, respectively, and the other end of the resistor R17 is connected to the pin CSG of the switch control chip U2 and the source of the field effect tube Q2. The other end of the resistor R14 is connected to the pin CS of the switch control chip U2 and one end of the capacitor C23, respectively. The other end of the capacitor C23 is connected to the pin CSG of the switch control chip U2. The input end of the zener diode D3 is connected to the source of the field effect tube Q3, and the output end of the zener diode D3 is connected to one end of the capacitor C18 and the capacitor C19 in parallel, and the other end is connected to the pin CSG of the switch control chip U2.

[0029] The pin VIN of the switch control chip U2 is connected to the power output terminal, and a capacitor C14 is connected in series to the pin VIN as a filter capacitor. The pin UVLO of the switch control chip U2 is connected to one end of the resistor R3 and one end of the resistor R8 respectively, the other end of the resistor R8 is connected to the power input terminal, the other end of the resistor R3 is grounded, and a capacitor C13 is connected in parallel to the resistor R3. If the UVLO pin is lower than 1.23V, the regulator will be in standby mode (VCC regulator is running and the switching regulator is disabled). When the UVLO pin exceeds 1.23V, the regulator enters normal operating mode. An external voltage divider can be used to set the undervoltage shutdown threshold. The UVLO pin outputs a fixed 5-μA current. If the current limit condition exists for 256 consecutive switching cycles, the internal switch pulls the UVLO pin together and then releases it. The pin RT of the switch control chip U2 is connected to the oscillation circuit, which includes a resistor R4. The size of the resistor R4 affects the internal oscillation frequency of the switch control chip U2. The frequency range is 50kHz to 500kHz. In this embodiment, the frequency is set to 100kHz. The pin EN of the switch control chip U2 is connected to the power input terminal through the resistor R2. If the EN pin is lower than 0.5V, the regulator will be in a low power state and VIN is less than 10μa. EN must be increased to more than 3V to operate normally.

[0030] The RAMP pin of the switch control chip U2 is connected to one end of the capacitor C15, and the other end of the capacitor C15 is grounded. The slope of the current mode of the simulated current ramp is controlled according to the size of the capacitor C15, thereby controlling the operation of the switch control chip U2. The simulated current mode control can reduce the noise sensitivity of the pulse width modulation circuit so that high input voltages can be reliably controlled, and the duty cycle required in the application is extremely small.

[0031] Pin SS of the switch control chip U2 is connected to the soft start circuit. An external capacitor and an internal 10μA current source set the rise time of the error amplifier reference. The SS pin remains low when VCC is below the VCC undervoltage threshold (less than 3.7V), the UVLO pin is low (less than 1.23V), EN is low (less than 0.5V), or the thermal shutdown is activated. The soft start circuit includes capacitor C16, one end of which is connected to pin SS of the switch control chip U2, and the other end of capacitor C16 is grounded.

[0032] Pin FB of the switch control chip U2 is connected to one end of the resistor R16, and the other end of the resistor R16 is grounded. Pin FB of the switch control chip U2 is connected to the inverting input of the internal error amplifier, and a feedback signal is input to control the transition of the boost mode or buck mode. Pin COMP of the switch control chip U2 is connected to the loop compensation circuit. The loop compensation circuit includes capacitor C41 and capacitor C42. Pin COMP of the switch control chip U2 is connected to one end of the resistor R9 and capacitor C42 respectively, the other end of the resistor R9 is connected to one end of the capacitor C41, and the other end of the capacitor C41 and the other end of the capacitor C42 are connected to pin FB of the switch control chip U2. Capacitor C42 introduces an additional pole to eliminate high-frequency switching noise. If the crossover frequency is much lower than the right half plane zero frequency, the error amplifier zero offsets the modulator pole, leaving a single attitude response at the crossover frequency of the loop gain. The single-pole response at the crossover frequency produces a very stable loop with a 90-degree phase margin. The error amplifier zero should be chosen at a frequency close to the modulator pole and well below the target crossover frequency. This limits the product of resistor R9 and capacitor C41 for the required compensation network zero. Increasing resistor R9 while proportionally reducing capacitor C41 increases the error amplifier gain. Conversely, decreasing resistor R9 while proportionally increasing capacitor C41 decreases the error amplifier gain. The total loop gain can be predicted as the sum of the modulator gain and the error amplifier gain in dB. If a network analyzer is available, the modulator gain can be measured and the error amplifier gain configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed according to the guidelines given. Step load transient testing can be performed to verify acceptable performance. The step load goal is to achieve minimum overshoot with a damped response.

[0033] The pin VOUT of the switch control chip U2 is connected to the regulated output voltage monitoring circuit. The pin VOUT of the switch control chip U2 is respectively connected to one end of the resistor R29 and one end of the capacitor C24, the other end of the resistor E29 is connected to one end of the resistor R28, and the other end of the resistor R28 and the other end of the capacitor C24 are connected to the pin FB of the switch control chip U2.

[0034] The drain of the field effect tube Q3 is connected to the power input terminal through the overvoltage protection circuit. The overvoltage protection circuit mainly includes a voltage stabilizing diode ZD1, a transistor Q1 and a field effect tube T1. The power input terminal is connected to the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the source of the field effect tube T1 and one end of the resistor R10 respectively, the other end of the resistor R10 is connected to the resistor R11 and the negative electrode of the voltage-stabilizing diode ZD1 respectively, the other end of the resistor R11 is connected to the base of the transistor Q1, the positive electrode of the voltage-stabilizing diode ZD1 is connected to one end of the resistor R12 and one end of the capacitor C2 respectively, the other end of the resistor R12 is connected to the collector of the transistor Q1 and the gate of the field effect tube T1 respectively, the other end of the capacitor C2 is connected to the drain of the field effect tube T1, the emitter of the transistor Q1 is connected to the source of the field effect tube T1, the resistor R13 is connected between the drain of the field effect tube T1 and the base of the transistor Q1, and the drain of the field effect tube T1 is connected to the drain of the field effect tube Q3. When the input voltage is normal, the voltage-stabilizing diode ZD1 is not broken down, the transistor Q1 is in a cut-off state, and the power supply is allowed to work normally. Once the input voltage exceeds the set value, the Zener diode ZD1 is broken down, the transistor Q1 is turned on, and then the field effect transistor T1 is controlled to be turned off, cutting off the power output, thereby achieving overvoltage protection.

[0035] The above embodiments only express several implementation methods of the utility model, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model.

Claims

1. A low ripple high current buck-boost device, comprising a housing, characterized in that: A buck-boost circuit is provided in the shell, and the buck-boost circuit includes a switching power supply chip, and the switching power supply chip is respectively connected to the high-voltage side buck MOSFET circuit and the low-voltage side boost MOSFET circuit, and the buck-boost circuit is connected to the power input terminal through an overvoltage protection circuit.

2. The low ripple high current buck-boost device according to claim 1, characterized in that: The low-voltage side boost MOSFET circuit includes a field effect transistor Q2, and the high-voltage side buck MOSFET circuit includes a field effect transistor Q3. The magnitude of the input current is detected to control the opening and closing of the field effect transistors Q2 and Q3 to achieve the transition between the boost mode and the buck mode.

3. The low ripple high current buck-boost device according to claim 2, characterized in that: The overvoltage protection circuit includes a field effect transistor T1, the source of the field effect transistor T1 is connected to the power input end, the source of the field effect transistor T1 is connected to the base and emitter of the transistor Q1, the collector of the transistor Q1 is connected to the gate of the field effect transistor T1, the base of the transistor Q1 is connected to the cathode of the voltage stabilizing diode ZD1, and the collector of the transistor Q1 is connected to the anode of the voltage stabilizing diode ZD1.

4. The low ripple high current buck-boost device according to claim 3, characterized in that: The switching power supply chip is connected to a control circuit, the control circuit includes a capacitor C15, and the control circuit controls the switching power supply chip through a current mode simulating a current ramp.

5. The low ripple high current buck-boost device according to claim 4, characterized in that: The switching power supply chip is connected to an oscillating circuit, and the oscillating circuit includes a resistor R4.

6. The low ripple high current buck-boost device according to claim 5, characterized in that: The switching power supply chip is connected to a loop compensation circuit, and the loop compensation circuit includes a capacitor C41 and a capacitor C42.

7. The low ripple high current buck-boost device according to claim 6, characterized in that: The switch power supply chip is connected to the soft start circuit.

8. A low ripple high current buck-boost device according to claim 1 or 2 or 3 or 4 or 5, characterized in that: The switching power supply chip is connected to the exposed chip connection pad.

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