CMOS (complementary metal oxide semiconductor) ultra-wide-band ultra-high-linearity power amplifier circuit

Abstract

The utility model discloses a CMOS ultra-wideband ultra-high linearity power amplifier circuit, which comprises a first stage PA and a second stage PA, the first stage PA and the second stage PA form a cascade structure, the upstream of the first stage PA and the upstream of the second stage PA are respectively provided with a self-adaptive bias voltage generation module, and the upstream of the first stage PA and the upstream of the second stage PA are respectively provided with a self-adaptive bias voltage generation module. The self-adaptive bias voltage generation module comprises a first MOS switch and a second MOS switch, a source electrode of the first MOS switch and a source electrode of the second MOS switch are both coupled with a power supply VDD, a grid electrode of the first MOS switch is coupled with a grid electrode of the second MOS switch through a first resistor and a second resistor, and a grid electrode of the first MOS switch is coupled with a grid electrode of the second MOS switch through a second resistor. And a compensation capacitor is arranged between the drain electrode of the first MOS switch and the drain electrode of the second MOS switch. By means of the compensation capacitor CX between the drain electrode of the first MOS switch and the drain electrode of the second MOS switch, effect adjustment of envelope detection gain along with frequency change can be easily achieved, and therefore bias voltage compensation of a wider band is achieved.

Description

Technical Field

[0001] The utility model relates to an amplifier circuit, more specifically, to a CMOS ultra-wideband ultra-high linearity power amplifier circuit. Background Art

[0002] In order to achieve greater communication capacity, the RF front-end device itself must be able to carry a wider signal bandwidth. On the other hand, under the premise of limited RF bandwidth, in order to further improve the communication capacity, it is necessary to use high-order modulation technology, which puts forward higher linearity requirements for the RF front-end device itself. Therefore, how to realize ultra-wideband and ultra-high linearity power amplifiers based on CMOS technology has been one of the hot research topics in recent years.

[0003] There are two main reasons for the loss of linearity of power amplifiers (PAs): AM-AM distortion and AM-PM distortion. Existing literature shows that the two distortions can be suppressed through better compensation circuit design. However, most existing solutions are for narrowband suppression. In the case of ultra-wideband, the AM-AM and AM-PM distortion characteristics of the amplifier vary greatly at different frequencies, which makes the previous linearity optimization methods inapplicable, and there are almost no linearity improvement methods for ultra-wideband PAs.

[0004] Chinese invention patent document CN112543005B discloses a compensation circuit for phase modulation of amplitude modulation, a radio frequency power amplifier and a device, and a compensation circuit for phase modulation of amplitude modulation of a radio frequency power amplifier, characterized in that the compensation circuit includes a detection circuit, a reconfigurable current-controlled voltage source circuit and a phase shift circuit, wherein the detection circuit is used to detect the power of an input signal and output a control current according to the power of the input signal when the power of the input signal is greater than a preset power threshold; the reconfigurable current-controlled voltage source circuit is used to generate a bias voltage according to the control current; and the phase shift circuit is used to amplitude modulate the radio frequency power amplifier according to the bias voltage. Compensate for phase modulation AM-PM distortion; wherein the reconfigurable current-controlled voltage source circuit includes a first transistor group and a second transistor group, and the first transistor group and the second transistor group both include a plurality of switch transistors; the reconfigurable current-controlled voltage source circuit is also used to control the bias voltage and the control current to be an increasing function relationship when the first transistor group is turned on according to the second control voltage and the second transistor group is turned off according to the third control voltage; or, when the first transistor group is turned off according to the second control voltage and the second transistor group is turned on according to the third control voltage, the bias voltage and the control current are controlled to be a decreasing function relationship. Obviously, the patent can achieve the purpose of the power of the input signal being greater than the preset power threshold through the cooperation of the detection circuit, the reconfigurable current-controlled voltage source circuit and the phase shift circuit, but this structure cannot solve the existing problem of impaired linearity. Utility Model Content

[0005] Based on this, it is necessary to provide a CMOS ultra-wideband ultra-high linearity power amplifier circuit for the above technical problems. The CMOS ultra-wideband ultra-high linearity power amplifier circuit includes a first-stage PA and a second-stage PA. The first-stage PA and the second-stage PA form a cascade structure. The upstream of the first-stage PA and the second-stage PA are both provided with an adaptive bias voltage generation module. The adaptive bias voltage generation module includes a first MOS switch and a second MOS switch. The source of the first MOS switch and the source of the second MOS switch are both coupled to the power supply VDD. The gate of the first MOS switch is coupled to the gate of the second MOS switch via a first resistor and a second resistor. A compensation capacitor is provided between the drain of the first MOS switch and the drain of the second MOS switch. The gate of the first MOS switch is coupled to the same input terminal of the first-stage PA or the second-stage PA, and the gate of the second MOS switch is coupled to the inverting input terminal of the first-stage PA or the second-stage PA. By using the compensation capacitor CX between the drain of the first MOS switch and the drain of the second MOS switch, the effect adjustment of the envelope detection gain changing with the frequency can be easily realized, thereby realizing a wider-band bias voltage compensation. The compensation capacitor CX can significantly enhance the high-frequency compensation strength and realize the ultra-wideband linearity compensation function.

[0006] In order to solve the above technical problems, the utility model adopts the following technical solutions:

[0007] A CMOS ultra-wideband ultra-high linearity power amplifier circuit, characterized in that the CMOS ultra-wideband ultra-high linearity power amplifier circuit comprises a first-stage PA and a second-stage PA, the first-stage PA and the second-stage PA form a cascade structure, an adaptive bias voltage generating module is provided upstream of the first-stage PA and the second-stage PA, the adaptive bias voltage generating module comprises a first MOS switch and a second MOS switch, the source of the first MOS switch and the source of the second MOS switch are both coupled to a power supply VDD, the gate of the first MOS switch is coupled to the gate of the second MOS switch via a first resistor and a second resistor, and a compensation capacitor is provided between the drain of the first MOS switch and the drain of the second MOS switch.

[0008] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, two electrodes of the compensation capacitor are grounded.

[0009] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the source of the first MOS switch and the source of the second MOS switch have a common electrode, and the common electrode is coupled to the power supply VDD via a third resistor.

[0010] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the gate of the first MOS switch is coupled to the same input end of the first-stage PA or the second-stage PA, and the gate of the second MOS switch is coupled to the inverting input end of the first-stage PA or the second-stage PA.

[0011] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the first MOS switch and the second MOS switch are in a mirror image structure.

[0012] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the compensation capacitor is a variable capacitor.

[0013] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the compensation capacitor is a solid-state capacitor.

[0014] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the third resistor is a variable resistor.

[0015] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the first resistor and the second resistor are variable resistors.

[0016] As a preferred implementation of the CMOS ultra-wideband ultra-high linearity power amplifier circuit provided by the utility model, the first resistor, the second resistor and the third resistor are all digital potentiometers.

[0017] Compared with the prior art, the utility model has the following beneficial effects:

[0018] The utility model provides a CMOS ultra-wideband ultra-high linearity power amplifier circuit, wherein the gate of the first MOS switch is coupled to the same input terminal of the first-stage PA or the second-stage PA, and the gate of the second MOS switch is coupled to the inverting input terminal of the first-stage PA or the second-stage PA. By using the compensation capacitor CX between the drain of the first MOS switch and the drain of the second MOS switch, the effect adjustment of the envelope detection gain changing with the frequency can be easily realized, thereby realizing a wider-band bias voltage compensation. The compensation capacitor CX can significantly enhance the compensation strength of high frequency and realize the ultra-wideband linearity compensation function.

[0019] In addition, the compensation capacitor CX can be a variable capacitor. The compensation capacitor CX is a solid capacitor. Since the compensation capacitor CX is a variable capacitor, the user can adjust the compensation capacity of the capacitor, which is flexible.

[0020] In addition, the first resistor, the second resistor and the third resistor can all be variable resistors. Since the first resistor, the second resistor and the third resistor are all variable resistors, the user can adjust the resistors to accurately control the compensation capability of the amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the scheme in the utility model, a brief introduction is given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a connection diagram of the CMOS ultra-wideband ultra-high linearity power amplifier circuit of the utility model;

[0023] Figure 2 for Figure 1 The application connection diagram of the CMOS ultra-wideband ultra-high linearity power amplifier circuit;

[0024] Figure 3 for Figure 2 Schematic diagram of the application principle of the CMOS ultra-wideband ultra-high linearity power amplifier circuit;

[0025] The markings in the figure are as follows: 1. First-stage PA; 2. Second-stage PA; 3. Adaptive bias voltage generation module; 4. First MOS switch; 5. Second MOS switch; 7. Second resistor; 9. Third resistor; CX, compensation capacitor; S, common pole. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0027] As described in the background technology, for RF circuits, in order to achieve a larger communication capacity, the RF front-end device itself must be able to carry a wider signal bandwidth. On the other hand, under the premise of limited RF bandwidth, in order to further improve the communication capacity, it is necessary to use high-order modulation technology, and high-order modulation technology puts forward higher linearity requirements for the RF front-end device itself. Therefore, how to realize an ultra-wideband ultra-high linearity power amplifier based on CMOS technology has been one of the hot research topics in recent years. The reasons for the loss of linearity of the power amplifier PA are mainly divided into two reasons: AM-AM distortion and AM-PM distortion. Existing literature shows that the two distortions can be suppressed by better compensation circuit design. However, most of the existing solutions are suppression solutions for narrowband. In the case of ultra-wideband, the AM-AM and AM-PM distortion characteristics of the amplifier have very large differences at different frequencies, which makes the previous linearity optimization method inapplicable, and there is almost no linearity improvement method for ultra-wideband PA.

[0028] In order to solve this technical problem, the utility model provides a CMOS ultra-wideband ultra-high linearity power amplifier circuit, comprising a first stage PA1 and a second stage PA2, wherein the first stage PA1 and the second stage PA2 form a cascade structure, wherein an adaptive bias voltage generating module 3 is provided upstream of the first stage PA1 and the second stage PA2, wherein the adaptive bias voltage generating module 3 comprises a first MOS switch 4 and a second MOS switch 5, wherein the source of the first MOS switch 4 and the source of the second MOS switch 5 are both coupled to a power supply VDD8, wherein the gate of the first MOS switch 4 is coupled to the gate of the second MOS switch 5 via a first resistor 6 and a second resistor 7, and a compensation capacitor CX is provided between the drain of the first MOS switch 4 and the drain of the second MOS switch 5. The first MOS switch 4 and the second MOS switch 5 are in a mirror structure. The two poles of the compensation capacitor CX are grounded.

[0029] Through the above structural design, the gate of the first MOS switch 4 is coupled to the same input terminal of the first stage PA1 or the second stage PA2, and the gate of the second MOS switch 5 is coupled to the inverting input terminal of the first stage PA1 or the second stage PA2. By using the compensation capacitor CX between the drain of the first MOS switch 4 and the drain of the second MOS switch 5, the effect of the envelope detection gain changing with the frequency can be easily adjusted, thereby realizing a wider bandwidth bias voltage compensation. The compensation capacitor CX can significantly enhance the compensation strength of high frequency and realize the ultra-wideband linearity compensation function.

[0030] In order to enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0031] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0033] Example 1

[0034] like Figure 1 , Figure 2 and Figure 3 As shown, the CMOS ultra-wideband ultra-high linearity power amplifier circuit includes a first stage PA1 (PA, i.e., power amplifier) ​​and a second stage PA2, wherein the first stage PA1 and the second stage PA2 form a cascade structure, and an adaptive bias voltage generating module 3 is provided upstream of the first stage PA1 and the second stage PA2, and the adaptive bias voltage generating module 3 includes a first MOS switch 4 and a second MOS switch 5, wherein the source of the first MOS switch 4 and the source of the second MOS switch 5 are both coupled to a power supply VDD8, and the gate of the first MOS switch 4 is coupled to the gate of the second MOS switch 5 via a first resistor 6 and a second resistor 7, and a compensation capacitor CX is provided between the drain of the first MOS switch 4 and the drain of the second MOS switch 5.

[0035] It should be noted that the first MOS switch 4 and the second MOS switch 5 are in a mirror image structure. Both electrodes of the compensation capacitor CX are grounded.

[0036] The source of the first MOS switch 4 and the source of the second MOS switch 5 have a common electrode S, and the common electrode S is coupled to the power source VDD8 via a third resistor 9 .

[0037] The working mode of this embodiment is described below.

[0038] like Figure 2As shown, the gate of the first MOS switch 4 is coupled to the same input terminal of the first stage PA1 or the second stage PA2, and the gate of the second MOS switch 5 is coupled to the inverting input terminal of the first stage PA1 or the second stage PA2. By using the compensation capacitor CX between the drain of the first MOS switch 4 and the drain of the second MOS switch 5, the effect of the envelope detection gain changing with the frequency can be easily adjusted, thereby realizing a wider bandwidth bias voltage compensation. The compensation capacitor CX can significantly enhance the compensation strength of high frequency and realize the ultra-wideband linearity compensation function.

[0039] Example 2

[0040] The CMOS ultra-wideband ultra-high linearity power amplifier circuit provided in Example 1 is further optimized. Specifically, the compensation capacitor CX is a variable capacitor.

[0041] It should be noted that the compensation capacitor CX is a solid capacitor.

[0042] The working mode of this embodiment is described below.

[0043] Since the compensation capacitor CX is a variable capacitor, the user can adjust the compensation capability of the capacitor, which has good flexibility.

[0044] Example 3

[0045] The CMOS ultra-wideband ultra-high linearity power amplifier circuit provided in Embodiment 1 or 2 is further optimized. Specifically, the third resistor 9 is a variable resistor.

[0046] In addition, the first resistor 6 and the second resistor 7 are variable resistors.

[0047] The first resistor 6 , the second resistor 7 and the third resistor 9 are all digital potentiometers.

[0048] The working mode of this embodiment is described below.

[0049] Since the first resistor 6 , the second resistor 7 and the third resistor 9 are all variable resistors, the user can adjust the resistors to accurately control the compensation capability of the amplifier circuit.

[0050] In addition, the transistor is a field effect transistor or a triode. When these crystals are field effect transistors, they can be N-type transistors (such as metal-oxide-semiconductor field effect transistors (N-Metal-Oxide-Semiconductor, NMOS)), or P-type metal-oxide-semiconductor field effect transistors, complementary metal-oxide-semiconductor field effect transistors, and other circuit structure types.

[0051] The terms "coupling" and "coupling" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0052] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to replace some of the technical features therein with equivalents. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A CMOS ultra-wideband ultra-high linearity power amplifier circuit, characterized in that: The CMOS ultra-wideband ultra-high linearity power amplifier circuit comprises a first-stage PA (1) and a second-stage PA (2), wherein the first-stage PA (1) and the second-stage PA (2) form a cascade structure, wherein an adaptive bias voltage generating module (3) is provided upstream of the first-stage PA (1) and the second-stage PA (2), wherein the adaptive bias voltage generating module (3) comprises a first MOS switch (4) and a second MOS switch (5), wherein the source of the first MOS switch (4) and the source of the second MOS switch (5) are both coupled to a power supply VDD (8), wherein the gate of the first MOS switch (4) is coupled to the gate of the second MOS switch (5) via a first resistor (6) and a second resistor (7), and a compensation capacitor (CX) is provided between the drain of the first MOS switch (4) and the drain of the second MOS switch (5).

2. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 1, characterized in that: Both electrodes of the compensation capacitor (CX) are grounded.

3. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 2, characterized in that: The source of the first MOS switch (4) and the source of the second MOS switch (5) have a common electrode (S), and the common electrode (S) is coupled to the power supply VDD (8) via a third resistor (9).

4. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 1, characterized in that: The first MOS switch (4) and the second MOS switch (5) are in a mirror image structure.

5. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 1, characterized in that: The compensation capacitor (CX) is a variable capacitor.

6. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 1, characterized in that: The compensation capacitor (CX) is a solid-state capacitor.

7. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 3, characterized in that: The third resistor (9) is a variable resistor.

8. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 7, characterized in that: The first resistor (6) and the second resistor (7) are variable resistors.

9. The CMOS ultra-wideband ultra-high linearity power amplifier circuit according to claim 8, characterized in that: The first resistor (6), the second resistor (7) and the third resistor (9) are all digital potentiometers.

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