ESD secondary protection circuit
By adding NMOS tube M0 as secondary protection and resistor R0 to the traditional ESD protection circuit for gate coupling and leakage, the problem of insufficient first-level protection of traditional ESD protection circuit and different interdigit MOS tubes are solved, and more efficient ESD protection and clamping capabilities are achieved.
Patent Information
- Application Number
- CN202421505354.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-06-28
AI Technical Summary
Traditional ESD protection circuits have the problem of insufficient first-level protection, making it difficult to effectively clamp the voltage, resulting in a large current being connected to the internal devices, and the MOS tube in the form of an interdigit is not turned on at the same time when the ESD is discharged, resulting in the failure of the ESD protection capability to increase as expected.
In the traditional ESD protection structure, an NMOS tube M0 is added as a secondary protection, performs a second clamp, and uses gate coupling to use gate coupling when a large current comes, by opening the MOS tube to ensure that each interdigital tube will release current.
Improves ESD protection and clamping capabilities, ensuring that high current does not break down the internal devices, and when ESD occurs, the MOS tube in the form of an interdigit can open the drainage path at the same time, enhancing the ESD protection capabilities.
Smart Images
Figure CN222868910U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical components, in particular to an ESD secondary protection circuit. Background Art
[0002] ESD (electrostatic discharge) refers to electrostatic discharge, which can damage devices and integrated circuit systems. Because the instantaneous voltage of electrostatic discharge is very high, usually several thousand volts, there are two ways for MOS devices to be permanently damaged by electrostatic discharge: ① Generally, when the accumulated charge on the gate causes the electric field strength to be too large, the gate oxide layer is broken down, which will cause the resistance between the gate and the channel to be very low; ② If a large current flows between the source and drain junction, regardless of forward bias or reverse bias, the diode will burn out, causing the source, drain and substrate to short-circuit. Therefore, preventing ESD is a difficult problem in IC design and manufacturing. In order to solve ESD, a discharge path must be provided for the induced charge. General ESD protection places an ESD suppressor or diode in parallel between the PAD and the internal module of the chip to protect the system circuit from electrical overstress. If there is no ESD protection, the large current from the ESD will directly flow into the system circuit and damage the components, but if there is an ESD protection diode, the large current breakdown protection diode provides a low-resistance discharge path, thereby protecting the internal circuit of the chip.
[0003] Traditional ESD protection circuits such as Figure 1 As shown: This circuit uses GGNMOS (GATE-GROUNDED NMOS) as a circuit structure for ESD protection, but such a structure has defects:
[0004] A. Because the structure has only one level of protection, considering the internal resistance of the ESD device and the impedance of the current loop, it may be difficult to clamp the voltage to a safe voltage, resulting in large current being connected to the internal device.
[0005] B. When the MOS tubes in the form of fingers are used for ESD discharge, all the MOS tubes cannot discharge current at the same time, and only two or three of them are turned on.
[0006] Therefore, a circuit is needed that can improve ESD protection and clamping capabilities. Summary of the invention
[0007] The utility model is to solve the problem of ESD protection capability and clamping capability, and provides an ESD secondary protection circuit. In view of defect A of the prior art, an NMOS tube M0 is added to the traditional ESD protection structure as secondary protection, mainly to clamp the primary protection signal for the second time. In view of defect B, a resistor is added to the traditional ESD protection structure, and its purpose is to utilize gate coupling. When a large current comes, it is not through reverse breakdown but through opening the MOS tube to discharge the current. In this way, it can be ensured that each interdigital tube of the MOS tube will discharge the current.
[0008] The utility model provides an ESD secondary protection circuit, comprising a resistor R2 connected between an input end and an output end, a MOS tube M0 having one end connected between the resistor R2 and the output end and the other end grounded, a MOS tube M1 having one end connected between the resistor R2 and the input end and the other end grounded, and a resistor R0 having one end connected to the MOS tube M1 and the other end grounded;
[0009] The gate, source and substrate of the MOS tube M0 are all grounded, and the drain is connected between the resistor R2 and the output end. The MOS tube M1 is in a forked finger form, with the source located on both sides and the drain placed in the middle; the source and substrate of the MOS tube M1 are connected and then grounded, the drain is connected between the resistor R2 and the input end, and the gate is connected to the resistor R0; the resistor R0 is connected to the gate of the MOS tube M1.
[0010] In the ESD secondary protection circuit described in the present invention, as a preferred embodiment, the distance between the contact hole of the MOS tube M0 and the gate is 2 microns.
[0011] The utility model discloses an ESD secondary protection circuit. As a preferred embodiment, both the MOS tube M0 and the MOS tube M1 are NMOS tubes; the MOS tube M1 is a primary ESD protection, and the MOS tube M0 is a secondary ESD protection.
[0012] In the ESD secondary protection circuit described in the present invention, as a preferred embodiment, in the layout, the distance between the MOS tube M1 and the PAD is smaller than the distance between the MOS tube M0 and the PAD.
[0013] The utility model discloses an ESD secondary protection circuit, as a preferred mode, in the layout, the substrate of the MOS tube M0 is annular, the MOS tube M0 is in the form of a fork finger, the source is placed on both sides, and the drain is placed in the middle.
[0014] In the ESD secondary protection circuit described in the present invention, as a preferred embodiment, the MOS tube M1 is adjacent to the MOS tube M0 on the layout.
[0015] The utility model discloses an ESD secondary protection circuit, as a preferred mode, in the layout, the source and substrate of the MOS tube M1 are horizontally connected to GND through metal wires, and the metal wires are chamfered.
[0016] In the ESD secondary protection circuit described in the present invention, as a preferred embodiment, in the layout, the drain of the MOS tube M1 is connected to the PAD through a longitudinal metal wire.
[0017] The ESD secondary protection circuit described in the present invention is preferably configured such that, on the layout, the resistor R0 is located outside the isolated power ring of the MOS tube M1 and inside the isolated ground ring; and the resistor R2 is located outside the isolated ground ring.
[0018] The utility model describes an ESD secondary protection circuit, as a preferred mode, the metal width on the drain of the MOS tube M0 is 2 microns and is filled with through holes, and the drain is covered with array through holes with a width of 0.45 microns*0.45 microns and a number of 1*2.
[0019] The utility model provides a layout structure of ESD secondary protection. In view of defect A of the prior art, an NMOS tube M0 is added to the traditional ESD protection structure as secondary protection, mainly for the second clamping of the primary protection signal. In view of defect B, a resistor is added to the traditional ESD protection structure, the purpose of which is to utilize gate coupling. When a large current comes, the current is discharged by opening the MOS tube instead of by reverse breakdown. In this way, it can be ensured that each interdigital tube of the MOS tube will discharge the current.
[0020] The utility model has the following advantages:
[0021] (1) The utility model adds an NMOS tube to the ESD primary protection structure and places it inside or on the side of the module as a secondary protection to prevent the primary protection from failing to clamp the voltage in a safe area and breaking through the internal MOS tube gate.
[0022] (2) The utility model adds a resistor to the first-level ESD protection, and the MOS tube discharges through gate coupling to prevent multiple fingers of the MOS tube from being unable to be turned on at the same time to discharge a large current.
[0023] (3) The utility model not only ensures that the ESD protection can clamp the voltage to a safe value that will not break down the gate oxide layer of the MOS tube, but also can meet the requirement that the interdigitated MOS simultaneously opens the discharge path when ESD occurs. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 The ESD protection circuit diagram in the background technology;
[0025] Figure 2A circuit diagram of an ESD secondary protection circuit;
[0026] Figure 3 It is a cross-sectional view of an ESD protection circuit in the background technology;
[0027] Figure 4 This is a MOS tube MO layout for an ESD secondary protection circuit;
[0028] Figure 5 This is a layout of an ESD secondary protection circuit. DETAILED DESCRIPTION
[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.
[0030] Example 1
[0031] like Figure 2 , 4 , 5, a secondary ESD protection circuit, in the background technology Figure 1 A resistor R0 and an NMOS tube M0 are added to the structure to improve the protection capability of the ESD protection tube and prevent the first-level ESD clamp from failing to clamp the voltage in a safe area, and add secondary protection for secondary clamping.
[0032] Analyze the traditional ESD protection circuit, such as Figure 1 As shown: connect the gate, source, and substrate together, and connect the drain to the IO terminal to withstand the ESD surge voltage. Figure 3This is the ESD protection profile of GGNMOS. The drain of NMOS, Psub substrate, and source are the collector, base, and emitter of the parasitic NPN respectively. Because the gate is short-circuited with the substrate, the gate of NMOS is always in the off state. When a large voltage comes in at the IO end, the reverse-biased PN junction formed by the drain and the substrate is broken down, and a large amount of current flows into the substrate in an instant. Because the substrate has parasitic resistance, a voltage drop is generated on the substrate, causing the parasitic PN emitter junction between the source and the substrate to be forward biased, while the collector junction between the drain and the substrate is reverse biased, and the parasitic NPN is forward-biased, forming a discharge path to discharge the large ESD current from the IO end into GND. Because ESD has to be made into a forked-finger form, but during ESD discharge, multiple MOS tubes are not necessarily turned on at the same time. Generally, they are turned on by reverse breakdown. Usually two or three will be turned on first. This is because the layout cannot make the relative position and pulling direction of each forked-finger MOS tube exactly the same. Once these 2-3 forked-finger tubes are turned on, the ESD current will flow to these 2-3 tubes, while the other forked-finger tubes remain in the closed state. Therefore, the ESD protection capability is actually only the protection capability of these 2-3 forked-finger tubes, not the protection capability of 10 forked-finger tubes. This leads to the failure of the ESD protection capability to increase as expected.
[0033] exist Figure 1 Add a resistor R0 to the structure, such as Figure 2 As shown: one end of the resistor is connected to GND, and the other end is connected to the gate of M1. Due to the existence of parasitic capacitance between the gate and the drain, when the ESD transient positive voltage is applied to PAD, Figure 2 A transient positive voltage will be coupled to the M1 gate, and at this time M1 will open the channel, which is equivalent to opening the drains of all the interdigital tubes of the MOS tube, and discharging the current generated by the transient positive voltage into the ground. In this way, it can be ensured that each interdigital tube is opened at the same time to discharge the current, making each interdigital tube discharge the ESD current more uniform.
[0034] Traditional ESD protection circuits, such as Figure 1 As shown: Considering the internal resistance of the ESD device and the impedance of the current loop, this structure may not be able to clamp the voltage to a safe area, causing a large current to enter the interior and destroy the device.
[0035] exist Figure 1 Add a MOS tube M0 to the structure, such as Figure 2 As shown: the gate and source of the MOS tube are connected to GND, the drain is connected to R2 and outputs the signal. The main function of M0 is to clamp the signal to a safe voltage by using M0 as the secondary ESD protection tube structure when the structure of the ESD protection tube used by M1 cannot clamp the signal to a safe voltage, so as to ensure that the large current will not break down the internal devices.
[0036] According to the analysis of the above circuit, the layout structure design is divided into two parts. The first part is as follows: Figure 4 For Figure 1 The purpose of adding MOS tube layout design to the structure is to perform secondary clamping of the signal. The MOS tube for ESD secondary protection is placed inside or on the side of the module. The NMOS substrate is made into a ring to increase substrate contact. The MOS tube is made into a forked finger form, and the source is placed on both sides. The drain is placed in the middle to reduce the external influence on the drain. The distance from the CT hole to the gate on both sides is increased to 2u, the withstand voltage of the drain is increased, the metal coverage on the drain is increased, and as many through holes as possible are made to cover the drain to meet the current discharge. Place the ESD secondary protection next to the protected device and reduce the connection resistance as much as possible. The second part is as follows Figure 5 exist Figure 1 The layout design with resistors added to the structure aims to improve the ESD protection capability. In this layout design, the first-level ESD protection should be as close to the pad as possible. The source and substrate of M1 are connected to GND horizontally through wide metal 3. In order to prevent the tip of the metal from discharging, the wide metal line should be chamfered, and the drain is directly connected to the pad by the vertical wide metal 2. The resistor R0 used to improve the ESD protection capability is placed outside the isolated power ring of the ESD protection tube and inside the isolated ground ring, while the current limiting resistor R2 is placed outside the isolated ground ring.
[0037] The specific embodiment of this invention is as follows: Figure 2 As shown, a resistor R0 is added compared to the traditional ESD protection circuit, L = 58u, W = 1u, and the resistance is about one thousand ohms, which is used to open the MOS tube M1. R2 is a resistor with L = 35u, W = 1u. The main function of this resistor is to limit the current of the clamped signal. M1 is a first-level ESD protection tube. The type used is a protection tube specially used for ESD protection. The size is fw = 50u, nf = 5. M0 is a MOS tube for ESD secondary protection. This protection is generally placed inside the module. The type used is a low-voltage 5V device with a size of fw = 20u, nf = 2. The function of this tube is that when the first-level ESD protection cannot clamp the voltage in a safe area, the tube can perform secondary clamping.
[0038] The layout structure is as follows Figure 4 , Figure 5 As shown: By widening the metal on the drain to 2u and filling it with through holes, the through hole width is 0.45*0.45, and the number of 1*2 arrays are spread over the drain to ensure that the discharge path of large current is large enough. Place the secondary protection on the edge of the module to be protected to reduce the connection resistance between the input receiving end and the secondary protection. Increase the spacing from the drain CT hole to the gate to 2u, thereby increasing the withstand voltage value of the MOS tube and increasing the ESD protection capability. The wide metal routing cuts the 90° corners to prevent tip discharge.
[0039] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.
Claims
1. An ESD secondary protection circuit, characterized in that: It includes a resistor R2 connected between the input end and the output end, a MOS tube M0 having one end connected between the resistor R2 and the output end and the other end grounded, a MOS tube M1 having one end connected between the resistor R2 and the input end and the other end grounded, and a resistor R0 having one end connected to the MOS tube M1 and the other end grounded; The gate, source and substrate of the MOS tube M0 are all grounded, and the drain is connected between the resistor R2 and the output end. The MOS tube M1 is in a forked finger form, with the source located on both sides and the drain placed in the middle; the source and substrate of the MOS tube M1 are connected and then grounded, the drain is connected between the resistor R2 and the input end, and the gate is connected to the resistor R0; the resistor R0 is connected to the gate of the MOS tube M1.
2. The ESD secondary protection circuit according to claim 1, characterized in that: Both the MOS tube M0 and the MOS tube M1 are NMOS tubes; the MOS tube M1 is a primary ESD protection, and the MOS tube M0 is a secondary ESD protection.
3. The ESD secondary protection circuit according to claim 1, characterized in that: The distance between the contact hole and the gate of the MOS tube M0 is 2 microns.
4. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the distance between the MOS tube M1 and the PAD is smaller than the distance between the MOS tube M0 and the PAD.
5. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the substrate of the MOS tube M0 is ring-shaped, the MOS tube M0 is in the form of a fork finger, the source is placed on both sides, and the drain is located in the middle.
6. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the MOS tube M1 is adjacent to the MOS tube M0.
7. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the source and substrate of the MOS tube M1 are laterally connected to GND through metal wires, and the metal wires are chamfered.
8. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the drain of the MOS tube M1 is connected to the PAD through a vertical metal wire.
9. The ESD secondary protection circuit according to claim 1, characterized in that: On the layout, the resistor R0 is located outside the isolated power ring of the MOS tube M1 and inside the isolated ground ring; the resistor R2 is located outside the isolated ground ring.
10. The ESD secondary protection circuit according to claim 1, characterized in that: The metal width on the drain of the MOS tube M0 is 2 micrometers and is fully perforated with through holes, and the drain is fully covered with array through holes with a width of 0.45 micrometers*0.45 micrometers and a number of 1*2.