Wiring structure of differential pair layout
By using the wiring structure of differential pair MOS tubes and virtual tubes in the differential pair layout, the problem of insufficient accuracy and matching performance is solved, and a differential pair layout wiring scheme with high precision and high matching performance is realized, and the layout height is reduced.
Patent Information
- Application Number
- CN202421525980.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-01
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-07-01
AI Technical Summary
The existing differential layout wiring scheme has problems with insufficient accuracy and matching performance, and the layout height is high, which affects the conductive performance.
The wiring structure of differential pair MOS tubes and virtual tubes is adopted. By placing the metal wires of the source and drain in the middle, the gate is placed on both upper and lower sides, and using M3 outlets to pass through the substrate ring, constantly opening the substrate to improve accuracy and matching performance and reduce the layout height.
It improves the accuracy and matching performance of the differential pair, reduces the layout height, enhances the conductivity, and meets the circuit requirements with high accuracy requirements.
Smart Images
Figure CN222869306U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical components, in particular to a wiring structure of a differential pair layout. Background Art
[0002] The differential amplifier circuit (also called differential amplifier circuit, differential pair, differential pair) can solve the noise problem and is an extremely widely used circuit in analog integrated circuits. Compared with ordinary amplifier circuits, it has many advantages: First, it distinguishes the differential mode and common mode signals. Ideally, it only amplifies the differential signal and completely suppresses the common mode signal. Second, the highly symmetrical structure of the differential pair makes it have strong anti-interference ability, and the differential output signal is almost unchanged. Third, the differential pair has the advantages of high linearity and large output swing, and has a wide range of applications.
[0003] The differential pair circuit needs to properly balance or filter the differential signal, otherwise there will be electromagnetic interference problems; it requires good symmetry, otherwise it will affect the noise suppression effect. The differential pair has high requirements for the working environment. In order to ensure symmetry, many scholars have proposed many wiring schemes. Some schemes have some problems:
[0004] A. Figure 1 As shown, since one end is shared, in order to ensure matching performance, the virtual tube can only be connected to the drain. This wiring method is only suitable for common source or common drain connection with a common end.
[0005] B. Figure 2 As shown in FIG. 1 , the substrate of this differential pair structure is disconnected for wiring, which may affect the conductivity. Since the source and drain of the transistor are wired from the top and bottom, the overall layout height is relatively high.
[0006] Therefore, a high-precision, high-matching performance differential pair layout routing solution is needed. Summary of the invention
[0007] The utility model aims to solve the accuracy and matching problems of differential pair layout wiring, and provides a wiring structure of a differential pair layout. The transistor is split to improve the accuracy and matching performance of the differential pair; the M3 output line passes through the substrate ring without disconnecting the substrate; the metal wires of the source and the drain are placed in the middle, and the gate is placed on the upper and lower sides to reduce the layout height.
[0008] The utility model provides a wiring structure of a differential pair layout, comprising a substrate ring, a differential pair MOS tube with common centroid matching, and a virtual tube D connected inside the substrate ring and located on both sides of the differential pair MOS tube;
[0009] The differential pair MOS tube includes a PMOS tube PM8 and a PMOS tube PM9, PM8 includes four transistors A arranged up and down and connected in sequence from left to right, PM9 includes four transistors B arranged up and down and connected in sequence from left to right, the upper part of the differential pair MOS tube is an ABBA interdigitated structure, and the lower part is a BAAB interdigitated structure, the source and drain of the differential pair MOS tube are connected from the middle, and the gate is connected from the top and bottom, the number of virtual tubes D is 4 and they are respectively connected to the substrate ring, and the substrate ring wraps the routing of the differential pair MOS tube and the virtual tube D inside.
[0010] The wiring structure of a differential pair layout described in the present invention is, as a preferred embodiment, that the PM8 source output terminal SA, the PM8 drain output terminal DA, the PM9 source output terminal SB and the PM9 drain output terminal DB are all separately provided and not shared.
[0011] The wiring structure of a differential pair layout described in the present invention is, as a preferred method, a PM9 drain output terminal DB, a PM8 source output terminal SA, a PM8 drain output terminal DA and a PM9 source output terminal SB are arranged in sequence from left to right on the right side of the substrate ring; the PM9 drain output terminal DB, the PM8 source output terminal SA, the PM8 drain output terminal DA and the PM9 source output terminal SB all pass through the substrate ring through the third layer of metal wiring.
[0012] The wiring structure of a differential pair layout described in the present invention is, as a preferred method, that the source output terminal SA of PM8 is connected to the lower part of the source of the two transistors A on the upper side and the upper part of the source of the two transistors A on the lower side, and the drain output terminal DA of PM8 is connected to the lower part of the drain of the two transistors A on the upper side and the upper part of the drain of the two transistors A on the lower side.
[0013] The wiring structure of a differential pair layout described in the present invention is, as a preferred method, that the PM9 drain output terminal DB is connected to the lower part of the drain of the two upper transistors B and the upper part of the drain of the two lower transistors B, and the PM9 source output terminal SB is connected to the lower part of the source of the two upper transistors B and the upper part of the source of the two lower transistors B.
[0014] The wiring structure of a differential pair layout described in the present invention is, as a preferred embodiment, that the PM8 source output terminal GA and the PM9 source output terminal GB are both separately provided and not shared.
[0015] The wiring structure of a differential pair layout described in the present invention is preferably configured such that a PM8 gate output terminal GA and a PM9 gate output terminal GB are sequentially arranged on the left side of the substrate ring from left to right.
[0016] In the wiring structure of a differential pair layout described in the present invention, as a preferred embodiment, the gate output terminal GA of PM8 is respectively connected to the upper gate portions of the two transistors A on the upper side and the lower gate portions of the two transistors A on the lower side.
[0017] In the wiring structure of a differential pair layout described in the present invention, as a preferred embodiment, the gate output terminal GB of PM9 is respectively connected to the upper gate portions of the two transistors B on the upper side and the lower gate portions of the two transistors B on the lower side.
[0018] The wiring structure of a differential pair layout described in the present invention is, as a preferred method, four virtual tubes D of the same size and symmetrically arranged on the left and right sides of the inside of the substrate ring, the two virtual tubes D on the upper side are connected to the upper side of the substrate ring respectively, and the two virtual tubes D on the lower side are connected to the lower side of the substrate ring respectively.
[0019] The MOS tube of the utility model adopts common centroid matching, but keeps the minimum distance between each other and does not share ports; the source and drain are connected in the middle, and the gate is connected above and below to reduce the layout height; the dummy tube is connected with the substrate in a ring to ensure a four-terminal short-circuit connection.
[0020] The utility model has the following advantages:
[0021] (1) Considering the stability of signal transmission, the present invention places the differential pair of tubes separately without sharing any ports. The wiring adopts the scheme of upper and lower gate wires and middle source and drain wires. This has a lower connection height than the prior art.
[0022] (2) In order to ensure the consistency of the environment around PM8 and PM9, common centroid matching is adopted. In the existing integrated process, there is a thermal gradient or a linear gradient in the process. The thermal gradient is generated by a hot spot on the chip, which will cause the electrical characteristics of the devices around it to change. Devices far from the hot spot are less affected than those close to the hot spot. The common centroid technology makes the distribution of the thermal gradient effect between devices more balanced.
[0023] (3) Added a dummy tube of the same size. When the device starts to corrode after working for a period of time, the environment of the device in the middle must be different from that of the two sides. The devices on the two sides will be corroded more than the devices in the middle, which will also cause the mismatch between PM8 and PM9. Added a dummy tube to protect the matching tube. At the same time, the dummy tube is not connected to any other device on the circuit line to maintain the function of the original circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is the background technology 1 layout;
[0025] Figure 2 It is the background technology 2 layout;
[0026] Figure 3 It is a wiring structure layout of a differential pair layout.
[0027] Reference numerals:
[0028] 1. Substrate; 2. Differential pair MOS tube. DETAILED DESCRIPTION
[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.
[0030] Example 1
[0031] like Figure 1 As shown, a wiring structure of a differential pair layout includes a substrate ring 1, a differential pair MOS transistor 2 with common centroid matching, and a virtual transistor D connected inside the substrate ring 1 and located on both sides of the differential pair MOS transistor 2;
[0032] The differential pair MOS tube 2 includes a PMOS tube PM8 and a PMOS tube PM9, PM8 includes four transistors A arranged up and down and connected sequentially from left to right, PM9 includes four transistors B arranged up and down and connected sequentially from left to right, the upper part of the differential pair MOS tube 2 is an ABBA interdigital structure, and the lower part is a BAAB interdigital structure, the source and drain of the differential pair MOS tube 2 are connected from the middle, and the gate is connected from the top and bottom, the number of virtual tubes D is 4 and they are respectively connected to the substrate ring 1, and the substrate ring 1 wraps the wiring of the differential pair MOS tube 2 and the virtual tube D inside;
[0033] PM8 source output terminal SA, PM8 drain output terminal DA, PM9 source output terminal SB and PM9 drain output terminal DB are all set separately and not shared; PM9 drain output terminal DB, PM8 source output terminal SA, PM8 drain output terminal DA and PM9 source output terminal SB are set in sequence from left to right on the right side of substrate ring 1; PM9 drain output terminal DB, PM8 source output terminal SA, PM8 drain output terminal DA and PM9 source output terminal SB are all connected through the substrate ring 1 through the third layer of metal wiring. , without disconnecting the substrate; the source output terminal SA of PM8 is connected to the lower part of the source of the two transistors A on the upper side and the upper part of the source of the two transistors A on the lower side, and the drain output terminal DA of PM8 is connected to the lower part of the drain of the two transistors A on the upper side and the upper part of the drain of the two transistors A on the lower side; the drain output terminal DB of PM9 is connected to the lower part of the drain of the two transistors B on the upper side and the upper part of the drain of the two transistors B on the lower side, and the source output terminal SB of PM9 is connected to the lower part of the source of the two transistors B on the upper side and the upper part of the source of the two transistors B on the lower side;
[0034] The PM8 source output terminal GA and the PM9 source output terminal GB are both separately provided and not shared; the PM8 gate output terminal GA and the PM9 gate output terminal GB are sequentially provided on the left side of the substrate ring 1 from left to right; the PM8 gate output terminal GA is respectively connected to the upper gates of the two transistors A on the upper side and the lower gates of the two transistors A on the lower side; the PM9 gate output terminal GB is respectively connected to the upper gates of the two transistors B on the upper side and the lower gates of the two transistors B on the lower side;
[0035] The four virtual tubes D are of the same size and are symmetrically arranged on the left and right sides of the substrate ring 1. The two virtual tubes D on the upper side are connected to the upper side of the substrate ring 1 respectively, and the two virtual tubes D on the lower side are connected to the lower side of the substrate ring 1 respectively.
[0036] The purpose of this utility model is to design a high-precision differential pair wiring solution, referring to Figure 3 This solution splits the transistors to improve the accuracy and matching performance of the differential pair; the M3 outgoing line passes through the substrate ring without breaking the substrate. The metal wires of the source and drain are placed in the middle, and the gate is placed on the upper and lower sides. Figure 2 Compared with the layout, the height is reduced.
[0037] The utility model provides a high-precision, high-matching performance differential pair layout wiring solution, referring to Figure 3 The overall accuracy and matching performance are better, which can meet the circuit requirements with high precision. The MOS tubes are matched with the same centroid, but the minimum distance between each other is maintained and the ports are not shared. The source and drain are connected in the middle, and the gate is connected above and below to reduce the layout height. The dummy tube is connected to the substrate ring to ensure a four-terminal short-circuit connection.
[0038] The utility model not only ensures the precision and matching performance of the MOS tube, but also reduces the height of the layout as much as possible, making the structure more compact.
[0039] The utility model provides a high-precision, high-matching performance differential pair layout wiring solution. Figure 3 As shown, the minimum spacing is maintained between the MOS tubes, the substrate wraps the routing inside, and the virtual tube is connected to the substrate separately, so that the overall accuracy and matching performance of the layout are better, which can meet the circuit requirements with higher precision.
[0040] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A wiring structure of a differential pair layout, characterized in that: It comprises a substrate ring (1), a common centroid matched differential pair MOS transistor (2), and a virtual transistor D connected inside the substrate ring (1) and located on both sides of the differential pair MOS transistor (2); The differential pair MOS tube (2) comprises a PMOS tube PM8 and a PMOS tube PM9, PM8 comprises four transistors A arranged in upper and lower parts and connected in sequence from left to right, PM9 comprises four transistors B arranged in upper and lower parts and connected in sequence from left to right, the upper part of the differential pair MOS tube (2) is an ABBA interdigitated structure, and the lower part is a BAAB interdigitated structure, the source and drain of the differential pair MOS tube (2) are connected from the middle, and the gate is connected from the upper and lower parts, the number of virtual tubes D is four and they are respectively connected to the substrate ring (1), and the substrate ring (1) encloses the wiring of the differential pair MOS tube (2) and the virtual tube D inside.
2. The wiring structure of a differential pair layout according to claim 1, characterized in that: The PM8 source output terminal SA, the PM8 drain output terminal DA, the PM9 source output terminal SB and the PM9 drain output terminal DB are all set separately and are not shared.
3. The wiring structure of a differential pair layout according to claim 2, characterized in that: The right side of the substrate ring (1) is provided with a PM9 drain output terminal DB, a PM8 source output terminal SA, a PM8 drain output terminal DA and a PM9 source output terminal SB in sequence from left to right; the PM9 drain output terminal DB, the PM8 source output terminal SA, the PM8 drain output terminal DA and the PM9 source output terminal SB all pass through the substrate ring (1) via a third-layer metal connection line.
4. The wiring structure of a differential pair layout according to claim 2, characterized in that: The source output terminal SA of PM8 is connected to the lower source of the two upper transistors A and the upper source of the two lower transistors A, and the drain output terminal DA of PM8 is connected to the lower drain of the two upper transistors A and the upper drain of the two lower transistors A.
5. The wiring structure of a differential pair layout according to claim 2, characterized in that: The PM9 drain output terminal DB is connected to the lower drains of the two upper transistors B and the upper drains of the two lower transistors B, and the PM9 source output terminal SB is connected to the lower sources of the two upper transistors B and the upper sources of the two lower transistors B.
6. The wiring structure of a differential pair layout according to claim 1, characterized in that: The PM8 source output terminal GA and the PM9 source output terminal GB are both independently set and not shared.
7. The wiring structure of a differential pair layout according to claim 6, characterized in that: The left side of the substrate ring (1) is provided with a PM8 gate output terminal GA and a PM9 gate output terminal GB in sequence from left to right.
8. The wiring structure of a differential pair layout according to claim 6, characterized in that: The gate output terminal GA of PM8 is connected to the upper gate portions of the two transistors A on the upper side and the lower gate portions of the two transistors A on the lower side respectively.
9. The wiring structure of a differential pair layout according to claim 6, characterized in that: The gate output terminal GB of PM9 is connected to the upper gate portions of the two transistors B on the upper side and the lower gate portions of the two transistors B on the lower side respectively.
10. The wiring structure of a differential pair layout according to claim 1, characterized in that: The four virtual tubes D are of the same size and are symmetrically arranged on the left and right sides of the substrate ring (1). The two virtual tubes D on the upper side are connected to the upper side of the substrate ring (1) respectively, and the two virtual tubes D on the lower side are connected to the lower side of the substrate ring (1) respectively.