Annular internal circuit electrostatic protection layout structure with back gate contact

Abstract

The utility model provides an annular internal circuit electrostatic protection layout structure with back gate contact, which comprises a resistor R0 connected with an input end, an NMOS (N-channel Metal Oxide Semiconductor) tube NM0, a PMOS (P-channel Metal Oxide Semiconductor) tube PM0 and a PMOS tube PM1 connected with the PM0, wherein the NMOS tube NM0 and the PMOS tube PM0 are respectively connected with the other end of the resistor R0, and a drain electrode of the NM0, a grid electrode and a drain electrode of the PM0 are connected with the other end of the resistor R0 and then connected with an output end; a grid electrode and a source electrode of the NM0 are connected and then grounded, a source electrode of the PM0 is connected with a drain electrode of the PM1, and a grid electrode and a source electrode of the PM1 are connected with a power supply VDD; pM0, PM1 and NM0 are all square grid electrodes, and PM1 and NM0 are in back gate contact. According to the utility model, the back gate contact is used to prevent minority carriers from entering the substrate, so that the latch-up effect is avoided and the area is reduced; the series-connected polycrystalline silicon current-limiting resistors are used, high voltage generated when electrostatic discharge occurs is converted into small current through the high-resistance resistor, a self-protection function is achieved, and the risk that the current flows to a power source from a device does not exist. Comprising a clamping structure with a self-protection function, the drain electrode is widened, and the high-resistance annular MOS device can be quickly started and can bear instant high voltage.

Description

Technical Field

[0001] The utility model relates to the technical field of electrical components, in particular to a ring-shaped internal circuit electrostatic protection layout structure with back-grid contact. Background Art

[0002] Electrostatic discharge (ESD) is a common form of electrical overstress that causes chip failure. In severe cases, the instantaneous high voltage generated by static electricity can break through the gate dielectric and make the integrated circuit unable to work properly. According to the application scenarios of the chip, the sensitivity of the integrated circuit to ESD can be measured through different test methods, which are specifically divided into: HBM (human body model), MM (machine model), and CDM (charged device model). Except for the pins connected to the substrate and large diffusion areas (such as power devices), general vulnerable pins need to have an ESD protection structure connected to the pad. Generally speaking, the ESD protection structure includes primary protection, secondary protection, and internal circuit protection. Among them, the primary and secondary protection are relatively close to the pins, and the internal circuit protection is generally placed in the internal circuit.

[0003] Generally, internal circuit protection uses a common NMOS (GGNMOS) with the gate and source grounded and a series current limiting resistor. Sometimes a PMOS or another GGNMOS is added to form a CDM clamping structure. Usually, GGNMOS is specially processed to widen the distance between the drain and source contacts to more than 2um, and the polysilicon gate enhances the current limiting.

[0004] However, this electrostatic protection structure has the following disadvantages:

[0005] 1. GGNMOS requires substrate contact to provide potential to the substrate. Ordinary substrate contact cannot provide effective protection for the device, and the overall area is too large after addition.

[0006] 2. If the voltage at the pin is greater than the power supply voltage, there is a risk that current may flow to the power supply.

[0007] 3. The source-gate-drain structure of ordinary MOS has uneven current flow and large drain capacitance. For ESD devices that need to be turned on quickly, the turn-on speed is slightly slow. Summary of the invention

[0008] The utility model aims to solve the problems of too large electrostatic protection structure area, possible current flow to the power supply and slow start-up speed, and provides a ring-shaped internal circuit electrostatic protection layout structure with back gate contact. The back gate contact is used to prevent minority carriers from entering the substrate, avoiding the latch effect while reducing the area; a polysilicon current limiting resistor is used in series, and the high voltage when electrostatic discharge occurs is converted into a small current through a high-resistance resistor, which has a self-protection function and does not have the risk of current flowing from the device to the power supply; including a clamping structure with a self-protection function, the ring-shaped MOS device with a widened drain and high resistance can start quickly and withstand instantaneous high voltage.

[0009] The utility model provides a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, comprising a resistor R0 connected to an input end and a PMOS tube PM1, a PMOS tube PM0, and an NMOS tube NM0 connected to an output side of the resistor R0 from top to bottom in sequence, the resistor R0 is connected to the gate and drain of the PMOS tube PM0, and the drain of the NMOS tube NM0, the source of PM0 and the drain of PM1 are connected, and the drain of PM0 is connected to the output end;

[0010] The gate and source of NM0 are both grounded, and the gate and source of PM1 are both connected to the power supply VDD;

[0011] PM0, PM1 and NM0 are all annular MOS tubes with square gates or circular gates, and the sources of PM1 and NM0 are back-gate contacts.

[0012] In the annular internal circuit electrostatic protection layout structure with back gate contact described in the utility model, as a preferred embodiment, the resistor R0 is a polysilicon current limiting resistor.

[0013] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, as a preferred embodiment, the resistance value of the resistor R0 is 10kΩ and the width is 2um.

[0014] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, in which, as a preferred embodiment, PM0, PM1 and NM0 are all square gates.

[0015] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, as a preferred embodiment, the distances from the PM0, PM1 and NM0 drain contact holes to the polysilicon gate are all greater than 2 um.

[0016] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, as a preferred embodiment, the HRI layer is connected near the drain contact holes of PM0, PM1 and NM0.

[0017] In the annular internal circuit electrostatic protection layout structure with back gate contact described in the utility model, as a preferred embodiment, the drain active regions of PM0, PM1 and NM0 include boron.

[0018] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, as a preferred embodiment, STRAP is connected between PM0, PM1 and NM0.

[0019] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact, as a preferred embodiment, the source and drain of PM0, PM1 and NM0 are all independent active areas.

[0020] The utility model discloses a ring-shaped internal circuit electrostatic protection layout structure with back gate contact. As a preferred embodiment, the channel widths of PM0, PM1 and NM0 are all 10um and the channel lengths are all 500nm.

[0021] The utility model has the following advantages:

[0022] (1) The utility model uses a back gate contact to prevent minority carriers from entering the substrate, thereby avoiding the latch effect and reducing the area;

[0023] (2) The utility model uses a polysilicon current limiting resistor in series to convert the high voltage when electrostatic discharge occurs into a small current through a high-resistance resistor, which has a self-protection function and does not have the risk of current flowing from the device to the power supply;

[0024] (3) The utility model includes a clamping structure with a self-protection function. The ring MOS device with widened drain and high resistance can start quickly and withstand instantaneous high voltage; reduce the drain capacitance and increase the turn-on speed of the device; once the voltage reaches the clamping voltage, when static discharge occurs, the GGNMOS will quickly discharge it to avoid damaging the gate oxide;

[0025] (4) The utility model uses the same low-voltage device as the internal circuit. When placing it, try to place it close to the gate oxide layer to be connected to form a close coupling structure to avoid voltage drop caused by parasitic resistance and inductance, resulting in the actual voltage being above the clamping voltage but not triggered;

[0026] (5) In some cases where the ESD requirements for integrated circuits are not high, the utility model can also serve as secondary protection, but it still needs to follow the principle of close coupling, that is, the ESD protection structure is placed close to the protected device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of an internal circuit electrostatic protection circuit having a ring-shaped internal circuit electrostatic protection layout structure with a back gate contact;

[0028] Figure 2 The invention discloses an internal circuit electrostatic protection layout having a ring-shaped internal circuit electrostatic protection layout structure with a back gate contact. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0030] Example 1

[0031] like Figures 1-2 As shown, a ring-shaped internal circuit electrostatic protection layout structure with back gate contact has a self-protection function;

[0032] Circuit principle Figure 1 As shown. The current flowing in from the pad flows into the circuit after passing through the primary protection and the secondary protection. It first passes through a series current limiting resistor R0. This current limiting resistor R0 is usually a polysilicon resistor with a resistance value of several thousand ohms. Its main function is to prevent large currents from flowing through the structure. In addition, the circuit also includes a clamping device. Usually, the clamping device uses a Zener diode or a MOSFET. In this design, two PMOS (PM0, PM1) and one NMOS (NM0) are used. The main function of PM1 is to protect PM0 from directly connecting its source to the power supply, so as to prevent it from generating the risk of dark current flowing from the device to the power supply. NM1 and PM0 jointly form a CDM clamp to protect the gate oxide layer adjacent to it and prevent excessive voltage from instantly breaking through the gate oxide and causing failure.

[0033] According to the above analysis of the circuit schematic, the layout of this embodiment is as follows Figure 2 As shown, this figure is only used as an example. The input current flows in from the left side, passes through a series polysilicon current limiting resistor R0 and then flows out from the other end below the resistor. Note that the current limiting resistor R0 should not be too thin, otherwise there will be too few contact holes entering the resistor, the metal wire will be too thin, and the current density will not be enough to carry the possible large current. After that, the current is divided into two parts, entering the PMOS area PM0 and PM1 upward, and entering the NMOS area NM0 downward. Note that the PMOS and NMOS here are specially treated. The distance from the drain contact hole to the polysilicon gate is increased to more than 2um to obtain a larger drain resistance, and an HRI layer is added near the contact hole. During production, a small amount of boron will be injected into the drain active area. Through such high-resistance injection, the resistance of the drain area is further increased, and the withstand voltage of the overall structure is improved.

[0034] In addition, the MOSFET of this layout structure also uses a ring MOS structure. Such a structure can reduce the area of ​​the drain region while providing a larger transistor width, aiming to reduce the ratio of the drain capacitance CD to the transistor width W, thereby improving the switching speed of the MOSFET. The ring MOS structure can use a square gate and a circular gate. The utility model uses a MOSFET structure with a square gate. Although the circular gate does not have the sharp corners of the square gate and is not easy to induce avalanche effects, it is not easy to meet the design rules when the HRI layer is added to the circular gate. And the OffGrid problem is prone to occur.

[0035] The inner diameter of the square grid is set as A, and the outer diameter is set as B. The inner diameter of the circular grid is set as C, and the outer diameter is set as D.

[0036] The calculation formulas for the width and length of square and circular grids are as follows:

[0037] Square grid: W≈2(A+B);

[0038] L≈(BA) / 2;

[0039] Circular grid: W = π × (DC) / In (D / C);

[0040] L = (DC) / 2;

[0041] In addition, in order to avoid the latch-up effect and prevent minority carriers from entering the substrate, back gate contacts are added to the source of PM1 and NM0. Note that the source of PM0 is not connected to the power supply, and adding back gate contacts is not allowed. STRAP is added between MOS and MOS as protection to absorb minority carriers and noise.

[0042] It is worth noting that the source and drain of the ring MOS should be independent active areas, because the contact hole in the middle gate part will connect to the active area at the bottom, causing a short circuit.

[0043] When outputting a signal, although the signal entering the clamping structure and the signal output are the same signal line in the schematic diagram, they are still separated when connected. The benefit of this is to ensure that the current flows evenly through the entire device and prevent large current from directly pouring into the gate oxide layer connected to it.

[0044] In the utility model, the resistance value of R0 is selected in the range of about 10kΩ, the width of the polysilicon resistor is selected in the range of 2um, and the dimensions of PM0, PM1 and NM0 are all 10um in channel width and 500nm in channel length.

[0045] The utility model provides an electrostatic protection structure capable of reducing the internal circuit area.

[0046] This electrostatic protection structure has the following advantages:

[0047] 1. Use back gate contact to prevent minority carriers from entering the substrate, avoiding latch-up effect while reducing the area.

[0048] 2. It has a self-protection function and there is no risk of current flowing from the device to the power supply.

[0049] 3. Reduce the drain capacitance and increase the turn-on speed of the device. When static discharge occurs, it can quickly discharge the large current to avoid damaging the gate oxide.

[0050] The utility model adopts the layout structure of the ring grid under the condition of meeting the design rules, which greatly saves the area of ​​the electrostatic protection layout structure and reserves a backup plan for the avalanche effect that may be induced by the square grid tip.

[0051] At the same time, the utility model has a self-protection function and improves the stability of the layout structure.

[0052] In addition, this design uses the same low-voltage devices as the internal circuit. When placing them, try to keep them close to the gate oxide layer that needs to be connected to form a close-coupled structure to avoid voltage drops caused by parasitic resistance and inductance, which may cause the actual voltage to be above the clamping voltage but not trigger.

[0053] At the same time, in some cases where the ESD requirements for integrated circuits are not high, the structure can also serve as secondary protection, but it still needs to follow the principle of close coupling, that is, the ESD protection structure is placed close to the protected device.

[0054] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A ring-shaped internal circuit electrostatic protection layout structure with back gate contact, characterized in that: It includes a resistor R0 connected to the input end and a PMOS transistor PM1, a PMOS transistor PM0, and an NMOS transistor NM0 connected to the output side of the resistor R0 from top to bottom, the resistor R0 is connected to the gate and drain of PM0, and the drain of NM0, the source of PM0 and the drain of PM1 are connected, and the drain of PM0 is connected to the output end; The gate and source of NM0 are both grounded, and the gate and source of PM1 are both connected to the power supply VDD; PM0, PM1 and NM0 are all annular MOS tubes with square gates or circular gates, and the sources of PM1 and NM0 are back-gate contacts.

2. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: Resistor R0 is a polysilicon current limiting resistor.

3. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 2, characterized in that: The resistance value of resistor R0 is 10kΩ and the width is 2um.

4. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: PM0, PM1 and NM0 all have square gates.

5. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: The distances from the drain contact holes of PM0, PM1 and NM0 to the polysilicon gate are all above 2 um.

6. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: The HRI layer is connected near the drain contact holes of PM0, PM1 and NM0.

7. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: The drain active regions of PM0, PM1, and NM0 include boron therein.

8. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: STRAP is connected between PM0, PM1 and NM0.

9. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: The sources and drains of PM0, PM1 and NM0 are all independent active regions.

10. The ring-shaped internal circuit electrostatic protection layout structure with back gate contact according to claim 1, characterized in that: The channel widths of PM0, PM1 and NM0 are all 10um and the channel lengths are all 500nm.

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