Anti-interference driving interlocking circuit

Abstract

The utility model discloses an anti-interference driving interlocking circuit, the driving interlocking circuit comprises a main control circuit, a DSP control chip and an interlocking execution unit, the interlocking execution unit comprises a controllable switch and a driving circuit, the controllable switch comprises an optocoupler U25, the optocoupler U25 comprises an optical coupler U25, and the driving circuit comprises an optical coupler U25. The driving circuit comprises a triode Q25, a triode Q89, a resistor R476, a capacitor C365, a capacitor C373, a resistor R482, a resistor R384, a resistor R654, a resistor R660, a resistor R661, a capacitor C366, a resistor R655, a capacitor C361 and a capacitor C367; through accurate control of the high-performance processor and real-time monitoring of the state detection module, accurate management and control of the interlocking execution unit are achieved, the safety and reliability of the interlocking circuit are improved, when the main control circuit sends an activation instruction, the driving circuit drives the controllable switch to be switched to be in a conduction state, and the controllable switch is switched to be in a closed state. And through two paths of driving signals, a single switching tube unit is controlled, and equipment damage or safety accidents caused by one path of fault are avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to an anti-interference driving interlocking circuit. Background Art

[0002] As electronic devices become more popular and more complex, interlock circuits are widely used as a common safety measure. However, existing interlock circuit systems often have safety defects. For example, when one circuit is operated incorrectly, the other circuit cannot effectively intervene, which may cause equipment damage or safety accidents. Utility Model Content

[0003] The purpose of the utility model is to provide an anti-interference drive interlocking circuit to solve the problems raised in the above background technology.

[0004] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: an anti-interference drive interlock circuit, the drive interlock circuit includes a main control circuit, a DSP control chip and an interlock execution unit, the interlock execution unit includes a controllable switch and a drive circuit, the controllable switch includes an optical coupler U25, the drive circuit includes a transistor Q25, a transistor Q89, a resistor R476, a capacitor C365, a capacitor C373, a resistor R482, a resistor R384, a resistor R654, a resistor R660, a resistor R661, a capacitor C366, a resistor R655, a capacitor C361, and a capacitor C367;

[0005] One end of the capacitor C365 is connected to the connection line between the first output end of the power supply and the transistor Q25, the other end of the capacitor C365 is grounded, the collector of the transistor Q25 is connected to one end of the resistor R476, the other end of the resistor R476 is connected to the chip pin Boost.B1, the common end between the transistor Q25 and the resistor R476 is connected to one end of the capacitor C373, the capacitor C373 and the resistor R482 are connected in parallel and grounded, the common end between the emitter of the transistor Q25 and the resistor R384 is connected to one end of the optical coupler U36, the common end between the optical coupler U25 and the resistor R384 is connected to the transistor Q89, and the transistor Q89 and the resistor R654 are connected in parallel to the resistor R660 On one end, resistor R660 is connected in parallel with resistor R661 and capacitor C366 respectively, the common end between resistor R661 and capacitor C366 is connected to the line between transistor Q89 and resistor R655, the other end of resistor R655 is connected to chip pin Buck.B2, one end of optocoupler U25 is connected to chip pin Boost.B1, one end of optocoupler U25 is connected to the second output end of the power supply, the common end between the second output end of the power supply and optocoupler U25 is connected to capacitor C361, one end of capacitor C361 is grounded, the other end of optocoupler U25 is connected to the power input end, the common end between the power input end and optocoupler U25 is connected to capacitor C367, one end of capacitor C367 is grounded.

[0006] Preferably, the optical coupler U25 includes an NPN transistor and a PNP transistor, one end of the driving interlocking circuit is connected to a switch tube unit, and the optical coupler U25 controls the switch tube unit through two driving signals.

[0007] Preferably, the main control circuit uses a microprocessor or a digital signal processor as a core controller, and the main control circuit receives external instructions through a multiplexer, and selectively activates or disables the interlock execution unit according to the instructions.

[0008] Preferably, the chip pins of the DSP control chip are Buck.B2 and Boost.B1 respectively, and Buck.B2 and Boost.B1 are correspondingly interlocked drives and are configured as opposite signals.

[0009] Preferably, when the main control circuit sends an activation instruction, the drive circuit will drive the controllable switch to switch to the on state, thereby achieving circuit interlocking; when the main control circuit sends a disable instruction, the controllable switch will switch to the off state to release the interlocking.

[0010] Compared with the prior art, the beneficial effects of the utility model are:

[0011] The utility model provides a driving interlocking circuit, which realizes accurate management and control of the interlocking execution unit through the accurate control of the high-performance processor and the real-time monitoring of the state detection module, thereby improving the safety and reliability of the interlocking circuit. When the main control circuit sends an activation instruction, the driving circuit will drive the controllable switch to switch to the on state, thereby realizing the interlocking of the circuit. The operation is simple, and a single switch tube unit is controlled through two-way driving signals, thereby avoiding equipment damage or safety accidents caused by a failure of one way. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a circuit diagram of one of the drive interlock circuits of the utility model.

[0013] Figure 2 This is a circuit diagram of another one of the drive interlock circuits of the utility model.

[0014] In the figure: optocoupler U25; transistor Q25; transistor Q89; resistor R476; capacitor C365; capacitor C373; resistor R482; resistor R384; resistor R654; resistor R660; resistor R661; capacitor C366; resistor R655; capacitor C361; capacitor C367. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0016] See also Figure 1 to Figure 2 The utility model provides a technical solution: an anti-interference drive interlock circuit, which includes a main control circuit, a DSP control chip and an interlock execution unit, the interlock execution unit includes a controllable switch and a drive circuit, the controllable switch includes an optical coupler U25, and the drive circuit includes a transistor Q25, a transistor Q89, a resistor R476, a capacitor C365, a capacitor C373, a resistor R482, a resistor R384, a resistor R654, a resistor R660, a resistor R661, a capacitor C366, a resistor R655, a capacitor C361, and a capacitor C367.

[0017] One end of capacitor C365 is connected to the line between the first output end of the power supply and the transistor Q25, the other end of capacitor C365 is grounded, the collector of transistor Q25 is connected to one end of resistor R476, the other end of resistor R476 is connected to chip pin Boost.B1, the common end between transistor Q25 and resistor R476 is connected to one end of capacitor C373, capacitor C373 and resistor R482 are connected in parallel and grounded, the common end between the emitter of transistor Q25 and resistor R384 is connected to one end of optocoupler U36, and the common end between optocoupler U25 and resistor R384 is connected to transistor Q89.

[0018] The transistor Q89 and the resistor R654 are connected in parallel to one end of the resistor R660. The resistor R660 is connected in parallel to the resistor R661 and the capacitor C366 respectively. The common end between the resistor R661 and the capacitor C366 is connected to the line between the transistor Q89 and the resistor R655. The other end of the resistor R655 is connected to the chip pin Buck.B2.

[0019] The optocoupler U25 includes an NPN transistor and a PNP transistor. One end of the optocoupler U25 is connected to the chip pin Boost.B1. One end of the drive interlock circuit is connected to the switch tube unit, so that when there is a false trigger caused by signal interference in the control signal, it can effectively avoid the short circuit closure of the switch tube. The optocoupler U25 controls the switch tube unit through two drive signals. If the two signals are set high at the same time, the switch tube will not be turned on.

[0020] One end of the optocoupler U25 is connected to the second output end of the power supply, and the common end between the second output end of the power supply and the optocoupler U25 is connected to a capacitor C361, one end of the capacitor C361 is grounded, and the other end of the optocoupler U25 is connected to the power input end, and the common end between the power input end and the optocoupler U25 is connected to a capacitor C367, one end of the capacitor C367 is grounded.

[0021] The main control circuit uses a high-performance microprocessor or digital signal processor as the core controller, and implements complex control logic and algorithms through programming. The main control circuit receives external instructions through a multiplexer and selectively activates or disables the interlock execution unit according to the instructions.

[0022] The chip pins of the DSP control chip are Buck.B2 and Boost.B1 respectively. Buck.B2 and Boost.B1 are corresponding interlocking drives and are configured as opposite signals.

[0023] When the main control circuit sends an activation instruction, the drive circuit will drive the controllable switch to switch to the on state, thereby realizing the interlocking of the circuit; when the main control circuit sends a disable instruction, the controllable switch will switch to the off state to release the interlocking.

[0024] In summary, the utility model provides a drive interlocking circuit, which realizes precise management and control of the interlocking execution unit through precise control of a high-performance processor and real-time monitoring of a status detection module, thereby improving the safety and reliability of the interlocking circuit. When the main control circuit sends an activation instruction, the drive circuit will drive the controllable switch to switch to the on state, thereby realizing the interlocking of the circuit. The operation is simple, and a single switch tube unit is controlled by two drive signals to avoid equipment damage or safety accidents caused by a failure in one path.

[0025] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An anti-interference drive interlock circuit, characterized in that: The driving interlocking circuit includes a main control circuit, a DSP control chip and an interlocking execution unit, the interlocking execution unit includes a controllable switch and a driving circuit, the controllable switch includes an optical coupler U25, and the driving circuit includes a transistor Q25, a transistor Q89, a resistor R476, a capacitor C365, a capacitor C373, a resistor R482, a resistor R384, a resistor R654, a resistor R660, a resistor R661, a capacitor C366, a resistor R655, a capacitor C361, and a capacitor C367; One end of the capacitor C365 is connected to the connection line between the first output end of the power supply and the transistor Q25, the other end of the capacitor C365 is grounded, the collector of the transistor Q25 is connected to one end of the resistor R476, the other end of the resistor R476 is connected to the chip pin Boost.B1, the common end between the transistor Q25 and the resistor R476 is connected to one end of the capacitor C373, the capacitor C373 and the resistor R482 are connected in parallel and grounded, the common end between the emitter of the transistor Q25 and the resistor R384 is connected to one end of the optical coupler U36, the common end between the optical coupler U25 and the resistor R384 is connected to the transistor Q89, and the transistor Q89 and the resistor R654 are connected in parallel to the resistor R660 On one end, resistor R660 is connected in parallel with resistor R661 and capacitor C366 respectively, the common end between resistor R661 and capacitor C366 is connected to the line between transistor Q89 and resistor R655, the other end of resistor R655 is connected to chip pin Buck.B2, one end of optocoupler U25 is connected to chip pin Boost.B1, one end of optocoupler U25 is connected to the second output end of the power supply, the common end between the second output end of the power supply and optocoupler U25 is connected to capacitor C361, one end of capacitor C361 is grounded, the other end of optocoupler U25 is connected to the power input end, the common end between the power input end and optocoupler U25 is connected to capacitor C367, one end of capacitor C367 is grounded.

2. The anti-interference drive interlock circuit according to claim 1, characterized in that: The optical coupler U25 includes an NPN transistor and a PNP transistor. One end of the driving interlock circuit is connected to a switch tube unit. The optical coupler U25 controls the switch tube unit through two driving signals.

3. The anti-interference drive interlock circuit according to claim 1, characterized in that: The main control circuit adopts a microprocessor or a digital signal processor as a core controller. The main control circuit receives external instructions through a multiplexer and selectively activates or disables the interlock execution unit according to the instructions.

4. The anti-interference drive interlock circuit according to claim 1, characterized in that: The chip pins of the DSP control chip are Buck.B2 and Boost.B1 respectively. Buck.B2 and Boost.B1 are corresponding interlocking drives and are configured as opposite signals.

5. The anti-interference drive interlock circuit according to claim 1, characterized in that: When the main control circuit sends an activation instruction, the drive circuit drives the controllable switch to switch to the on state, thereby realizing the interlocking of the circuit; When the main control circuit sends a disable command, the controllable switch will switch to the off state and release the interlock.

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