PCIE expansion board card supporting multi-slot double-width GPU

Abstract

The utility model provides a PCIE (Peripheral Component Interconnect Express) expansion board card supporting a multi-slot double-width GPU (Graphics Processing Unit), which is characterized by comprising an expansion board, and the expansion board comprises a plurality of PCIE slots, a plurality of MCIO (Multi-Chip Input / Output) interfaces and a plurality of power interfaces; the first PCIE switching chip and the second PCIE switching chip are connected with the expansion board through an MCIO interface, and the first PCIE switching chip and the second PCIE switching chip are respectively provided with at least five PCIE * 16 slots in an expansion mode. A more efficient and economical PCIe expansion solution is provided for the field of AI servers so as to meet the increasing requirements of artificial intelligence applications for high-performance computing resources.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, and in particular to a PCIE expansion board supporting multi-slot double-width GPUs. Background Art

[0002] GPU, full name Graphics Processing Unit, is a microprocessor specially designed to process graphics and image data. It was originally developed to accelerate computer graphics rendering, but over time, the architecture and functionality of GPUs have evolved to handle a wider range of computing tasks, especially excelling in parallel processing. GPUs have hundreds or thousands of cores and can process large amounts of data at the same time, making them ideal for tasks that require a lot of parallel computing. In the field of AI, especially in deep learning, a large number of matrix operations and data parallel operations need to be processed during model training and inference. The parallel processing capabilities of GPUs make them an ideal choice for accelerating these tasks. Deep learning models typically contain a large number of neural network layers, each of which requires a large number of matrix multiplications and activation function calculations. GPUs can efficiently perform these computationally intensive operations, significantly shortening training time and improving the efficiency of model training.

[0003] Traditional server configurations usually rely on the CPU and a limited number of GPUs to handle computing tasks, but as the complexity of tasks increases and the amount of data surges, the computing power of a single GPU is often unable to meet the growing performance requirements. To meet this challenge, GPU servers came into being. These servers are specially designed to support multiple GPU cards to improve computing efficiency through parallel computing and accelerated task processing. However, traditional server architectures have limitations in supporting multi-GPU configurations, such as the limited number of PCIe slots on the motherboard, and the size and heat dissipation requirements of GPU cards pose additional challenges to server design. In addition, the computational data between GPUs connected to the CPU downstream port needs to be processed by the CPU, which may cause the CPU to become a performance bottleneck and increase the latency of data processing. These limiting factors not only affect the flexibility of server configuration, but also restrict its scalability, making it difficult to meet the ever-changing needs of high-performance computing. Utility Model Content

[0004] In view of this, the purpose of the utility model is to provide a PCIE expansion board that supports multi-slot double-width GPUs, aiming to provide a more efficient and economical PCIe expansion solution for the AI ​​server field.

[0005] The technical solution adopted by the utility model to solve the above technical problems is as follows:

[0006] The utility model provides a PCIE expansion board supporting multi-slot double-width GPUs, including an expansion board, wherein the expansion board includes multiple PCIE slots, multiple MCIO interfaces and multiple power interfaces;

[0007] A first PCIE switching chip and a second PCIE switching chip, wherein the first PCIE switching chip and the second PCIE switching chip are connected to the expansion board through an MCIO interface, and the first PCIE switching chip and the second PCIE switching chip each expand at least 5 PCIEx16 slots.

[0008] In some embodiments, the first PCIE switch chip and the second PCIE switch chip are PEX88096.

[0009] In some embodiments, the expansion board is provided with 13 PCIE slots, 10 of which are used to connect a double-width GPU card, 1 of which is used to connect a network card, and the remaining 2 PCIE slots are used to connect other devices;

[0010] The expansion board is provided with 9 MCIO interfaces for connecting the uplink ports of the first PCIE switch chip and the second PCIE switch chip;

[0011] The expansion board is provided with two power supply interfaces for receiving power.

[0012] In some embodiments, the PCIE slot includes:

[0013] A first PCIE slot, wherein the first PCIE slot is connected to a server mainboard through a first MCIO interface and a second MCIO interface using a cable to provide a PCIEX16 signal;

[0014] A second PCIE slot, wherein the second PCIE slot is connected to the server mainboard through a third MCIO interface using a cable to provide a PCIEX8 signal;

[0015] A third PCIE slot, wherein the third PCIE slot is a PCIEx16 signal PCIE slot output by the first PCIE switching chip;

[0016] A fourth PCIE slot, wherein the fourth PCIE slot is a PCIEx16 signal PCIE slot output by the first PCIE switching chip;

[0017] A fifth PCIE slot, wherein the fifth PCIE slot is a PCIEx16 signal PCIE slot output by the first PCIE switching chip;

[0018] A sixth PCIE slot, wherein the sixth PCIE slot is a PCIEx16 signal PCIE slot output by the first PCIE switching chip;

[0019] A seventh PCIE slot, wherein the seventh PCIE slot is a PCIEx16 signal PCIE slot output by the first PCIE switching chip;

[0020] An eighth PCIE slot, wherein the eighth PCIE slot is a PCIEx16 signal PCIE slot output by the second PCIE switching chip;

[0021] A ninth PCIE slot, wherein the ninth PCIE slot is a PCIEx16 signal PCIE slot output by the second PCIE switching chip;

[0022] A tenth PCIE slot, wherein the tenth PCIE slot is a PCIEx16 signal PCIE slot output by the second PCIE switching chip;

[0023] An eleventh PCIE slot, wherein the eleventh PCIE slot is a PCIE x16 signal PCIE slot output by the second PCIE switch chip;

[0024] A twelfth PCIE slot, wherein the twelfth PCIE slot is connected to the server mainboard through the fourth MCIO interface and the fifth MCIO interface using a cable to provide a PCIEX16 signal;

[0025] The thirteenth PCIE slot is a PCIE slot for outputting a PCIE x16 signal from the second PCIE switching chip.

[0026] In some embodiments, the MCIO interface includes:

[0027] A first MCIO interface is connected to the first slot and provides a PCIEX8 signal;

[0028] The second MCIO interface is connected to the first slot and provides a PCIEX8 signal;

[0029] The third MCIO interface is connected to the second slot and provides PCIEX8 signal;

[0030] The fourth MCIO interface is connected to the twelfth slot and provides PCIEX8 signal;

[0031] The fifth MCIO interface is connected to the twelfth slot and provides PCIEX8 signal;

[0032] The sixth MCIO interface is connected to the uplink port of the first PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIEX8 signal;

[0033] The seventh MCIO interface is connected to the uplink port of the first PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIEX8 signal;

[0034] The eighth MCIO interface is connected to the uplink port of the second PCIE switch chip and is connected to the mainboard through an X8 cable to provide PCIEX8 signals;

[0035] The ninth MCIO interface is connected to the uplink port of the second PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIEX8 signal.

[0036] In some embodiments, the power interface includes a first power interface and a second power interface, and the first power interface and the second power interface respectively take 12V power and 3.3V power, and then convert through DC / DC and LDO power chips to provide CORE power for the first PCIE switching chip and the second PCIE switching chip and power for the PCIE slot.

[0037] In some embodiments, the uplink interfaces of the first PCIE switch chip and the second PCIE switch chip are connected to the server motherboard through two sets of PCIEX16 signals, and the first PCIE slot, the second PCIE slot and the twelfth PCIE slot are PCIE slots directly connected to the server motherboard.

[0038] In some embodiments, a clock BUFFER is included, which is used to receive a 100MHz clock signal provided by the motherboard, and replicate and enhance it to meet the clock requirements of the first PCIE switch chip, the second PCIE switch chip and the PCIE slot, wherein the clock signal output by the BUFFER of the sixth MCIO interface is distributed to the first PCIE slot and the third PCIE slot to the seventh PCIE slot, wherein the clock signal output by the BUFFER of the eighth MCIO interface is distributed to the eighth PCIE slot to the thirteenth PCIE slot, wherein the clock signal output by the BUFFER of the third MCIO interface is distributed to the second PCIE slot.

[0039] In some embodiments, the fan interface includes a first fan interface, a second fan interface, a third fan interface, a fourth fan interface, and a fifth fan interface.

[0040] The PCIE expansion card supporting multi-slot double-width GPU provided by the embodiment of the utility model is mainly composed of a switching chip, a power distribution component, a signal distribution component, a heat dissipation component and a monitoring component. In actual use, the power distribution component is composed of multiple power modules, which provide independent power supply for each PCIE slot to ensure that each slot can obtain stable power support. Each power module is connected to the power management system through an independent power channel to achieve accurate control and management of the power supply of each slot.

[0041] The switch chip PEX88096 can optimize the bandwidth allocation of the PCIE bus to ensure more efficient data transmission. It can dynamically adjust resource allocation according to the bandwidth requirements of each device, thereby improving the data throughput of the entire system.

[0042] The signal distribution component is responsible for distributing the PCIe signal of the motherboard to each PCIE slot to ensure the efficiency and stability of data transmission. By using high-speed signal buffers and clock management chips, the signal transmission path is optimized, signal delay is reduced, and the data processing rate is increased.

[0043] The heat dissipation component includes multiple cooling fans and heat sinks, which are designed to fit closely with the PCIE slot to ensure that the GPU and other high-performance computing devices can still maintain the optimal operating temperature under high load. The heat dissipation component monitors the device temperature in real time through the temperature sensor and automatically adjusts the fan speed as needed to achieve the best heat dissipation effect.

[0044] The monitoring component is responsible for real-time monitoring of the operating status of the expansion board, including key parameters such as power supply voltage, current, temperature, etc. Through the integrated monitoring software, users can remotely view and manage these parameters to ensure stable system operation. The monitoring component also has a fault warning function. Once an abnormality is detected, the user will be notified immediately to avoid potential system failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the expansion board structure of an embodiment of the utility model;

[0046] Figure 2 This is a schematic diagram of power distribution in an embodiment of the utility model;

[0047] Figure 3 A schematic diagram of PCIE signals according to an embodiment of the present utility model;

[0048] Figure 4 A schematic diagram of a clock design according to an embodiment of the utility model;

[0049] Figure 5 This is a schematic diagram of the expansion board structure of an embodiment of the utility model;

[0050] Description of the accompanying drawings: 100, expansion board; 101, first PCIE slot; 102, second PCIE slot; 103, third PCIE slot; 104, fourth PCIE slot; 105, fifth PCIE slot; 106, sixth PCIE slot; 107, seventh PCIE slot; 108, eighth PCIE slot; 109, ninth PCIE slot; 110, tenth PCIE slot; 111, eleventh PCIE slot; 112, twelfth PCIE slot; 113, thirteenth PCIE slot; 201, sixth MCIO interface; 202, the Seventh MCIO interface; 203, eighth MCIO interface; 204, ninth MCIO interface; 205, first MCIO interface; 206, second MCIO interface; 207, third MCIO interface; 208, fourth MCIO interface; 209, fifth MCIO interface; 301, first fan interface; 302, second fan interface; 303, third fan interface; 304, fourth fan interface; 305, fifth fan interface; 401, first power interface; 402, second power interface; 501, first PCIE switching chip; 502, second PCIE switching chip. DETAILED DESCRIPTION

[0051] The overall idea of ​​the technical solution provided by the utility model is as follows:

[0052] See also Figures 1 to 5 , a PCIE expansion board supporting multi-slot double-width GPUs, comprising an expansion board 100, wherein the expansion board 100 comprises a plurality of PCIE slots, a plurality of MCIO interfaces and a plurality of power interfaces;

[0053] A first PCIE switching chip 501 and a second PCIE switching chip 502 are connected to the expansion board 100 via an MCIO interface. The first PCIE switching chip 501 and the second PCIE switching chip 502 each expand at least 5 PCIEx16 slots.

[0054] PCI Express (PCIe), as a high-speed, high-bandwidth interface technology, is the key to connecting various high-performance computing and storage components in AI servers. The embodiment of the utility model is designed for the special needs of AI servers by using a PCIe expansion board based on the PEX88096 chip, providing optimized bandwidth management, reduced data transmission latency and higher energy efficiency, especially showing significant advantages in supporting large-scale parallel processing and fast data access. It aims to provide a more efficient and economical PCIe expansion solution for the AI ​​server field to meet the growing demand for high-performance computing resources in artificial intelligence applications. PEX88096 has 96 PCIE GEN4 channels with a rate of up to 16GT / s. The expansion board uses two PEX88096 chips. The upstream port of each PEX88096 chip is configured as X16 and connected to the mainboard end through 2 MCIOX8 cables. Each PEX88096 chip expands 5 X16 downstream slots. The expansion board has a total of 13 PCIE slots, which can simultaneously support the expansion of 10 PCIEX16 double-width GPU cards plus a single-width network card.

[0055] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0056] See also Figure 5 , the first PCIE switch chip 501 and the second PCIE switch chip 502 are PEX88096. It can provide high-speed data transmission capability, support a large number of device connections, optimized bandwidth management, high energy efficiency, support double-width GPU cards, and provide flexibility and scalability. These features together meet the needs of AI servers for high-performance computing resources.

[0057] See also Figure 1 , the expansion board 100 is provided with 13 PCIE slots, 10 of which are used to connect a double-width GPU card, 1 of which is used to connect a network card, and the remaining 2 PCIE slots are used to connect other devices;

[0058] The expansion board 100 is provided with 9 MCIO interfaces for connecting the uplink ports of the first PCIE switch chip 501 and the second PCIE switch chip 502;

[0059] The expansion board 100 is provided with two power interfaces for receiving power.

[0060] Preferably, by installing the network card in the PCIE slot on the PCIe expansion board, the user can choose a network card with different performance as needed, thereby achieving flexibility and customizability of network connection. This allows users to choose a suitable network card according to the needs of specific applications, such as high bandwidth, low latency or specific network protocol support. High-performance network cards can provide higher data transmission rates and lower latency, which is essential for applications that require large amounts of data transmission and real-time communication, such as AI servers, high-performance computing, etc. Connecting the network card through the PCIe expansion board can ensure that network communication will not become a bottleneck for system performance. Installing the network card on the PCIe expansion board makes the maintenance and upgrade of network equipment more convenient. If you need to replace the network card or upgrade the network performance, you only need to simply replace or upgrade the network card on the PCIe expansion board without touching the motherboard. The network card on the PCIe expansion board can support a variety of network standards and protocols, including but not limited to 10G, 25G, 40G, 100G Ethernet, etc., which provides users with a wide range of choices to meet the needs of different network environments.

[0061] Preferably, in the PCIe expansion board, in addition to the PCIE slots used to connect the network card, the remaining PCIE slots can be connected to other devices. By using additional PCIE slots to connect other devices, such as storage devices (such as SSDs), high-performance network interface cards (NICs), professional graphics cards, encryption cards, etc., the functionality and performance of the system can be significantly increased. This enables the system to handle more complex data processing tasks and increase the speed of data storage and transmission. These additional PCIE slots allow users to customize the system configuration according to specific application requirements and workloads. For example, if the system needs to handle a large amount of data storage and backup tasks, more storage devices can be added; if video editing or 3D rendering is required, a high-performance graphics card can be added.

[0062] See also Figure 1 , the PCIE slot comprises:

[0063] A first PCIE slot 101, wherein the first PCIE slot 101 is connected to the server mainboard through a first MCIO interface 205 and a second MCIO interface 206 using a cable to provide a PCIEX16 signal;

[0064] A second PCIE slot 102, wherein the second PCIE slot 102 is connected to the server mainboard via a third MCIO interface 207 using a cable to provide a PCIEX8 signal;

[0065] A third PCIE slot 103, wherein the third PCIE slot 103 is a PCIEx16 signal PCIE slot output by the first PCIE switching chip 501;

[0066] A fourth PCIE slot 104, wherein the fourth PCIE slot 104 is a PCIEx16 signal PCIE slot output by the first PCIE switching chip 501;

[0067] A fifth PCIE slot 105, wherein the fifth PCIE slot 105 is a PCIEx16 signal PCIE slot output by the first PCIE switching chip 501;

[0068] A sixth PCIE slot 106, wherein the sixth PCIE slot 106 is a PCIEx16 signal PCIE slot output by the first PCIE switching chip 501;

[0069] A seventh PCIE slot 107, wherein the seventh PCIE slot 107 is a PCIEx16 signal PCIE slot output by the first PCIE switching chip 501;

[0070] An eighth PCIE slot 108 , wherein the eighth PCIE slot 108 is a PCIEx16 signal PCIE slot output by the second PCIE switching chip 502 ;

[0071] A ninth PCIE slot 109, wherein the ninth PCIE slot 109 is a PCIEx16 signal PCIE slot output by the second PCIE switching chip 502;

[0072] The tenth PCIE slot 110 is a PCIE slot for PCIEx16 signals output by the second PCIE switching chip 502;

[0073] An eleventh PCIE slot 111, wherein the eleventh PCIE slot 111 is a PCIEx16 signal PCIE slot output by the second PCIE switching chip 502;

[0074] A twelfth PCIE slot 112, wherein the twelfth PCIE slot 112 is connected to the server mainboard through the fourth MCIO interface 208 and the fifth MCIO interface 209 using a cable to provide a PCIEX16 signal;

[0075] The thirteenth PCIE slot 113 is a PCIE slot for outputting a PCIEx16 signal from the second PCIE switching chip 502 .

[0076] See also Figure 5 , the MCIO interface comprises:

[0077] The first MCIO interface 205 is connected to the first slot and provides a PCIEX8 signal;

[0078] The second MCIO interface 206 is connected to the first slot and provides a PCIEX8 signal;

[0079] The third MCIO interface 207 is connected to the second slot and provides a PCIEX8 signal;

[0080] The fourth MCIO interface 208 is connected to the twelfth slot and provides a PCIEX8 signal;

[0081] The fifth MCIO interface 209 is connected to the twelfth slot and provides a PCIEX8 signal;

[0082] The sixth MCIO interface 201 is connected to the uplink port of the first PCIE switch chip 501 and is connected to the mainboard via an X8 cable to provide a PCIEX8 signal;

[0083] The seventh MCIO interface 202 is connected to the uplink port of the first PCIE switch chip 501 and is connected to the mainboard through an X8 cable to provide a PCIEX8 signal;

[0084] The eighth MCIO interface 203 is connected to the uplink port of the second PCIE switch chip 502 and is connected to the mainboard via an X8 cable to provide a PCIEX8 signal;

[0085] The ninth MCIO interface 204 is connected to the uplink port of the second PCIE switch chip 502 and is connected to the mainboard via an X8 cable to provide a PCIEX8 signal.

[0086] See also Figure 1 The power interface includes a first power interface 401 and a second power interface 402. The first power interface 401 and the second power interface 402 respectively take 12V power and 3.3V power, and then convert through DC / DC and LDO power chips to provide CORE power for the first PCIE switching chip 501 and the second PCIE switching chip 502 and power for the PCIE slot.

[0087] See also Figure 5 The uplink interfaces of the first PCIE switching chip 501 and the second PCIE switching chip 502 are connected to the server mainboard through two sets of PCIEX16 signals, and the first PCIE slot 101, the second PCIE slot 102 and the twelfth PCIE slot 112 are PCIE slots directly connected to the server mainboard.

[0088] See also Figure 4, since the PEX88096 chip itself needs to input 2 clock signals, and the upstream PCIE signal has only 1 pair of 100MHz clocks, a clock BUFFER needs to be introduced to expand the clock. A clock BUFFER is included, which is used to receive the 100MHz clock signal provided by the motherboard, and to copy and enhance it to meet the clock requirements of the first PCIE switching chip 501, the second PCIE switching chip 502 and the PCIE slot, wherein the clock signal output by the BUFFER of the sixth MCIO interface 201 is distributed to the first PCIE slot 101 and the third PCIE slot 103 to the seventh PCIE slot 107, wherein the clock signal output by the BUFFER of the eighth MCIO interface 203 is distributed to the eighth PCIE slot 108 to the thirteenth PCIE slot 113, wherein the clock signal output by the third MCIO interface 207 is distributed to the second PCIE slot 102.

[0089] See also Figure 1 , the fan interface includes a first fan interface 301, a second fan interface 302, a third fan interface 303, a fourth fan interface 304 and a fifth fan interface 305. Although the preferred embodiments of the utility model have been described, those skilled in the art may make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the attached claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the utility model.

[0090] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A PCIE expansion card supporting multi-slot double-width GPUs, characterized in that: It includes an expansion board, wherein the expansion board includes multiple PCIE slots, multiple MCIO interfaces and multiple power interfaces; A first PCIE switching chip and a second PCIE switching chip, wherein the first PCIE switching chip and the second PCIE switching chip are connected to the expansion board through an MCIO interface, and the first PCIE switching chip and the second PCIE switching chip each expand at least 5 PCIE x16 slots.

2. The PCIE expansion card supporting multi-slot double-width GPU according to claim 1, characterized in that: The first PCIE switch chip and the second PCIE switch chip are PEX88096.

3. The PCIE expansion card supporting multi-slot double-width GPU according to claim 1 or 2, characterized in that: The expansion board is provided with 13 PCIE slots, 10 of which are used to connect double-width GPU cards, 1 of which is used to connect a network card, and the remaining 2 PCIE slots are used to connect other devices; The expansion board is provided with 9 MCIO interfaces for connecting the uplink ports of the first PCIE switch chip and the second PCIE switch chip; The expansion board is provided with two power supply interfaces for receiving power.

4. The PCIE expansion card supporting multi-slot double-width GPU according to claim 3, characterized in that: The PCIE slot includes: A first PCIE slot, wherein the first PCIE slot is connected to a server mainboard through a first MCIO interface and a second MCIO interface using a cable to provide a PCIE X16 signal; A second PCIE slot, wherein the second PCIE slot is connected to the server mainboard through a third MCIO interface using a cable to provide a PCIE X8 signal; A third PCIE slot, wherein the third PCIE slot is a PCIE x16 signal PCIE slot output by the first PCIE switching chip; A fourth PCIE slot, wherein the fourth PCIE slot is a PCIE x16 signal PCIE slot output by the first PCIE switching chip; A fifth PCIE slot, wherein the fifth PCIE slot is a PCIE x16 signal PCIE slot output by the first PCIE switch chip; A sixth PCIE slot, wherein the sixth PCIE slot is a PCIE x16 signal PCIE slot output by the first PCIE switch chip; A seventh PCIE slot, wherein the seventh PCIE slot is a PCIE x16 signal PCIE slot output by the first PCIE switching chip; An eighth PCIE slot, wherein the eighth PCIE slot is a PCIE x16 signal PCIE slot output by the second PCIE switch chip; A ninth PCIE slot, wherein the ninth PCIE slot is a PCIE x16 signal PCIE slot output by the second PCIE switching chip; A tenth PCIE slot, wherein the tenth PCIE slot is a PCIE x16 signal PCIE slot output by the second PCIE switch chip; An eleventh PCIE slot, wherein the eleventh PCIE slot is a PCIE x16 signal PCIE slot output by the second PCIE switch chip; A twelfth PCIE slot, wherein the twelfth PCIE slot is connected to the server mainboard through the fourth MCIO interface and the fifth MCIO interface using a cable to provide a PCIE X16 signal; The thirteenth PCIE slot is a PCIE slot for outputting a PCIE x16 signal from the second PCIE switching chip.

5. The PCIE expansion card supporting multi-slot double-width GPU according to claim 3, characterized in that: The MCIO interface includes: The first MCIO interface is connected to the first slot and provides a PCIE X8 signal; The second MCIO interface is connected to the first slot and provides a PCIE X8 signal; The third MCIO interface is connected to the second slot and provides PCIE X8 signal; The fourth MCIO interface is connected to the twelfth slot and provides PCIE X8 signal; The fifth MCIO interface is connected to the twelfth slot and provides PCIE X8 signal; The sixth MCIO interface is connected to the uplink port of the first PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIE X8 signal; The seventh MCIO interface is connected to the uplink port of the first PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIE X8 signal; The eighth MCIO interface is connected to the uplink port of the second PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIE X8 signal; The ninth MCIO interface is connected to the uplink port of the second PCIE switch chip and is connected to the mainboard through an X8 cable to provide a PCIE X8 signal.

6. The PCIE expansion card supporting multi-slot double-width GPU according to claim 3, characterized in that: The power interface includes a first power interface and a second power interface, the first power interface and the second power interface respectively take 12V power and 3.3V power, and then convert through DC / DC and LDO power chips to provide CORE power for the first PCIE switching chip and the second PCIE switching chip and power for the PCIE slot.

7. The PCIE expansion card supporting multi-slot double-width GPU according to claim 3, characterized in that: The uplink interfaces of the first PCIE switching chip and the second PCIE switching chip are connected to the server mainboard via two groups of PCIE X16 signals, and the first PCIE slot, the second PCIE slot and the twelfth PCIE slot are PCIE slots directly connected to the server mainboard.

8. The PCIE expansion card supporting multi-slot double-width GPUs according to claim 3, characterized in that: It includes a clock BUFFER, which is used to receive a 100MHz clock signal provided by the motherboard, and replicate and enhance it to meet the clock requirements of the first PCIE switching chip, the second PCIE switching chip and the PCIE slot, wherein the clock signal output by the BUFFER of the sixth MCIO interface is distributed to the first PCIE slot and the third PCIE slot to the seventh PCIE slot, wherein the clock signal output by the BUFFER of the eighth MCIO interface is distributed to the eighth PCIE slot to the thirteenth PCIE slot, wherein the clock signal output by the third MCIO interface is distributed to the second PCIE slot.

9. The PCIE expansion card supporting multi-slot double-width GPU according to claim 3, characterized in that: The device also includes fan interfaces, which include a first fan interface, a second fan interface, a third fan interface, a fourth fan interface, and a fifth fan interface.

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