Power module

Abstract

The utility model provides a power module. The power module comprises a substrate, a first part and a second packaging body, the substrate includes a plurality of first conductive structures. The first component includes a first bare chip, a plurality of first conductive elements each electrically connected to the first bare chip, and a first package wrapping the first bare chip and the plurality of first conductive elements. A portion of each first conductive element is exposed from the first package and is connected to a corresponding first conductive structure of the substrate. The second packaging body is arranged on the substrate and at least covers connection parts of the plurality of first conductive elements and the corresponding first conductive structures. According to the configuration of the power module, the research and development period of the power module can be shortened, and the research and development and production cost of the power module can be reduced.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of power devices, and more particularly to a power module. Background Art

[0002] Power devices are electronic devices used to achieve power regulation and conversion. Power devices are mainly divided into discrete devices and power modules. Discrete devices usually include a single bare die encapsulated in a housing and are suitable for low-power applications. Power modules can integrate multiple bare chips according to specific application requirements and are suitable for medium and high-power applications.

[0003] Typically, a power module includes a substrate, a plurality of bare chips directly welded on the substrate, and a package body arranged on the substrate to wrap the plurality of bare chips. The substrate provides mechanical support and electrical connection to the bare chips. The substrate may be formed with a conductive pattern, and the plurality of bare chips may be electrically interconnected or electrically connected to other electrical components located inside or outside the power module via the conductive pattern. The bare chip includes a die-attach layer for welding to the conductive pattern of the substrate and a bonding layer for wire bonding and electrically connected to the conductive pattern by wire. The pins may be connected to the circuit pattern of the substrate in the package body, and a portion of the pins may extend from the package body to be connected to other electrical components located outside the module, such as a printed circuit board (PCB) on which the power module is to be installed. In this way, the bare chip may be electrically connected to other electrical components located outside the module through the circuit pattern and pins of the substrate.

[0004] Reliability is an important performance indicator of power modules. During the R&D stage, according to power module test and certification specifications such as AQG 324 issued by the European Power Electronics Research Center (ECPE), many tests are required to verify the reliability of the power module. These tests mainly include QM-Module Test, Characterizing Module Testing, Environmental Testing, Life Testing, and Final Testing for Recording the Electrical Parameters of All DUTs. The die attach layer and bonding layer of the bare chip are very fragile parts and are prone to fatigue failure. Therefore, during the R&D stage, if the design of the power module is modified, the entire power module needs to be retested to verify its reliability, even for minor modifications. This results in the R&D of power modules often taking several months or even a year, which is long and costly.

[0005] During the production stage, power modules are usually manufactured through the following process: wafers are diced to obtain bare chips; a series of reliability tests are performed on the bare chips to screen out qualified bare chips; multiple qualified bare chips are welded on the same substrate and packaged to obtain power modules. However, there is a problem in this manufacturing process: before the bare chips are packaged, some reliability tests (for example, withstand voltage tests under high voltage) cannot be performed on the bare chips because the bare chips are exposed to air or an environment without protective gas. This will cause some unqualified bare chips to be unable to be detected, and these unqualified bare chips will be integrated into the same power module together with qualified bare chips. The presence of unqualified bare chips in the power module will cause the overall parameters of the power module to be unqualified when the power module is tested later. This will cause the yield of the power module to be lower than the yield of the bare chip, waste manufacturing resources, and thus increase manufacturing costs. Utility Model Content

[0006] In view of this, the present disclosure aims to propose a new power module to shorten the R&D cycle of the power module and reduce its R&D and production costs.

[0007] The present application proposes a power module. The power module comprises: a substrate comprising a plurality of first conductive structures; a first component mounted on the substrate, the first component comprising a first bare chip, a plurality of first conductive elements each electrically connected to the first bare chip, and a first package encapsulating the first bare chip and the plurality of first conductive elements, wherein a portion of each of the first conductive elements is exposed from the first package and connected to the corresponding first conductive structure of the substrate; and a second package, the second package being disposed on the substrate and at least covering the connection portions between the plurality of first conductive elements and the corresponding first conductive structures.

[0008] In some embodiments, the multiple first conductive elements of the first component include one or more first gate conductive elements, one or more first source conductive elements, and one or more first drain conductive elements, the multiple first conductive structures of the substrate include one or more first gate conductive structures, one or more first source conductive structures, and one or more first drain conductive structures, a portion of each of the first gate conductive elements is exposed from the first package body and connected to the corresponding first gate conductive structure, a portion of each of the first source conductive elements is exposed from the first package body and connected to the corresponding first source conductive structure, and a portion of each of the first drain conductive elements is exposed from the first package body and connected to the corresponding first drain conductive structure.

[0009] In some embodiments, the first package body includes a first bottom surface facing the substrate, and each of the first conductive elements of the first component is configured to be in the form of a first conductive pad, the first conductive pad is exposed at the first bottom surface, and each of the first conductive structures of the substrate is configured to be in the form of a first mating conductive pad, and each of the first conductive pads is soldered to the corresponding first mating conductive pad.

[0010] In some embodiments, the first bottom surface of the first package body includes four side edges, the multiple first conductive elements are arranged into four rows, each of the four rows is arranged adjacent to a corresponding one of the four side edges, and the first conductive elements in each of the rows include a first gate conductive element, a first source conductive element, and a first drain conductive element, wherein: the shape of the first bottom surface of the first package body is square, and for the four rows, the configurations of the first gate conductive element, the first source conductive element, and the first drain conductive element are rotationally symmetrical at 90 degrees about the center of the first bottom surface; or the shape of the first bottom surface of the first package body is rectangular, and for two of the four rows that are arranged adjacent to two opposite long sides of the first bottom surface, the configurations of the first gate conductive element, the first source conductive element, and the first drain conductive element are rotationally symmetrical at 180 degrees about the center of the first bottom surface, and for the other two of the four rows that are arranged adjacent to two opposite short sides of the first bottom surface, the configurations of the first gate conductive element, the first source conductive element, and the first drain conductive element are rotationally symmetrical at 180 degrees about the center of the first bottom surface.

[0011] In some embodiments, the first component also includes a central conductive pad, which extends from the first bare chip to the first bottom surface and is exposed at a central area of ​​the first bottom surface, and the substrate also includes a second mating conductive pad, and the central conductive pad is soldered to the second mating conductive pad.

[0012] In some embodiments, the substrate also includes multiple second conductive structures, and the power module includes: a second component mounted on the substrate, the second component including a second bare chip, multiple second conductive elements each electrically connected to the second bare chip, and a third package body encapsulating the second bare chip and the multiple second conductive elements, wherein a portion of each second conductive element is exposed from the third package body and connected to the corresponding second conductive structure of the substrate; and at least one interconnection structure, each of the interconnection structures electrically connecting the corresponding first conductive structure to the corresponding second conductive structure to establish an electrical connection between the first bare chip and the second bare chip.

[0013] In some embodiments, the plurality of second conductive elements of the second component include one or more second gate conductive elements, one or more second source conductive elements, and one or more second drain conductive elements, the plurality of second conductive structures of the substrate include one or more second gate conductive structures, one or more second source conductive structures, and one or more second drain conductive structures, a portion of each of the second gate conductive elements is exposed from the third package body and connected to the corresponding second gate conductive structure, a portion of each of the second source conductive elements is exposed from the third package body and connected to the corresponding second source conductive structure, and a portion of each of the second drain conductive elements is exposed from the third package body and connected to the corresponding second drain conductive structure, the plurality of first conductive elements of the first component include one or more first drain conductive elements, the plurality of first conductive structures of the substrate include one or more first drain conductive structures, a portion of each of the first drain conductive elements is exposed from the first package body and connected to the corresponding first drain conductive structure, and each of the interconnect structures electrically connects the corresponding first drain conductive structure with the corresponding second source conductive structure.

[0014] In some embodiments, the third package body includes a second bottom surface facing the substrate, and each of the second conductive elements of the second component is configured as a second conductive pad, the second conductive pad is exposed at the second bottom surface, each of the second conductive structures of the substrate is configured as a third mating conductive pad, each of the second conductive pad is soldered to the corresponding third mating conductive pad, and the at least one interconnect structure includes at least one of a bonding wire, a conductive trace arranged at the surface of the substrate, and a conductive layer arranged in the substrate.

[0015] In some embodiments, the first component and the second component are electrically connected by the at least one interconnect structure to form a part of a bridge circuit.

[0016] In some embodiments, the second package body covers the first component, the second component, the plurality of first conductive structures, the plurality of second conductive structures, and the at least one interconnect structure.

[0017] In some embodiments, the first component has a QFN package configuration.

[0018] In some embodiments, the second component has a QFN package configuration.

[0019] In some embodiments, the first bare chip is a MOSFET bare chip or an IGBT bare chip.

[0020] In some embodiments, the second bare chip is a MOSFET bare chip or an IGBT bare chip.

[0021] In some embodiments, the substrate is a ceramic-based copper-clad laminate, and the plurality of first conductive structures and the plurality of second conductive structures are formed from a same copper layer of the substrate.

[0022] These techniques may be used alone or in any suitable combination.The foregoing summary is provided by way of illustration and is not meant to be limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects of the present disclosure will be more thoroughly understood and appreciated in conjunction with the accompanying drawings. It should be noted that the drawings are schematic only and are not drawn to scale. In different drawings, the same components are represented by the same reference numerals. For the sake of brevity, not all components or parts of the power module according to the present disclosure are shown or labeled in the drawings. In addition, it should be understood that the size, proportional relationship and number of components of the components or parts in the drawings are not intended to limit the present disclosure. In the drawings:

[0024] Figure 1 is a top view schematically showing a power module according to an embodiment of the present disclosure, wherein a package of the power module is removed to show a conductive structure of a substrate and a first component, a second component and an interconnection structure disposed on the substrate;

[0025] Figure 2 The power module is schematically shown along Figure 1 A cross-sectional view along line II in which the package of the power module is shown;

[0026] Figure 3 It is schematically shown Figure 1 a bottom perspective view of the first component;

[0027] Figure 4 yes Figure 3 a bottom view of the first component; and

[0028] Figure 5 It is schematically shown Figure 1 a bottom perspective view of the second component;

[0029] Figure 6 yes Figure 5 a bottom view of the second component; and

[0030] Figure 7 It is schematically shown Figure 1 A top view of the substrate. DETAILED DESCRIPTION

[0031] Some embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings. It should be understood that these embodiments are not intended to limit the present disclosure in any way. In addition, the features in the embodiments of the present disclosure may be combined with each other without conflict.

[0032] Figure 1 and Figure 2 A power module 1 according to an embodiment of the present disclosure is schematically shown. Figure 1 is a schematic top view of the power module 1, and Figure 2 is the power module 1 along Figure 1 Schematic cross-sectional view along line II in FIG.

[0033] The power module 1 may be configured to implement power conditioning and / or conversion. For example, the power module 1 may be used in an inverter such as an automotive inverter to implement conversion of direct current to alternating current. It should be understood that the specific application of the power module 1 is not limited thereto.

[0034] like Figure 1 and Figure 2 As shown, the power module 1 includes a substrate 10, a first component 20 and a second component 30 mounted on the substrate 10, and a second package body 40 disposed on the substrate 10 to package the first component 20 and the second component 30. Figure 1 The second package body 40 is removed in the figure to show the conductive structures 11 and 12 of the substrate 10 and the first component 20, the second component 30 and the interconnection structure 60 disposed on the substrate 10. These components and structures will be described in detail below.

[0035] Figure 7 The substrate 10 is schematically shown in a top view. The substrate 10 is a part of the power module 1 and is used to provide support and electrical connection for various electrical components of the power module 1. Exemplarily, the substrate 10 may be a ceramic-based copper-clad laminate. Figure 2 As shown, the substrate 10 may include a ceramic core 10a and a first copper layer 10b and a second copper layer 10c respectively disposed on a first surface 10a1 and a second surface 10a2 opposite to each other of the ceramic core 10a. The first copper layer 10b may form a plurality of first conductive structures 11 on the first surface 10a1. In other words, the substrate 10 may include a plurality of first conductive structures 11 formed by the first copper layer 10b.

[0036] Please continue to refer to Figure 2 , the first component 20 is mounted on the substrate 10 to be supported by the substrate 10. In addition, as will be described in detail below, the first component 20 is electrically connected to the plurality of first conductive structures 11 of the substrate 10. Figure 3 and Figure 4 A first component 20 is further shown.

[0037] like Figures 2 to 4 As shown, the first component 20 includes a first bare chip 21, a plurality of first conductive elements 23, and a first package 25 encapsulating the first bare chip 21 and the plurality of first conductive elements 23. The first bare chip 21 is located in the first package 25. That is, the chip attachment layer and the bonding layer of the first bare chip 21 are located in the first package 25. Each first conductive element 23 is configured to electrically connect the first bare chip 21 to the corresponding first conductive structure 11 of the substrate 10. Specifically, each first conductive element 23 is electrically connected to the first bare chip 21 in the first package 25, and a portion of each first conductive element 23 is exposed from the first package 25 and connected to the corresponding first conductive structure 11 of the substrate 10. That is, the first bare chip 21 is encapsulated in the first package 25, and indirectly establishes an electrical connection with the substrate 10 via the plurality of first conductive elements 23. The second package 40 is disposed on the substrate 10 and at least covers the connection portions of the first conductive elements 23 and the corresponding first conductive structures 11.

[0038] Compared to the conventional power module configuration as described in the background art in which a bare chip is directly soldered on a substrate, the configuration of the power module 1 according to the present disclosure can shorten the R&D cycle of the power module and reduce its R&D and production costs, and can improve the reliability of the power module.

[0039] Specifically, on the one hand, since the first bare chip 21 is encapsulated in the first package body 25 and indirectly establishes an electrical connection with the substrate 10 via a plurality of first conductive elements 23, this configuration can provide protection for the first bare chip 21, especially its chip attachment layer and bonding layer. The plurality of first conductive elements 23 act as "interposers" to provide electrical connection between the first bare chip 21 located in the first package body 25 and the substrate 10 located outside the first package body 25. In the research and development stage of the power module, it is only necessary to design the plurality of first conductive structures 11 of the substrate 10 to match the plurality of first conductive elements 23 of the first component 20, so as to achieve a reliable electrical connection between the first bare chip 21 and the substrate 10. This configuration allows the electrical connection between the first bare chip 21 and the substrate 10 to be standardized, that is, to form a standardized interface. In this case, even if the design of the power module is modified in the research and development stage, it is not necessary to retest this standardized interface to verify its reliability. This enables the verification process of the power module to be significantly shortened, thereby shortening the research and development cycle of the power module and reducing its research and development cost. This standardized configuration can be widely applied to various power modules. On the other hand, during the production stage of the power module 1, since the first bare chip 21 and the plurality of first conductive elements 23 are packaged as a separate discrete component (i.e., the first component 20), a more comprehensive reliability test can be performed on the first bare chip 21 before the first component 20 is mounted on the substrate 10 (for example, a withstand voltage test under high voltage can be performed, which cannot be performed when the first bare chip 21 is exposed to air or an environment without protective gas). This makes it possible to eliminate all unqualified first components 20 as much as possible before the first component 20 is integrated into the power module 1, thereby significantly improving the yield of the power module 1, thereby reducing the production cost of the power module 1. In addition, encapsulating the first bare chip 21 in the first package body 25 can provide protection for the first bare chip 21 when the first bare chip 21 is mounted on the substrate 10, thereby improving the yield of the power module 1. The second package body 40 can provide protection for the connection between the first conductive element 23 and the corresponding first conductive structure 11, thereby improving the yield and reliability of the power module 1.

[0040] The first conductive element 23 is formed of a conductive material. The conductive material suitable for manufacturing the first conductive element 23 may be, for example, copper or a copper alloy. The first package 25 and the second package 40 are respectively formed of packaging materials. The packaging material suitable for forming the package may be, for example, silicone gel or epoxy resin. The first package 25 and the second package 40 may be formed of the same or different materials.

[0041] like Figure 3 and Figure 4As best shown, the plurality of first conductive elements 23 of the first component 20 may include a plurality of first gate conductive elements 23G, a plurality of first source conductive elements 23S, and a plurality of first drain conductive elements 23D. In the first package body 25, the plurality of first gate conductive elements 23G are respectively electrically connected to corresponding gates (not shown) of the first bare chip 21, the plurality of first source conductive elements 23S are respectively electrically connected to corresponding sources (not shown) of the first bare chip 21, and the plurality of first drain conductive elements 23D are respectively electrically connected to corresponding drains (not shown) of the first bare chip 21. Figure 2 As shown, the first bare chip 21 may include a top surface 21a and a bottom surface 21b opposite to each other. The first bare chip 21 is arranged in an orientation with the bottom surface 21b facing the first surface 10a1 of the substrate 10. The bonding wire 27 may extend between the first source conductive element 23S and the top surface 21a of the first bare chip 21 to electrically connect the first source conductive element 23S to the corresponding source of the first bare chip 21. The bonding wire 27 may be connected between the first source conductive element 23S and the corresponding source of the first bare chip 21 by a wire bonding process. Please continue to refer to Figure 2 , the first drain conductive element 23D may extend in the first package body 25 to contact the bottom surface 21b of the first bare chip 21 to be electrically connected to the corresponding drain of the first bare chip 21. Figure 2 Only one first source conductive element 23S and one first drain conductive element 23D are shown as being connected to the first bare chip 21, but it should be understood that other first source conductive elements 23S and other first drain conductive elements 23D can be electrically connected to the first bare chip 21 in a similar manner. In addition, it is conceivable that the first gate conductive element 23G can be electrically connected to the corresponding gate of the first bare chip 21 in a manner similar to the first source conductive element 23S.

[0042] It should be understood that the first gate conductive element 23G, the first source conductive element 23S and the first drain conductive element 23D are electrically connected to the corresponding gate, source and drain of the first bare chip 21 in a manner not limited to the described manner. It should also be understood that the orientation of the first bare chip 21 is not limited to the orientation shown in the figure.

[0043] Please continue to refer to Figure 3 and Figure 4 A portion of each of the plurality of first gate conductive elements 23G, the plurality of first source conductive elements 23S, and the plurality of first drain conductive elements 23D is exposed from the first package body 25 for connection to the corresponding first conductive structure 11 of the substrate 10 .

[0044] like Figure 1 and Figure 7As shown, the plurality of first conductive structures 11 of the substrate 10 may include a plurality of first gate conductive structures 11G, a plurality of first source conductive structures 11S, and a plurality of first drain conductive structures 11D. The plurality of first gate conductive structures 11G, the plurality of first source conductive structures 11S, and the plurality of first drain conductive structures 11D may be arranged in a pattern that corresponds to a pattern of portions of the plurality of first gate conductive elements 23G, the plurality of first source conductive elements 23S, and the plurality of first drain conductive elements 23D exposed from the first package body 25, thereby allowing electrical connections to be established between the corresponding conductive structures and conductive elements. For example, as Figure 1 , Figure 3 , Figure 4 and Figure 7 As shown, the plurality of first gate conductive structures 11G, the plurality of first source conductive structures 11S and the plurality of first drain conductive structures 11D are arranged in a pattern corresponding one-to-one to the plurality of first gate conductive elements 23G, the plurality of first source conductive elements 23S and the plurality of first drain conductive elements 23D.

[0045] For the second component 30, a portion of each first gate conductive element 23G is exposed from the first package body 25 and connected to the corresponding first gate conductive structure 11G, a portion of each first source conductive element 23S is exposed from the first package body 25 and connected to the corresponding first source conductive structure 11S, and a portion of each first drain conductive element 23D is exposed from the first package body 25 and connected to the corresponding first drain conductive structure 11D. Through this configuration, the gate, source, and drain of the first bare chip 21 can be electrically connected to the first gate conductive structure 11G, the first source conductive structure 11S, and the first drain conductive structure 11D of the substrate 10 via the first gate conductive element 23G, the first source conductive element 23S, and the first drain conductive element 23D, respectively. That is, the gate, source, and drain of the first bare chip 21 are all electrically connected to the corresponding first conductive structure 11 of the substrate 10 through the first conductive element 23. This configuration can provide protection for the first bare chip 21, especially its chip attachment layer and bonding layer. In addition, this configuration allows standardization of the electrical connection between the first bare chip 21 and the substrate 10, that is, forming a standardized interface. As described above, this configuration can significantly shorten the verification process of the power module, thereby shortening the development cycle of the power module and reducing its development cost.

[0046] like Figure 3 and Figure 4 As shown, the first package body 25 includes a bottom surface 25a and a top surface 25b opposite to each other. When the first component 20 is mounted on the substrate 10, the bottom surface 25a of the first package body 25 faces the first surface 10a1 of the ceramic core 10a of the substrate 10, and the top surface 25b faces away from the first surface 10a1.

[0047] In some embodiments, Figures 2 to 4 As shown, each first conductive element 23 of the first component 20 (i.e., the first gate conductive element 23G, the first source conductive element 23S, and the first drain conductive element 23D) may be configured in the form of a first conductive pad exposed at the bottom surface 25a of the first package body 25. Figure 1 , Figure 2 and Figure 7 As shown, each first conductive structure 11 of the substrate 10 (i.e., the first gate conductive structure 11G, the first source conductive structure 11S, and the first drain conductive structure 11D) can be configured in the form of a first mating conductive pad. The first mating conductive pad is located on the first surface 10a1 of the ceramic core 10a of the substrate 10. Each first conductive pad of the first component 20 can be welded to the corresponding first mating conductive pad of the substrate 10. Such welding can be achieved by any suitable surface mounting technology (Surface Mounting Technology, SMT). For example, as Figure 2 As shown, this welding can be achieved by a reflow soldering process. Specifically, solder 50 is applied to the first mating conductive pad (i.e., the first conductive structure 11) of the substrate 10, and then the first component 20 is placed on the first surface 10a1 of the substrate 10, so that each first conductive pad (i.e., the first conductive element 23) of the first component 20 is aligned with the corresponding first mating conductive pad of the substrate 10. Subsequently, the substrate 10 and the first component 20 can be placed together in a reflow furnace and heated. The solder 50 melts to adhere to the first conductive pad, while the solder 50 remains adhered to the first mating conductive pad. After the solder 50 cools, the first conductive pad is connected and fixed to the first mating conductive pad by the solder 50. In this way, the first conductive pad is mechanically and electrically connected to the first mating conductive pad by the solder 50. It should be understood that the present disclosure is not limited to this. The first conductive pad of the first component 20 can be soldered to the corresponding first mating conductive pad of the substrate 10 by any suitable process.

[0048] like Figure 3 and Figure 4As shown, the bottom surface 25a of the first package body 25 may include four side edges (not shown), and a plurality of first conductive elements 23 may be arranged in four rows, each of which may be arranged adjacent to a corresponding one of the four side edges of the bottom surface 25a. The first conductive elements 23 in each row may be arranged along the row direction and spaced apart from each other. Each row may include at least one (one in the figure) first gate conductive element 23G, at least one (three in the figure) first source conductive element 23S, and at least one (three in the figure) first drain conductive element 23D. This configuration enables the first conductive elements 23 for establishing electrical connection to be arranged at the four side edges of the bottom surface 25a of the first package body 25. This can improve the arrangement density of the conductive elements on the first component 20. In addition, this can improve the flexibility of the electrical connection of the first component 20 to the substrate 10.

[0049] In one of these embodiments, the first component 20 may have a QFN (Quad Flat No-lead) packaging configuration. This packaging configuration can increase the arrangement density of the conductive elements on the first component 20. It should be understood that the second component 30 may also adopt any other suitable packaging configuration.

[0050] In some embodiments, Figure 3 and Figure 4 As shown, the shape of the bottom surface 25a of the first package body 25 can be a square. In this case, for the four rows of the first conductive elements 23, the configuration of the first gate conductive elements 23G, the first source conductive elements 23S and the first drain conductive elements 23D is 90 degrees rotationally symmetrical about the center of the bottom surface 25a (i.e., the center of the square). In other words, the number and position of the first gate conductive elements 23G, the first source conductive elements 23S and the first drain conductive elements 23D in the four rows are 90 degrees rotationally symmetrical about the center of the bottom surface 25a. This configuration can further improve the flexibility of the electrical connection of the first component 20 to the substrate 10.

[0051] In other partial embodiments, the shape of the bottom surface 25a of the first package body 25 may be a rectangle. That is, the bottom surface 25a may include two long sides opposite to each other and two short sides opposite to each other. For two rows of the four rows of the first conductive elements 23 disposed adjacent to the two long sides of the bottom surface 25a, the configuration of the first gate conductive elements 23G, the first source conductive elements 23S, and the first drain conductive elements 23D is 180 degrees rotationally symmetrical about the center of the bottom surface 25a (i.e., the center of the rectangle), and for the other two rows of the four rows of the first conductive elements 23 disposed adjacent to the two short sides of the bottom surface 25a, the configuration of the first gate conductive elements 23G, the first source conductive elements 23S, and the first drain conductive elements 23D is also 180 degrees rotationally symmetrical about the center of the bottom surface 25a. This configuration can further improve the flexibility of the electrical connection of the first component 20 to the substrate 10.

[0052] In some embodiments, Figures 2 to 4 As shown, the first component 20 may include a central conductive pad 23C. The central conductive pad 23C may extend from the first bare chip 21 to the bottom surface 25a of the first package body 25 and be exposed at a central area of ​​the bottom surface 25a. Figure 2 and Figure 7 As shown, the substrate 10 may include a second mating conductive pad 11C. The second mating conductive pad 11C is also formed by the first copper layer 10b. When the first component 20 is mounted on the substrate 10, the central conductive pad 23C of the first component 20 is soldered to the second mating conductive pad 11C of the substrate 10. For example, Figure 2 As schematically shown in FIG. 5 , the central conductive pad 23C can be connected and fixed to the second mating conductive pad 11C by solder 50. This can be achieved by a reflow process as described above. It should be understood that the present disclosure is not limited thereto, and the central conductive pad 23C can be soldered to the second mating conductive pad 11C by any suitable process.

[0053] The central conductive pad 23C can establish a heat conduction path between the first component 20 and the substrate 10 to thermally couple the first component 20 to the substrate 10. This can enhance the heat dissipation capability of the first component 20. Preferably, the central conductive pad 23C can be aligned with the heat generating portion of the first bare chip 21. The ceramic core 10a of the substrate 10 can facilitate heat dissipation to the outside of the power module 1. Additionally or alternatively, the central conductive pad 23C can electrically connect the corresponding drain of the first bare chip 21 to the substrate 10, thereby further enhancing the electrical connection between the first bare chip 21 and the substrate 10.

[0054] In some embodiments, Figure 3 and Figure 4As shown, the portion of the central conductive pad 23C exposed at the bottom surface 25a can be larger than the portion of the first conductive element 23 in the form of a first conductive pad exposed at the bottom surface 25a. The central conductive pad 23C can be a single pad. In other embodiments, the central conductive pad 23C can be a plurality of separate pads.

[0055] like Figure 1 , Figure 2 and Figure 7 As shown, the first copper layer 10b may also form a plurality of second conductive structures 12 on the first surface 10a1. The second component 30 is mounted on the substrate 10 to be supported by the substrate 10 and is electrically connected to the plurality of second conductive structures 12 of the substrate 10. Figure 5 and Figure 6 A second component 30 is further shown.

[0056] like Figures 1 to 6 As shown, the configuration of the second component 30 is substantially the same as that of the first component 20. The second component 30 includes a second bare chip 31, a plurality of second conductive elements 33 each electrically connected to the second bare chip 31, and a third package body 35 encapsulating the second bare chip 31 and the plurality of second conductive elements 33. The second bare chip 31 is disposed in the third package body 35. That is, the chip attachment layer and the bonding layer of the second bare chip 31 are located in the third package body 35. Each second conductive element 33 is configured to electrically connect the second bare chip 31 to the corresponding second conductive structure 12 of the substrate 10. The specific structure of the plurality of second conductive elements 33 of the second component 30 and the connection method thereof with the second bare chip 31 and the second conductive structure 12 of the substrate 10 are similar to the specific structure of the plurality of first conductive elements 11 of the first component 20 and the connection method thereof with the first bare chip 21 and the first conductive element 11 of the substrate 10 described above. For the sake of brevity, these repeated parts will not be described in detail here.

[0057] This configuration of the second component 30 enables the second bare chip 31 to be electrically connected to the substrate 10 in a similar manner to the first bare chip 21 and then integrated into the power module 1. This can further shorten the development cycle of the power module 1 and reduce its development and production costs.

[0058] like Figure 2 As best shown, the second package body 40 can also cover the connection parts between the second conductive elements 33 and the corresponding second conductive structures 12. The second package body 40 can provide protection for the connection parts between the second conductive elements 33 and the corresponding second conductive structures 12, thereby improving the reliability of the power module 1.

[0059] In some embodiments, Figure 1 and Figure 2As shown, the power module 1 may further include a plurality of interconnect structures 60. Each interconnect structure 60 may connect a corresponding first conductive structure 11 (eg, Figure 1 and Figure 2 The first drain conductive structure 11D) and the corresponding second conductive structure 12 (for example, Figure 1 and Figure 2 The first bare chip 21 and the second bare chip 31 are electrically connected to the second source conductive structure 12S in the interconnect structure 60 to establish an electrical connection between the first bare chip 21 and the second bare chip 31. Specifically, since the interconnect structure 60 electrically connects the corresponding first conductive structure 11 with the corresponding second conductive structure 12, and since the first bare chip 21 is electrically connected to the first conductive structure 11 via the first conductive element 23, and the second bare chip 31 is electrically connected to the second conductive structure 12 via the second conductive element 33, a conductive path can be established between the first bare chip 21 and the second bare chip 31, thereby electrically connecting the first bare chip 21 and the second bare chip 31. In this way, the first component 20 and the second component 30 can be electrically connected together to form a circuit or a part of a circuit. The first bare chip 21 and the second bare chip 31 can be any suitable type of power bare chip. For example, each of the first bare chip 21 and the second bare chip 31 can be a MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor) bare chip or an IGBT (Insulated GateBipolar Transistor, Insulated Gate Bipolar Transistor) bare chip. The circuit may be, for example, a bridge circuit such as a half-bridge circuit, a drive circuit, a protection circuit, a filter circuit.

[0060] In some embodiments, the second package body 40 may also cover the connection portion between the interconnect structure 60 and the corresponding first conductive structure 11 and the connection portion between the interconnect structure 60 and the corresponding second conductive structure 12. In one of these embodiments, the second package body 40 may also cover the entire interconnect structure 60. These configurations can improve the reliability of the power module 1.

[0061] The second conductive element 33 is formed of a conductive material. The conductive material suitable for manufacturing the second conductive element 33 may be, for example, copper or a copper alloy. The third package body 35 is formed of a packaging material. The packaging material suitable for forming the third package body 35 may be, for example, silicone gel or epoxy resin. The first package body 25, the second package body 40, and the third package body 35 may be formed of the same or different materials.

[0062] Similar to the first component 20, Figure 5 and Figure 6As shown, the plurality of second conductive elements 33 of the second component 30 may also include a plurality of second gate conductive elements 33G, a plurality of second source conductive elements 33S, and a plurality of second drain conductive elements 33D. The specific structure of the second gate conductive element 33G, the second source conductive element 33S, and the second drain conductive element 33D of the second component 30 and the electrical connection method thereof with the second bare chip 31 are similar to the specific structure of the first gate conductive element 23G, the first source conductive element 23S, and the first drain conductive element 23D of the first component 20 described above and the electrical connection method thereof with the first bare chip 21. For the sake of brevity, these repeated parts will not be described again here.

[0063] like Figure 1 and Figure 7 As shown, the multiple second conductive structures 12 of the substrate 10 may correspondingly include multiple second gate conductive structures 12G, multiple second source conductive structures 12S, and multiple second drain conductive structures 12D. The multiple second gate conductive structures 12G, multiple second source conductive structures 12S, and multiple second drain conductive structures 12D are arranged in a similar manner to the multiple first gate conductive structures 11G, multiple first source conductive structures 11S, and multiple first drain conductive structures 11D. For the sake of brevity, these repeated parts will not be repeated here. Figure 1 , Figure 2 and Figure 7 Only some of the second gate conductive structures 12G, the second source conductive structures 12S, and the second drain conductive structures 12D of the substrate 10 are marked.

[0064] A portion of each second gate conductive element 33G is exposed from the third package body 35 and connected to the corresponding second gate conductive structure 12G, a portion of each second source conductive element 33S is exposed from the third package body 35 and connected to the corresponding second source conductive structure 12S, and a portion of each second drain conductive element 33D is exposed from the third package body 35 and connected to the corresponding second drain conductive structure 12D. The connection mode of the second gate conductive element 33G and the corresponding second gate conductive structure 12G, the connection mode of the second source conductive element 33S and the corresponding second source conductive structure 12S, and the connection mode of the second drain conductive element 33D and the corresponding second drain conductive structure 12D are similar to the connection mode of the first gate conductive element 23G and the corresponding first gate conductive structure 11G, the connection mode of the first source conductive element 23S and the corresponding first source conductive structure 11S, and the connection mode of the first drain conductive element 23D and the corresponding first drain conductive structure 11D, respectively. For the sake of brevity, these repeated parts will not be repeated here.

[0065] In some embodiments, the interconnect structure 60 may connect the corresponding first drain conductive structure 11D to the corresponding second source conductive structure 12D. Figure 1 and Figure 2 As shown, three interconnect structures 60 connect the corresponding first drain conductive structure 11D to the corresponding second source conductive structure 12D, respectively. This enables at least a portion of the drain of the first bare chip 21 and at least a portion of the source of the second bare chip 31 to be connected in series, so that the first component 20 and the second component 30 can be electrically connected to form a circuit or a part of a circuit. Such a circuit can be, for example, a bridge circuit such as a half-bridge circuit. It should be understood that although in Figure 1 and Figure 2 , three interconnect structures 60 are shown to respectively connect the three first drain conductive structures 11D of the first component 20 to the three second source conductive structures 12D of the second component 30. However, the present application is not limited thereto, and more or fewer interconnect structures 60 may connect the corresponding number of first drain conductive structures 11D of the first component 20 to the corresponding number of second source conductive structures 12D of the second component 30. For example, there may be only one interconnect structure 60. For another example, all the first drain conductive structures 11D of the first component 20 may be connected to the second source conductive structures 12D of the second component 30. In other embodiments, the interconnect structure may interconnect the first conductive structure and the second conductive structure in any suitable configuration according to the application requirements of the power module.

[0066] In some embodiments, Figure 2 and Figure 5 to Figure 6 As shown, similar to the first component 20, each second conductive element 33 of the second component 30 (i.e., the second gate conductive element 33G, the second source conductive element 33S, and the second drain conductive element 33D) can be configured in the form of a conductive pad (also referred to as a "second conductive pad"). The second conductive pad is exposed at the bottom surface 35a of the third package body 35. Figure 1 , Figure 2 and Figure 7 As shown, each second conductive structure 12 (i.e., the second gate conductive structure 12G, the second source conductive structure 12S, and the second drain conductive structure 12D) of the substrate 10 can be configured in the form of a third mating conductive pad. The third mating conductive pad is located on the first surface 10a1 of the ceramic core 10a of the substrate 10 and is also formed by the copper layer 10b.

[0067] Each second conductive pad of the second component 30 can be soldered to a corresponding third mating conductive pad of the substrate 10. Such soldering can be achieved in a manner similar to the above-described method of soldering the first conductive pad to the first mating conductive pad. Figure 2The solder 50 schematically shows the welding between the second conductive pad and the third mating conductive pad. For the sake of brevity, these repeated parts will not be described again.

[0068] In some embodiments, similar to the first component 20, in one of these embodiments, the second component 30 may also have a QFN packaging configuration. This packaging configuration can increase the arrangement density of the conductive elements on the second component 30. It should be understood that the second component 30 may also adopt any other suitable packaging configuration.

[0069] The shape of the bottom surface 35a of the third package body 35 of the second component 30 and the arrangement of the second conductive element 33 at the bottom surface 35a may be similar to the shape of the bottom surface 25a of the first package body 25 and the arrangement of the first conductive element 23 at the bottom surface 25a of the first component 20. For the sake of brevity, these repeated parts will not be repeated here.

[0070] In some embodiments, Figure 1 and Figure 2 As shown, the interconnection structure 60 may be in the form of a bonding wire. The use of a bonding wire can increase the electrical connection density in the power module 1, thereby facilitating the miniaturization of the power module 1. In other embodiments, the interconnection structure 60 may be in the form of a conductive trace disposed on the surface of the substrate 10 (e.g., the first surface 10a1 of the ceramic core 10a). In other embodiments, in the case of a multi-layer substrate, the interconnection structure may also be in the form of a conductive layer disposed in the substrate. In addition, in other embodiments, these three forms of interconnection structures may be used simultaneously. That is, the interconnection structure 60 may include at least one of a bonding wire, a conductive trace disposed on the surface of the substrate, and a conductive layer disposed in the substrate. Through this configuration, the design flexibility of the power module 1 can be improved.

[0071] In some embodiments, Figure 2 and Figure 5 to Figure 6 As shown, similar to the first component 20, the second component 30 may include a central conductive pad 33C. Figure 2 and Figure 7 As shown, the substrate 10 may include a fourth mating conductive pad 12C accordingly. The fourth mating conductive pad 12C may also be formed by the first copper layer 10b. The central conductive pad 33C of the second component 30 may be soldered to the fourth mating conductive pad 12C of the substrate 10. Such soldering may be achieved by the reflow soldering process described above. Figure 2The solder 50 schematically shows the welding of the central conductive pad 33C and the fourth mating conductive pad 12C. The structure and function of the central conductive pad 33C of the second component 30 can be similar to the structure and function of the central conductive pad 23C of the first component 20. For the sake of brevity, these repeated parts will not be repeated here.

[0072] In some embodiments, Figure 2 As shown, the second package body 40 can cover the first component 20, the second component 30, the first conductive structure 11 and the second conductive structure 12 of the substrate 10, and the interconnection structure 60. In other words, the first component 20, the second component 30, the first conductive structure 11 and the second conductive structure 12 of the substrate 10, and the interconnection structure 60 are all wrapped in the second package body 40. The second package body 40 can provide protection for these components and structures, thereby improving the reliability of the power module 1. For example, Figure 1 and Figure 2 As shown, the power module 1 may include a frame 70 configured to enclose a packaging space on the first surface 10a1. The second packaging body 40 fills the packaging space to cover the first component 20, the second component 30, the first conductive structure 11 and the second conductive structure 12 of the substrate 10, and the interconnection structure 60. It should be understood that the formation of the second packaging body 40 is not limited thereto.

[0073] Although not shown in the drawings, it is conceivable that the conductive pins can be connected to the first conductive structure 11 and the second conductive structure 12 on the substrate 10 in the second package body 40, and the conductive pins can extend from the second package body 40 for connection to other electrical components located outside the power module 1, such as a PCB to be mounted with the power module 1. In this way, the first bare chip 21 of the first component 20 and the second bare chip 31 of the second component 30 can be electrically connected to other electrical components located outside the power module 1 through corresponding conductive elements, corresponding conductive structures of the substrate 10, and pins.

[0074] Although it is described above that the substrate 10 is a ceramic copper-clad substrate, it should be understood that the present application is not limited thereto. The substrate 10 may be any other suitable type of substrate, such as a glass substrate, a multi-layer substrate, and the like.

[0075] Although it is described above that the conductive elements of the first component 20 and the second component 30 are in the form of conductive pads, and the matching conductive structure of the substrate 10 is in the form of matching conductive pads, it should be understood that the conductive elements of the first component 20 and the second component 30 may also be in any other suitable form. For example, the conductive elements of the first component 20 and the second component 30 may be in the form of pins. Correspondingly, the matching conductive structure of the substrate 10 may be in the form of conductive through holes. The pins of the first component 20 and the second component 30 may be inserted and soldered in the conductive through holes of the substrate 10.

[0076] Although it is described above that the first component 20 and the second component 30 each have a plurality of gate conductive elements, a plurality of source conductive elements, and a plurality of drain conductive elements, it should be understood that the first component 20 and the second component 30 each may have any suitable number (e.g., one) of gate conductive elements, source conductive elements, and drain conductive elements. The number of corresponding conductive structures of the substrate 10 may be changed accordingly.

[0077] Although it is described above and shown in the drawings that the gate conductive element, source conductive element and drain conductive element of the component are connected to the gate conductive structure, source conductive structure and drain conductive structure of the substrate 10 in a one-to-one correspondence, it should be understood that the present application is not limited thereto. For example, multiple source conductive structures of a component can be connected to the same source conductive structure of the substrate 10. For another example, multiple drain conductive elements of a component can be connected to the same drain conductive structure of the substrate 10.

[0078] Although it is described above that the power module 1 includes a first bare chip 21 packaged in a discrete first component 20 and a second bare chip 31 packaged in a discrete second component 30, it should be understood that the power module 1 may include additional bare chips. The additional bare chips may be electrically connected to the first bare chip 21 and the second bare chip 31 to form a circuit or a part of a circuit. The additional bare chips may be packaged in a discrete component and the component is mounted on the substrate 10, or the additional bare chips may be directly soldered on the substrate 10. It should also be understood that in the power module 1, only one bare chip may be packaged in a discrete component and the component is mounted on the substrate 10, while the other bare chips are directly soldered on the substrate 10. Compared with the traditional power module configuration, this power module configuration can also shorten the R&D cycle of the power module and reduce its R&D and production costs.

[0079] It should also be understood that the terms "first", "second", "third" and "fourth" are only used to distinguish one component or part from another component or part, but these components and parts should not be limited by such terms. The present disclosure is described in detail above in conjunction with specific embodiments. Obviously, the above description and the embodiments shown in the drawings should be understood as exemplary and not to limit the present disclosure.

[0080] It is obvious to those skilled in the art that various changes or modifications may be made to the present disclosure without departing from the spirit of the present disclosure, and these changes or modifications do not depart from the scope of the present disclosure.

Claims

1. A power module (1), characterized in that: The power module (1) comprises: A substrate (10) comprising a plurality of first conductive structures (11); a first component (20) mounted on the substrate (10), the first component (20) comprising a first bare chip (21), a plurality of first conductive elements (23) each electrically connected to the first bare chip (21), and a first package (25) encapsulating the first bare chip (21) and the plurality of first conductive elements (23), wherein a portion of each of the first conductive elements (23) is exposed from the first package (25) and connected to the corresponding first conductive structure (11) of the substrate (10); and A second package (40), the second package (40) is arranged on the substrate (10) and at least covers the connection parts between the plurality of first conductive elements (23) and the corresponding first conductive structures (11).

2. The power module (1) according to claim 1, characterized in that: The plurality of first conductive elements (23) of the first component (20) include one or more first gate conductive elements (23G), one or more first source conductive elements (23S) and one or more first drain conductive elements (23D); The plurality of first conductive structures (11) of the substrate (10) include one or more first gate conductive structures (11G), one or more first source conductive structures (11S) and one or more first drain conductive structures (11D); as well as A portion of each of the first gate conductive elements (23G) is exposed from the first package body (25) and connected to the corresponding first gate conductive structure (11G), a portion of each of the first source conductive elements (23S) is exposed from the first package body (25) and connected to the corresponding first source conductive structure (11S), and a portion of each of the first drain conductive elements (23D) is exposed from the first package body (25) and connected to the corresponding first drain conductive structure (11D).

3. The power module (1) according to claim 2, characterized in that: The first package body (25) includes a first bottom surface (25a) facing the substrate (10), and each of the first conductive elements (23) of the first component (20) is configured in the form of a first conductive pad, which is exposed at the first bottom surface (25a); Each of the first conductive structures (11) of the substrate (10) is configured to be in the form of a first mating conductive pad; and Each of the first conductive pads is soldered to a corresponding first mating conductive pad.

4. The power module (1) according to claim 3, characterized in that: The first bottom surface (25a) of the first package body (25) includes four side edges; The plurality of first conductive elements (23) are arranged in four rows, each of the four rows is disposed adjacent to a corresponding one of the four sides, and the first conductive elements (23) in each row include a first gate conductive element (23G), a first source conductive element (23S) and a first drain conductive element (23D); and in: The first bottom surface (25a) of the first package body (25) is in a square shape, and for the four rows, the first gate conductive element (23G), the first source conductive element (23S) and the first drain conductive element (23D) are arranged to be rotationally symmetrical at 90 degrees about the center of the first bottom surface (25a); or The first bottom surface (25a) of the first package body (25) is in the shape of a rectangle, and for two of the four rows which are arranged at two opposite long sides adjacent to the first bottom surface (25a), the configurations of the first gate conductive element (23G), the first source conductive element (23S) and the first drain conductive element (23D) are rotationally symmetrical 180 degrees about the center of the first bottom surface (25a), and for the other two of the four rows which are arranged at two opposite short sides adjacent to the first bottom surface (25a), the configurations of the first gate conductive element (23G), the first source conductive element (23S) and the first drain conductive element (23D) are rotationally symmetrical 180 degrees about the center of the first bottom surface (25a).

5. The power module (1) according to claim 3, characterized in that: The first component (20) further includes a central conductive pad (23C) extending from the first bare chip (21) to the first bottom surface (25a) and exposed at a central area of ​​the first bottom surface (25a); The substrate (10) further includes a second mating conductive pad (12C); and The central conductive pad (23C) is soldered to the second mating conductive pad (12C).

6. The power module (1) according to any one of claims 1 to 5, characterized in that: The substrate (10) further comprises a plurality of second conductive structures (12); and The power module (1) comprises: a second component (30) mounted on the substrate (10), the second component (30) comprising a second bare chip (31), a plurality of second conductive elements (33) each electrically connected to the second bare chip (31), and a third package (35) encapsulating the second bare chip (31) and the plurality of second conductive elements (33), wherein a portion of each second conductive element (33) is exposed from the third package (35) and connected to the corresponding second conductive structure (12) of the substrate (10); and At least one interconnect structure (60), each of the interconnect structures (60) electrically connects the corresponding first conductive structure (11) with the corresponding second conductive structure (12) to establish an electrical connection between the first bare chip (21) and the second bare chip (31).

7. The power module (1) according to claim 6, characterized in that: The plurality of second conductive elements (33) of the second component (30) include one or more second gate conductive elements (33G), one or more second source conductive elements (33S) and one or more second drain conductive elements (33D); The plurality of second conductive structures (12) of the substrate (10) include one or more second gate conductive structures (12G), one or more second source conductive structures (12S) and one or more second drain conductive structures (12D); A portion of each second gate conductive element (33G) is exposed from the third package body (35) and connected to the corresponding second gate conductive structure (12G), a portion of each second source conductive element (33S) is exposed from the third package body (35) and connected to the corresponding second source conductive structure (12S), and a portion of each second drain conductive element (33D) is exposed from the third package body (35) and connected to the corresponding second drain conductive structure (12D); The plurality of first conductive elements (23) of the first component (20) include one or more first drain conductive elements (23D), the plurality of first conductive structures (11) of the substrate (10) include one or more first drain conductive structures (11D), a portion of each of the first drain conductive elements (23D) is exposed from the first package body (25) and connected to the corresponding first drain conductive structure (11D); as well as Each of the interconnect structures (60) electrically connects the corresponding first drain conductive structure (11D) with the corresponding second source conductive structure (12S).

8. The power module (1) according to claim 7, characterized in that: The third package body (35) includes a second bottom surface (35a) facing the substrate (10), and each of the second conductive elements (33) of the second component (30) is configured as a second conductive pad, and the second conductive pad is exposed at the second bottom surface (35a); Each of the second conductive structures (12) of the substrate (10) is configured as a third mating conductive pad; Each of the second conductive pads is soldered to a corresponding third mating conductive pad; and The at least one interconnect structure (60) includes at least one of a bonding wire, a conductive trace disposed at a surface of the substrate (10), and a conductive layer disposed in the substrate (10).

9. The power module (1) according to claim 7, characterized in that: The first component (20) and the second component (30) are electrically connected by the at least one interconnect structure (60) to form a part of a bridge circuit.

10. The power module (1) according to claim 6, characterized in that: The second package body (40) covers the first component (20), the second component (30), the plurality of first conductive structures (11), the plurality of second conductive structures (12) and the at least one interconnect structure (60); and / or The first component (20) has a QFN package configuration; and / or The second component (30) has a QFN package configuration; and / or The first bare chip (21) is a MOSFET bare chip or an IGBT bare chip; and / or The second bare chip (31) is a MOSFET bare chip or an IGBT bare chip; and / or The substrate (10) is a ceramic-based copper-clad laminate, and the plurality of first conductive structures (11) and the plurality of second conductive structures (12) are formed by a same copper layer of the substrate (10).

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