High-speed signal line wiring structure for chip packaging substrate and packaging substrate

Abstract

The utility model provides a high-speed signal line wiring structure for a chip packaging substrate and the packaging substrate, and the wiring structure comprises a first layer structure located in the packaging substrate, the first layer structure is a metal layer and comprises a hollow region located above a solder ball, and the part, in the hollow region, of the metal layer of the first layer structure is removed; the first via hole is located between the first-layer structure and the second-layer structure, the second via hole is located between the first-layer structure and the third-layer structure, the second-layer structure is located above the first-layer structure, the third-layer structure is located below the first-layer structure, and the solder balls are arranged on the third-layer structure; the intersecting parts of the two via holes and the first-layer structure are located in the hollowed-out area; and the connecting structure is positioned between the two via holes, and the high-speed signal line positioned on the second layer structure is connected to the solder ball through the first via hole, the connecting structure and the second via hole. According to the invention, the wiring mode between the high-speed signal line and the solder ball can be improved, and the impedance drop of the high-speed signal line can be compensated.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a high-speed signal line wiring structure for a chip packaging substrate and a packaging substrate. Background Art

[0002] Figure 1A The structure of the package substrate is shown. The package substrate is a bridge between the chip and the PCB (Printed Circuit Board), providing electrical connection between the chip and the PCB. The package substrate includes, for example, single-layer, double-layer and multi-layer structures. In order to electrically connect the chip to the PCB, the PAD (connection point or pad on the chip) on the chip needs to be connected to the solder ball 13 of the package substrate through a trace. Connecting the PAD on the chip to the solder ball 13 requires the trace to cross the multi-layer structure of the package substrate.

[0003] Figure 1B The hardware structure arranged on the package substrate is shown. Figure 1A and Figure 1B As shown, the package substrate includes multiple layers. Vias 11 are provided on each layer of the package substrate so that the traces 12 cross the layers through the vias 11. The package substrate includes a core layer 15 and a dielectric layer 16. The vias 11 provided on the dielectric layer 16 are laser holes 161, and the vias 11 provided on the core layer 15 are mechanical holes 151. The BGA (Ball Grid Array, solder ball array package) solder ball area of ​​the package substrate includes solder balls 13 and solder ball pads 14, and the via area includes vias 11 and via pads.

[0004] Parasitic inductance (inductive) or parasitic capacitance (capacitive) effects are present in different areas of the package substrate. As for the capacitive effect, the capacitance distribution is uneven when the trace passes through the via, thus generating a capacitive area. The instantaneous impedance of the trace in the inductive effect area and the capacitive effect area is as follows:

[0005] 1. If the capacitor is located at the load, the transient current at the capacitor is: The transient impedance at the capacitor is: For a certain area, the greater the capacitance, the greater the impedance drop; for the same area, the higher the signal rate, the greater the impedance drop.

[0006] 2. The transient impedance of the inductive load is: If the rising edge of the signal is linear, the impedance of the inductive load is inversely proportional to the rising edge; the inductive compensation is expressed as: R, L, G, and C represent resistance, inductance, conductance, and capacitance per unit length, respectively. Usually, R and G are much smaller than the other terms and are thus neglected. Utility Model Content

[0007] For the capacitive area, the higher the signal rate of the routing transmission, the greater the impedance drop. For the BGA solder ball area, there is a relatively large parasitic capacitance effect. When the routing is a high-speed signal line, the impedance will show a large drop. Among them, the high-speed signal line is a signal line with a transmission rate of several hundred megabits or even higher, such as the DQ (data signal) / DQS (data selection signal) of the DDR (Double Data Rate) protocol, the DQ / DQS of the ONFI (Open NAND Flash Interface) protocol, Serdes, Dielink (inter-chip high-speed interconnection) and other signal lines. The DQ signal lines of the DDR protocol and the ONFI protocol include multiple parallel high-speed signal lines.

[0008] For example, Figure 2 The wiring method of the package substrate in the prior art is shown. Figure 2 In the embodiment, the package substrate includes 6 layers (e.g., the first layer 101, the second layer 102, the third layer 103, the fourth layer 104, the fifth layer 105, and the sixth layer 106, in order from top to bottom). For example, the solder ball 13 is connected to the high-speed signal line 122. In order to connect the high-speed signal line 122 to the solder ball 13, a via 11 is provided in each layer, and the high-speed signal line 122 is connected from the first layer 101 to the sixth layer 106 and connected to the solder ball 13 through the via 11. Among them, the high-speed signal line 122 is led from the fifth layer 105 to the sixth layer 106 through a via 11 in the fifth layer 105. Based on the above, there is a relatively large parasitic capacitance effect in the BGA solder ball area. When the routing is a high-speed signal line, the impedance will show a large drop when transmitting a high-speed signal. In addition, the space between the layers of the package substrate is limited, and it is difficult to set electronic components such as resistors, capacitors, and inductors to compensate for the impedance drop.

[0009] The embodiment of the present application provides a solution to the problem that high-speed signal lines may exhibit a large impedance drop in the BGA solder ball area. By improving the routing method between the high-speed signal lines and their corresponding solder balls, the impedance drop of the high-speed signal lines in the BGA solder ball area is compensated.

[0010] In a first aspect, an embodiment of the present application provides a high-speed signal line wiring structure for a chip packaging substrate, comprising:

[0011] A first layer structure located in the package substrate, the first layer structure is a metal layer, the first layer structure includes a hollow area located above the solder ball, and a portion of the metal layer of the first layer structure in the hollow area is removed;

[0012] a first via hole and a second via hole, wherein the first via hole is located between the first layer structure and the second layer structure, the second via hole is located between the first layer structure and the third layer structure, the second layer structure is located above the first layer structure, the third layer structure is located below the first layer structure, and the solder ball is arranged on the third layer structure; the intersection of the first via hole and the second via hole with the first layer structure is located in the hollowed-out area, so that the first via hole and the second via hole are not in contact with the metal layer of the first layer structure;

[0013] a connecting structure between the first via hole and the second via hole; and

[0014] The high-speed signal line located in the second layer structure is connected to the solder ball through the first via, the connection structure and the second via.

[0015] Optionally, a projection of the solder ball onto the first layer structure in a direction perpendicular to the first layer structure is located within the hollowed-out region, and both the first via hole and the second via hole are located directly above the solder ball.

[0016] Optionally, the first via is a first hollow structure formed based on a metal structure, allowing the high-speed signal line to pass from the second layer structure to the first layer structure; the second via is a second hollow structure formed based on a metal structure, allowing the high-speed signal line to pass from the first layer structure to the third layer structure.

[0017] Optionally, one end of the connection structure is connected to the via plate of the first via hole in the hollow area, and the other end is connected to the via plate of the second via hole in the hollow area.

[0018] Optionally, the connection structure is an arc-shaped conductive wire connecting the first via hole and the second via hole;

[0019] The arc-shaped conductive line compensates for the impedance drop of the high-speed signal line in the solder ball area.

[0020] Optionally, the first via hole and the second via hole are in contact, and the contacted position forms a first connecting line as a resistor connected in series to the high-speed signal line;

[0021] The impedance provided by the first connecting line compensates for the impedance drop of the high-speed signal line in the solder ball area.

[0022] Optionally, the first via hole and the second via hole are connected via a non-arc second connecting line, and the second connecting line is a resistor connected in series to the high-speed signal line;

[0023] The impedance provided by the second connecting line compensates for the impedance drop of the high-speed signal line in the solder ball area.

[0024] Optionally, the first layer structure is a power supply layer or a ground layer in the packaging substrate;

[0025] or,

[0026] The first layer structure is a layer structure added in the packaging substrate and specifically used for compensating for impedance drop.

[0027] In a second aspect, an embodiment of the present application provides a packaging substrate, comprising the high-speed signal line wiring structure for a chip packaging substrate described in the first aspect above.

[0028] According to an embodiment of the present application, a metal layer is selected as the first layer structure from among multiple layer structures of a packaging substrate, a hollowed-out area is set on the first layer structure opposite to the position of the solder ball, a first via is set between the first layer structure and the second layer structure, and a second via is set between the first layer structure and the third layer structure on which the solder ball is set, so that the part where the first via and the second via intersect with the first layer structure is located in the hollowed-out area and does not contact the metal layer of the first layer structure, and the first via and the second via are connected by a connecting structure, so that the high-speed signal line located in the second layer structure can be connected to the solder ball through the first via, the connecting structure and the second via, thereby improving the routing method between the high-speed signal line and its corresponding solder ball, and compensating for the impedance drop of the high-speed signal line in the BGA solder ball area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A The structure of the package substrate is shown;

[0030] Figure 1B The hardware structure arranged on the package substrate is shown;

[0031] Figure 2 The wiring method of the package substrate in the prior art is demonstrated;

[0032] Figure 3A A schematic diagram showing a routing method between a high-speed signal line and a solder ball provided in an embodiment of the present application is shown;

[0033] Figure 3B Shown Figure 3A A stereoscopic view of the corresponding reference layer;

[0034] Figure 3C Shown Figure 3B A top view of the corresponding reference layer;

[0035] Figure 4A A schematic diagram showing a routing method between a high-speed signal line and a solder ball provided in another embodiment of the present application is shown;

[0036] Figure 4B Shown Figure 4A A stereoscopic view of the corresponding reference layer;

[0037] Figure 4C Shown Figure 4B A top view of the corresponding reference layer;

[0038] Figure 5A A schematic diagram showing a routing method between a high-speed signal line and a solder ball provided in yet another embodiment of the present application is shown;

[0039] Figure 5B Shown Figure 5A A stereoscopic view of the corresponding reference layer;

[0040] Figure 5C Shown Figure 5B A top view of the corresponding reference layer;

[0041] Figure 6 This is a comparison chart before and after impedance compensation of the BGA solder ball area by using the solution of laying arc-shaped wires between vias;

[0042] Figure 7 This is a comparison diagram before and after impedance compensation of the BGA solder ball area using a solution that forms non-arc connecting lines between vias. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] Figure 3A A schematic diagram of a routing method between a high-speed signal line and a solder ball provided in an embodiment of the present application is shown.

[0045] In the routing method of this embodiment, firstly, a reference layer 100 is selected from the multiple layer structures corresponding to the package substrate. The reference layer 100 is a layer used as a signal reference plane, for example, a power layer, a ground layer, and other layers covered with metal, and the reference layer 100 of the package substrate is not a fixed layer, but can be selected from the multiple layer structures of the package substrate according to actual needs. Since the embodiment of the present application needs to improve the routing method between the high-speed signal line and its corresponding solder ball 200, as an example, Figure 3A As shown, the layer structure (eg, the fifth layer) located above the solder ball 200 is selected as the reference layer 100 .

[0046] After selecting the reference layer 100, based on the location of the solder ball pad, the area corresponding to the solder ball pad is determined in the reference layer 100, that is, the area in the reference layer 100 that is directly opposite to the solder ball pad is determined in the vertical direction of the package substrate main body plane. Then the area determined in the reference layer 100 is hollowed out. Then, vias (110 and 120) for passing high-speed signal lines are set in the hollowed-out area 140 to transmit signals based on the set vias. The via 110 connects the hollowed-out area 140 of the reference layer 100 with the upper layer of the reference layer 100, and the via 120 connects the hollowed-out area 140 of the reference layer 100 with the lower layer of the reference layer 100.

[0047] It should be noted that since the reference layer 100 in the embodiment of the present application is a layer covered with metal such as a power layer and a ground layer, the high-speed signal must pass through the reference layer 100 but cannot be electrically connected to the reference layer 100. Therefore, it is necessary to hollow out the reference layer 100 to avoid the high-speed signal being electrically connected to the power supply or the ground.

[0048] Figure 3B Shown Figure 3A The corresponding stereoscopic view of the reference layer, Figure 3C Shown Figure 3B The top view of the corresponding reference layer. FIG. 3A to FIG. 3C As shown, the reference layer 100 includes a hollowed-out area 140 and a non-hollowed-out area 150, the hollowed-out area 140 is directly opposite to the solder ball pad, and the vias provided in the hollowed-out area 140 include vias 110 and vias 120, both of which are located directly above the solder ball 200, the vias 110 are located between the reference layer 100 and the layer structure on the reference layer 100, and the vias 120 are located between the reference layer 100 and the solder ball 200, so as to realize that the routing of the layer structure on the reference layer 100 is connected to the solder ball 200 through the vias 110 and the vias 120. Figure 3B 3 shows an intra-layer portion 1101 of the via 110 located in the reference layer 100 and an intra-layer portion 1201 of the via 120 located in the reference layer 100 .

[0049] The vias 110 and 120 may be formed by a metal structure, for example, by processing a metal sheet to form a hollow structure, the hollow structure may be a columnar structure, such as a square column, a round column, etc., or may be a hollow table-shaped structure, or may be a hollow structure in other forms, and the hollow structure formed based on the metal sheet is a via for a high-speed signal line to pass through. The formed via 110 is arranged between the reference layer 100 and the layer structure above the reference layer 100, and the formed via 120 is arranged between the reference layer 100 and the solder ball 200, and the via 110 and the via 120 may have the same form, or the via 110 and the via 120 may have different forms.

[0050] The vias 110 and 120 are used to allow high-speed signal lines to pass through. After the vias 110 and 120 are set on the reference layer 100, in order to ensure the continuity of the high-speed signal lines between the vias 110 and 120, the vias 110 and 120 need to be connected. Therefore, the vias 110 and 120 are connected in the hollowed-out area 140 of the reference layer 100. Connecting the vias 110 and 120 actually means connecting the via pads of the vias 110 and 120. Figure 3C As shown, the via pad 111 of the via 110 is connected to the via pad 121 of the via 120 , so as to ensure that the signal transmitted through the high-speed signal line can be transmitted in the hollowed-out area 140 of the reference layer 100 and reach the solder ball 200 through the connection of the two via pads.

[0051] Since the high-speed signal line in the BGA solder ball area will show a capacitive impedance drop, the capacitive impedance drop can be compensated by the inductive impedance, and the arc-shaped connecting line will form an inductive coil and show an inductive effect, therefore, an arc-shaped wire 130 is formed in the hollowed-out area 140 of the reference layer 100 to connect the via plates of the via 110 and the via 120. That is, the arc-shaped wire 130 is arranged between the via 110 and the via 120, and the arc-shaped wire 130 between the via 110 and the via 120 generates an inductive effect, and the inductive impedance generated by the inductive effect is used to compensate for the impedance drop of the high-speed signal line in the BGA solder ball area. FIG. 3A to FIG. 3C As shown, an arc-shaped conductive line 130 is formed between the via hole 110 and the via hole 120 . The arc-shaped conductive line 130 exhibits an inductive effect. The inductive effect generates an inductive impedance to compensate for the impedance drop of the high-speed signal line.

[0052] The arc-shaped conductor 130 connecting the via 110 and the via 120 is also equivalent to a resistor connected in series to the high-speed signal line. The resistor can provide impedance, and then the impedance drop of the high-speed signal line in the BGA solder ball area can be compensated based on the impedance provided by the resistor, so as to realize the compensation of the impedance drop based on the inductive impedance generated by the arc-shaped conductor 130 and the impedance provided by the resistor.

[0053] It should be noted that the structure of the reference layer of the embodiment of the present application is formed by improving the existing layer structure, and can also be a newly added layer structure. For the case where the structure is improved on the basis of the existing layer structure, after providing the packaging substrate, the reference layer of the packaging substrate is determined, the corresponding area of ​​the reference layer is hollowed out, and two vias are set in the hollowed-out area, one of which is located between the reference layer and the layer structure above the reference layer, and the other via is located between the reference layer and the solder ball, so that the routing of the layer structure located on the upper layer of the reference layer is connected to the solder ball through the two vias; the two vias are connected by an arc-shaped wire, so that the signal transmitted by the high-speed signal line reaches the solder ball, and the impedance drop of the high-speed signal line is compensated based on the generated inductive impedance and the impedance provided by the resistor. The processes used to implement this process are all existing processes and will not be introduced here. In this implementation method, the packaging substrate is improved on the basis of the existing structure, and there is no need to add a new layer structure, so as to achieve rational use of resources and save costs.

[0054] In the case where the reference layer is a newly added layer structure, before providing the packaging substrate, the packaging substrate is designed based on the idea of ​​hollowing out the corresponding area of ​​the reference layer, arranging two vias in the hollowed-out area to allow the high-speed signal line to pass through and connecting the two vias through arc wires. At this time, the reference layer of the packaging substrate is a newly added layer structure, and there is no need to improve the packaging substrate after providing the packaging substrate, which can simplify the design process and improve efficiency.

[0055] Regardless of the method used to provide the packaging substrate after processing the reference layer, the corresponding area of ​​the reference layer needs to be hollowed out. By hollowing out the reference layer, vias are arranged between the reference layer and the upper structure, and vias are arranged between the reference layer and the solder balls. An arc wire is set between the two vias. This allows the high-speed signal line to reach the solder ball, and the impedance drop can be compensated based on the inductive impedance generated by the arc wire and the impedance provided by the resistor.

[0056] The above embodiment introduces a scheme of arranging an arc wire between two vias, compensating the impedance drop of the high-speed signal line based on the inductive impedance generated by the inductive effect of the arc wire and the impedance provided by the arc wire as a resistor. In addition to compensating the impedance drop based on the arc wire arranged between the two vias, other methods can also be used to compensate for the impedance drop of the high-speed signal line. The following introduces a scheme of compensating the impedance drop of the high-speed signal line using other methods.

[0057] Figure 4A A schematic diagram of a routing method between a high-speed signal line and a solder ball provided in yet another embodiment of the present application is shown.

[0058] In this embodiment, it is also necessary to hollow out the corresponding area of ​​the reference layer 100 of the package substrate, and set vias (110 and 120) in the hollowed-out area 140 for passing the high-speed signal line. The via 110 is arranged between the reference layer 100 and the layer structure of the upper layer of the reference layer 100, and the via 120 is arranged between the reference layer 100 and the solder ball 200, so as to transmit the signal between the layer structure of the upper layer of the reference layer 100 and the solder ball 200 based on the set via. The morphology of the via 110 and the via 120 is the same as that of the above embodiment, but the connection method between the via 110 and the via 120 is different from that of the above embodiment. In this embodiment, the via 110 and the via 120 are adjacent, and the two are in contact at the shorter edge, and the contact position forms a connecting line with a narrow width, and the connecting line is equivalent to a resistor. In this case, the impedance drop of the high-speed signal line in the BGA solder ball area is compensated based on the impedance provided by the resistor.

[0059] Figure 4B Shown Figure 4A The corresponding stereoscopic view of the reference layer, Figure 4C Shown Figure 4B The top view of the corresponding reference layer. FIG. 4A to FIG. 4C As shown, the reference layer 100 includes a hollowed-out area 140 and a non-hollowed-out area 150. The hollowed-out area 140 is directly opposite to the solder ball pad. The via 110 and the via 120 are arranged in the hollowed-out area 140. The via 110 and the via 120 are both located directly above the solder ball 200. The via 110 is arranged between the reference layer 100 and the layer structure above the reference layer 100, and the via 120 is arranged between the reference layer 100 and the solder ball 200. Both the via 110 and the via 120 are circular holes. In terms of spatial structure, the via 110 and the via 120 are in contact. The contact position (the position where the two vias are tangent) forms a connecting line. The formed connecting line is different from the signal line, for example, the specification is different from the signal line (its cross-sectional diameter is smaller than the cross-sectional diameter of the signal line). The connecting line is equivalent to a resistor, providing impedance. Since via 110 and via 120 form a connecting line at a contact position, via 110 is arranged between reference layer 100 and the layer structure above reference layer 100, and via 120 is arranged between reference layer 100 and solder ball 200, the high-speed signal line can be connected to solder ball 200 through hole 110 and via 120, and the impedance drop of the high-speed signal line in the BGA solder ball area can be compensated based on the impedance provided by the resistor.

[0060] It should be noted that Figure 4BThe diagram shows that the via 110 is located in the layer portion 1101 of the reference layer 100, and the via 120 is located in the layer portion 1201 of the reference layer 100. Since the via 110 is located between the reference layer 100 and the layer structure above the reference layer 100, and the via 120 is located between the reference layer 100 and the solder ball 200, the contact between the via 110 and the via 120 is formed by the via plate 111 of the via 110 in the reference layer 100 and the via plate 121 of the via 120 in the reference layer 100, and the connection line formed by the contact between the two is used to connect the bottom end of the via 110 and the top end of the via 120. In addition, the structure of the reference layer 100 in the embodiment of the present application can be formed by improving the existing layer structure, or it can be a newly added layer structure.

[0061] By setting two vias to contact each other in the spatial structure and forming a connecting line based on the contact position, it is possible to replace additional wiring based on the spatial physical structure, save costs, and use the connecting line as a resistor to provide impedance, thereby realizing impedance compensation for the impedance drop of the high-speed signal line in the BGA solder ball area based on impedance.

[0062] Figure 5A A schematic diagram of a routing method between a high-speed signal line and a solder ball provided in yet another embodiment of the present application is shown.

[0063] In this embodiment, it is also necessary to hollow out the corresponding area of ​​the reference layer 100 of the package substrate, and set vias (110 and 120) for passing the high-speed signal line in the hollowed-out area 140. The via 110 is located between the reference layer 100 and the layer structure above the reference layer 100, and the via 120 is located between the reference layer 100 and the solder ball 200, so as to transmit the signal carried by the high-speed signal line based on the set via. The morphology of the via 110 and the via 120 is the same as that of the above embodiment, but the connection method between the via 110 and the via 120 is different from the above case. In the present embodiment, via 110 is adjacent to via 120 but not in contact with via 120. Via 110 and via 120 are connected by a short connecting line 160 (non-arc line). Connecting line 160 is different from the signal line, for example, it has a different specification from the signal line (its cross-sectional diameter is smaller than that of the signal line). Connecting line 160 is equivalent to a resistor. At this time, the impedance drop of the high-speed signal line in the BGA solder ball area is also compensated based on the impedance provided by the resistor.

[0064] Figure 5B Shown Figure 5A The corresponding stereoscopic view of the reference layer, Figure 5C Shown Figure 5B The top view of the corresponding reference layer. FIG. 5A to FIG. 5CAs shown, the reference layer 100 includes a hollowed-out area 140 and a non-hollowed-out area 150. The hollowed-out area 140 is directly opposite to the solder ball pad. The via 110 and the via 120 are arranged in the hollowed-out area 140. The via 110 and the via 120 are both located directly above the solder ball 200. The via 110 is located between the reference layer 100 and the layer structure of the upper layer of the reference layer 100, and the via 120 is located between the reference layer 100 and the solder ball 200. The via 110 and the via 120 are adjacent in spatial structure. The via plate 111 of the via 110 and the via plate 121 of the via 120 are connected by a non-arc connecting line 160. The connecting line 160 between the two is equivalent to a resistor, providing impedance. Since connecting wire 160 is arranged between via 110 and via 120, via 110 is located between reference layer 100 and the layer structure above reference layer 100, and via 120 is located between reference layer 100 and solder ball 200, high-speed signal line can be connected to solder ball 200 through hole 110 and via 120, and the impedance drop of the high-speed signal line in the BGA solder ball area can be compensated based on the impedance provided by the resistor.

[0065] It should be noted that Figure 5B 1 shows that via 110 is located in the inner layer portion 1101 of reference layer 100, and via 120 is located in the inner layer portion 1201 of reference layer 100. The structure of the reference layer in the embodiment of the present application can be formed by improving the existing layer structure, or can be a newly added layer structure.

[0066] By arranging two via holes adjacent to each other in spatial structure, arranging a non-arc connecting line between the two adjacent via holes, and using the connecting line as a resistor to provide impedance, impedance drop compensation of the high-speed signal line in the BGA solder ball area is achieved based on impedance.

[0067] The above introduces different implementation schemes for improving the routing mode between high-speed signal lines and their corresponding solder balls and compensating for the impedance drop of high-speed signal lines in the BGA solder ball area. The following describes the effects of different schemes of the present application through simulation results.

[0068] Figure 6 This is a comparison chart before and after impedance compensation of the BGA solder ball area by using the solution of laying arc-shaped wires between vias.

[0069] Figure 6 The horizontal axis represents time, and the vertical axis represents impedance. Routes A and B are different routes for transmitting high-speed signals. Before the impedance of route A is compensated, the impedance in the BGA solder ball area drops from 45 ohms to between 28 and 29 ohms. After the impedance of route A is compensated by laying arc wires between vias, the impedance drops from 45 ohms to between 32 and 33 ohms.

[0070] Before the impedance of trace B is compensated, the impedance in the BGA solder ball area drops from 45 ohms to about 27 ohms. After the impedance of trace B is compensated by laying arc-shaped wires between vias, the impedance drops from 45 ohms to between 34 and 35 ohms. It can be seen that the impedance compensation of traces in the BGA solder ball area by laying arc-shaped wires between vias can reduce the impedance drop in the BGA solder ball area.

[0071] Figure 7 This is a comparison diagram before and after impedance compensation of the BGA solder ball area using a solution that forms non-arc connecting lines between vias.

[0072] Figure 7 The horizontal axis represents time, and the vertical axis represents impedance. Routes C and D are different routes for transmitting high-speed signals. Before the impedance of route C is compensated, the impedance in the BGA solder ball area drops from 45 ohms to between 25-26 ohms. After the impedance of route C is compensated by forming a non-arc connecting line between vias, the impedance drops from 45 ohms to between 30-31 ohms.

[0073] Before the impedance of trace D is compensated, the impedance in the BGA solder ball area drops from 45 ohms to about 27 ohms. After the impedance of trace D is compensated by forming a non-arc-shaped connecting line between vias, the impedance drops from 45 ohms to between 30 ohms. It can be seen that the impedance compensation of traces in the BGA solder ball area by forming a non-arc-shaped connecting line between vias can also reduce the impedance drop in the BGA solder ball area.

[0074] Through Figure 6 as well as Figure 7 From the analysis, it can be seen that although the scheme of arranging arc-shaped wires between vias and the scheme of forming non-arc-shaped connecting lines between vias can both compensate for the impedance of the BGA solder ball area and reduce the impedance drop of the BGA solder ball area to a certain extent, the impedance compensation of the BGA solder ball area can be compensated by arranging arc-shaped wires between vias. However, compared with the scheme of forming non-arc-shaped connecting lines between vias, the impedance compensation of the scheme of arranging arc-shaped wires between vias is better. The reason is that the scheme of arranging arc-shaped wires between vias can not only compensate for the impedance drop of high-speed signal lines based on the impedance provided by resistors, but also compensate for the impedance drop based on the inductive impedance generated by the arc-shaped wires, thereby realizing impedance drop compensation from two levels.

[0075] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A high-speed signal line wiring structure for a chip packaging substrate, characterized in that: include: A first layer structure located in the package substrate, the first layer structure is a metal layer, the first layer structure includes a hollow area located above the solder ball, and a portion of the metal layer of the first layer structure in the hollow area is removed; a first via hole and a second via hole, wherein the first via hole is located between the first layer structure and the second layer structure, the second via hole is located between the first layer structure and the third layer structure, the second layer structure is located above the first layer structure, the third layer structure is located below the first layer structure, and the solder ball is disposed on the third layer structure; The intersection of the first via hole and the second via hole with the first layer structure is located in the hollowed-out area, so that the first via hole and the second via hole are not in contact with the metal layer of the first layer structure; a connecting structure between the first via hole and the second via hole; as well as The high-speed signal line located in the second layer structure is connected to the solder ball through the first via, the connection structure and the second via.

2. The high-speed signal line wiring structure for a chip packaging substrate according to claim 1, characterized in that: The projection of the solder ball onto the first layer structure in a direction perpendicular to the first layer structure is located in the hollowed-out area, and the first via hole and the second via hole are both located directly above the solder ball.

3. The high-speed signal line wiring structure for a chip packaging substrate according to claim 2, characterized in that: The first via is a first hollow structure formed based on a metal structure, allowing the high-speed signal line to pass from the second layer structure to the first layer structure; the second via is a second hollow structure formed based on a metal structure, allowing the high-speed signal line to pass from the first layer structure to the third layer structure.

4. The high-speed signal line wiring structure for a chip packaging substrate according to any one of claims 1 to 3, characterized in that: One end of the connection structure is connected to the via plate of the first via hole in the hollow area, and the other end is connected to the via plate of the second via hole in the hollow area.

5. The high-speed signal line wiring structure for a chip packaging substrate according to claim 4, characterized in that: The connection structure is an arc-shaped conductive wire connecting the first via hole and the second via hole; The arc-shaped conductive line compensates for the impedance drop of the high-speed signal line in the solder ball area.

6. The high-speed signal line wiring structure for a chip packaging substrate according to claim 4, characterized in that: The first via hole and the second via hole are in contact, and the contacted position forms a first connection line which is a resistor connected in series to the high-speed signal line; The impedance provided by the first connecting line compensates for the impedance drop of the high-speed signal line in the solder ball area.

7. The high-speed signal line wiring structure for a chip packaging substrate according to claim 4, characterized in that: The first via hole and the second via hole are connected by a non-arc second connecting line, and the second connecting line is a resistor connected in series to the high-speed signal line; The impedance provided by the second connecting line compensates for the impedance drop of the high-speed signal line in the solder ball area.

8. The high-speed signal line wiring structure for a chip packaging substrate according to any one of claims 1 to 3, characterized in that: The first layer structure is a power supply layer or a ground layer in the packaging substrate; or, The first layer structure is a layer structure added in the packaging substrate and specifically used for compensating for impedance drop.

9. A packaging substrate, characterized in that: The invention comprises a high-speed signal line wiring structure for a chip packaging substrate as claimed in any one of claims 1 to 8.

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