One-driving-two IIC communication circuit with low power consumption and isolated power supply

Abstract

The utility model relates to the technical field of double-battery systems, in particular to a one-driving-two IIC communication circuit with low power consumption and isolated power supply. Comprising a DC-DC converter, a battery pack, an FAE chip, an MCU, a power supply control circuit module, an isolation power supply circuit module, an LDO voltage reduction circuit module, an IIC signal isolation circuit module, a 3.3 V control circuit module, a grounding control circuit module, an LSDA communication control circuit module and an isolation ground control circuit module. Electricity is taken from the battery pack, so that the problem of imbalance of battery cells after long-time working is avoided; the problems of power consumption and electric leakage are solved by controlling the on-off of a ground loop; communication between the MCU and the two FAE chips can be realized through one pin of the MCU. The circuit has the advantages of balanced power consumption, high protection performance and small IO port occupation.

Description

Technical Field

[0001] The utility model relates to the technical field of dual battery systems, in particular to a one-to-two IIC communication circuit with low power consumption and isolated power supply. Background Art

[0002] Compared with electric bicycles, electric motorcycles have the advantages of faster speed and stronger power, and are becoming more and more popular among the public, with great market prospects. However, at present, the market share of electric motorcycles is still relatively low, and the FAE chips designed by existing chip manufacturers rarely support the high number of strings of electric motorcycles. Although the daisy chain chips used in energy storage and automobiles are suitable for high-speed electric motorcycles, they are too expensive to use on ordinary electric motorcycles.

[0003] At present, ordinary electric motorcycles are generally designed by cascading two FAE chips. The two FAE chips are generally cascaded using the method recommended by the manufacturer to take power from the high-series FAE chip to the IIC isolation chip. Although the cost is low, it will cause the problem of unbalanced cells after long-term use. In addition, the solution recommended by the manufacturer requires powering off both the power supply and the signal line, using more components, more complex logic and the risk of leakage.

[0004] Therefore, it is necessary to design a low-power isolated power supply one-to-two IIC communication circuit to solve the problem of battery cell imbalance, as well as power consumption and leakage problems. Summary of the invention

[0005] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a one-to-two IIC communication circuit with low power consumption and isolated power supply to solve the problem of battery cell imbalance, as well as power consumption and leakage problems.

[0006] In order to achieve the above-mentioned purpose, the utility model is a one-to-two IIC communication circuit with low power consumption and isolated power supply, comprising a DC-DC converter, a battery pack, a FAE chip, an MCU, a power control circuit module, an isolated power circuit module, an LDO step-down circuit module, an IIC signal isolation circuit module, a 3.3V control circuit module, a grounding control circuit module, an LSDA communication control circuit module, and an isolated ground control circuit module. Battery pack one and battery pack two are connected in series, the voltage collection end of FAE chip one is connected to the voltage collection point of battery pack one in sequence, and the voltage collection end of FAE chip two is connected to the voltage collection point of battery pack two in sequence. The positive electrode of battery pack 2 is connected to the input end of the DC-DC converter, the 5V output end of the DC-DC converter is respectively connected to the input end of the power control circuit module and the input end of the LDO step-down circuit module 2, the output end of the power control circuit module is connected to the input end of the isolation power circuit module, the output end of the isolation power circuit module is connected to the input end of the LDO step-down circuit module 1, the output end of the LDO step-down circuit module 1 is divided into two paths and respectively connected to the high-voltage isolation signal input end of the IIC signal isolation circuit module and the isolation power supply end of the isolation ground control circuit module, the output end of the LDO step-down circuit module 2 is divided into two paths and respectively connected to the supply of the MCU The power end and the input end of the 3.3V control circuit module are connected. The control signal end of the 3.3V control circuit module is divided into three paths and respectively connected with the control end of the power control circuit module, the low-voltage non-isolated signal input end of the IIC signal isolation circuit module, and the control end of the ground control circuit module. The PD_EN pin of the MCU is divided into three paths and respectively connected with the control end of the 3.3V control circuit module, the control end of the LSDA communication control circuit module, and the control end of the isolated ground control circuit module. The LSDA end of the LSDA communication control circuit module is connected to the LSDA end of the FAE chip 1. The SDA end of the LSDA communication control circuit module is divided into two paths. They are respectively connected to the SDA pin of the MCU and the SDA end of the IIC signal isolation circuit module, the HSCL end of the IIC signal isolation circuit module is connected to the HSCL end of the FAE chip two, the HSDA end of the IIC signal isolation circuit module is connected to the HSDA end of the FAE chip two, the SCL end of the IIC signal isolation circuit module is divided into two paths and are respectively connected to the SCL pin of the MCU and the SCL end of the FAE chip one, the isolated HGND of the IIC signal isolation circuit module is connected to the isolated HGND of the isolated ground control circuit module, and the ground end of the IIC signal isolation circuit module is connected to the ground end of the ground control circuit module.

[0007] The battery pack 1 is composed of several battery bodies 1 connected in series, and the voltage collection point of the battery pack 1 is the positive pole or negative pole of the battery body 1. The battery pack 2 is composed of several battery bodies 2 connected in series, and the voltage collection point of the battery pack 2 is the positive pole or negative pole of the battery body 2.

[0008] The models of the FAE chip 1 and the FAE chip 2 are SH367309, the model of the MCU is APM32F072CBT6, and the model of the DC-DC converter is MP4581.

[0009] The power control circuit module includes resistor 2, resistor 5, resistor 8, power tube 1, and power tube 3. The isolated power circuit module includes resistor 4, capacitor 1, capacitor 2, capacitor 3, capacitor 4, and an isolated power supply. The LDO buck circuit module 1 includes capacitor 5, capacitor 6, and LDO buck chip 1. The input end of the power control circuit module is divided into two paths and is respectively connected to one end of resistor 2 and the drain electrode of power tube 1. The other end of resistor 2 is divided into three paths and is respectively connected to the gate of power tube 1 and the drain electrode of power tube 3. The gate of power tube 3 is respectively connected to one end of resistor 5 and one end of resistor 8. The other end of resistor 5 is the control end of the power control circuit module. The other end of resistor 8 and the source of power tube 3 are grounded. The source of power tube 1 is divided into three paths and is respectively connected to One end of capacitor one is divided into three paths and respectively connected to one end of capacitor one, one end of capacitor two, and pin 2 of the isolated power supply; the other end of capacitor one, the other end of capacitor two, and pin 1 of the isolated power supply are grounded; pin 4 of the isolated power supply is divided into four paths and respectively connected to one end of capacitor three, one end of capacitor four, one end of capacitor five, and pin 2 of LDO buck chip one; pin 3 of LDO buck chip one is connected to one end of capacitor six; pin 3 of LDO buck chip one is the output end of LDO buck circuit module one; pin 3 of the isolated power supply, pin 1 of LDO buck chip one, the other end of capacitor three, the other end of capacitor four, the other end of capacitor five, the other end of capacitor six, and one end of resistor four are connected to the isolated ground; and the other end of resistor four is connected to HGND.

[0010] The LDO buck circuit module 2 includes an LDO buck chip 2, a capacitor 7, a capacitor 8, a capacitor 9, and a capacitor 10. The 3.3V control circuit module includes a resistor 1, a power tube 2, and a resistor 3. The LSDA communication control circuit module includes a resistor 6, a resistor 7, and a power tube 4. The input end of the LDO buck circuit module 2 is divided into two paths and is respectively connected to the No. 2 pin of the LDO buck chip 2 and one end of the capacitor 10. The No. 3 pin of the LDO buck chip 2 is divided into six paths and is respectively connected to one end of the capacitor 7, one end of the capacitor 8, one end of the capacitor 9, one end of the resistor 1, the drain electrode of the power tube 2, and the power supply end of the MCU. The other end of the capacitor 10, the other end of the capacitor 7, and the other end of the capacitor 8 are connected to the drain electrode of the power tube 2. The end, the other end of capacitor nine, and pin 1 of the LDO buck chip two are grounded, the source of the power tube two is the control signal end of the 3.3V control circuit module, the gate of the power tube two is divided into two paths and is respectively connected to the other end of the resistor one and one end of the resistor three, the other end of the resistor three is divided into three paths and is respectively connected to one end of the resistor six, the gate of the power tube four, and the PD_EN pin of the MCU, the source of the power tube four is connected to the other end of the resistor six, the source of the power tube four is the SDA end of the LSDA communication control circuit module, the drain electrode of the power tube four is connected to one end of the resistor seven, the drain electrode of the power tube four is the LSDA end of the LSDA communication control circuit module, and the other end of the resistor seven is connected to the power supply end of the MCU.

[0011] The IIC signal isolation circuit module comprises an IIC signal isolation chip, a resistor nine, a resistor ten, a resistor eleven, a resistor twelve, a capacitor eleven, and a capacitor twelve. The high-voltage isolation signal input end of the IIC signal isolation circuit module is divided into four paths and respectively connected to one end of the resistor nine, one end of the resistor ten, one end of the capacitor eleven, and pin 1 of the IIC signal isolation chip. The other end of the resistor nine is connected to pin 2 of the IIC signal isolation chip. Pin 2 of the IIC signal isolation chip is the HSDA end of the IIC signal isolation circuit module. The other end of the resistor ten is connected to pin 3 of the IIC signal isolation chip. Pin 3 of the IIC signal isolation chip is the HSCL end of the IIC signal isolation circuit module. The other end of the capacitor eleven is connected to pin 4 of the IIC signal isolation circuit module. , pin 4 of the IIC signal isolation chip is respectively connected to the isolated HGND, the low-voltage non-isolated signal input end of the IIC signal isolation circuit module is divided into four paths and respectively connected to one end of resistor 11, one end of resistor 12, one end of capacitor 12, and pin 8 of the IIC signal isolation chip, the other end of resistor 11 is connected to pin 7 of the IIC signal isolation chip, pin 7 of the IIC signal isolation chip is the SDA end of the IIC signal isolation circuit module, the other end of resistor 12 is connected to pin 6 of the IIC signal isolation chip, pin 6 of the IIC signal isolation chip is the SCL end of the IIC signal isolation circuit module, the other end of capacitor 12 and pin 5 of the IIC signal isolation chip are respectively connected to the ground end.

[0012] The model of the isolated power supply is B0505S-1WR2, the model of the LDO buck chip one is HT7550-1, the model of the LDO buck chip two is HT7533-1, and the model of the IIC signal isolation chip is π220N31.

[0013] The isolated ground control circuit module includes a photocoupler, a resistor thirteen, a resistor fourteen, a resistor sixteen, and a power tube five. The power supply end of the MCU is connected in series with the resistor thirteen and then connected to pin 1 of the photocoupler. Pin 2 of the photocoupler is the control end of the isolated ground control circuit module. The isolated power supply end of the isolated ground control circuit module is connected in series with the resistor fourteen and then connected to pin 4 of the photocoupler. Pin 3 of the photocoupler is divided into two paths and is respectively connected to one end of the resistor sixteen and the gate of the power tube five. The drain electrode of the power tube five is connected to the isolated HGND. The other end of the resistor sixteen and the source of the power tube five are connected to the HGND.

[0014] The grounding control circuit module comprises resistor 15, resistor 17 and power tube 6. After resistor 15 is connected in series to the control end of the grounding control circuit module, the control end is divided into two paths and respectively connected to one end of resistor 17 and the gate of power tube 6. The drain electrode of power tube 6 is connected to the ground end, and the other end of resistor 17 and power tube 6 are grounded.

[0015] After the negative electrode of the battery pack 1 is connected in series with a current-sensing resistor, it is divided into two paths and respectively connected to one end of the discharge switch and one end of the pre-discharge switch, the other end of the pre-discharge switch is connected to one end of the pre-discharge resistor, and the other end of the discharge switch is connected to the other end of the pre-discharge resistor.

[0016] Compared with the prior art, the utility model designs a one-to-two IIC communication circuit, draws power from the battery pack, avoids the imbalance problem of the battery cells after long-term work; solves the power consumption and leakage problems by controlling the on and off of the ground loop; and realizes the communication between the MCU and the two FAE chips through one pin of the MCU. The utility model has the advantages of balanced power consumption, high protection, and less IO port occupation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a principle block diagram of the utility model.

[0018] Figure 2 This is a circuit diagram of the power control circuit module, the isolated power circuit module, and the LDO step-down circuit module of the utility model.

[0019] Figure 3 This is a circuit diagram of the LDO step-down circuit module 2, the 3.3V control circuit module, and the LSDA communication control circuit module of the utility model.

[0020] Figure 4 This is a circuit diagram of the IIC signal isolation circuit module of the utility model.

[0021] Figure 5 This is a circuit diagram of the isolated ground control circuit module of the utility model.

[0022] Figure 6 This is a circuit diagram of the grounding control circuit module of the utility model. DETAILED DESCRIPTION

[0023] The utility model is now further described with reference to the accompanying drawings.

[0024] See also Figure 1The utility model is a low-power isolated power supply one-to-two IIC communication circuit, including a DC-DC converter, a battery pack, a FAE chip, an MCU, a power control circuit module, an isolated power circuit module, an LDO step-down circuit module, an IIC signal isolation circuit module, a 3.3V control circuit module, a grounding control circuit module, an LSDA communication control circuit module, and an isolated ground control circuit module. The battery pack 1 and the battery pack 2 are connected in series, the voltage collection end of the FAE chip 10 is connected to the voltage collection point of the battery pack 1 in sequence, the voltage collection end of the FAE chip 2 11 is connected to the voltage collection point of the battery pack 2 in sequence, and the positive electrode of the battery pack 2 is connected to the DC-D The 5V output end of the DC-DC converter is connected to the input end of the power control circuit module 1 and the input end of the LDO buck circuit module 2 4 respectively; the output end of the power control circuit module 1 is connected to the input end of the isolation power circuit module 2; the output end of the isolation power circuit module 2 is connected to the input end of the LDO buck circuit module 3; the output end of the LDO buck circuit module 3 is divided into two paths and respectively connected to the high-voltage isolation signal input end of the IIC signal isolation circuit module 7 and the isolation power supply end of the isolation ground control circuit module 8; the output end of the LDO buck circuit module 2 4 is divided into two paths and respectively connected to the power supply end of the MCU and the 3.3V control circuit end. The input end of the circuit module 5 is connected, the control signal end of the 3.3V control circuit module 5 is divided into three paths and respectively connected to the control end of the power control circuit module 1, the low voltage non-isolated signal input end of the IIC signal isolation circuit module 7, and the control end of the ground control circuit module 9, the PD_EN pin of the MCU is divided into three paths and respectively connected to the control end of the 3.3V control circuit module 5, the control end of the LSDA communication control circuit module 6, and the control end of the isolated ground control circuit module 8, the LSDA end of the LSDA communication control circuit module 6 is connected to the LSDA end of the FAE chip 10, and the SDA end of the LSDA communication control circuit module 6 is divided into two paths and respectively connected to the MCU The SDA pin of the IIC signal isolation circuit module is connected to the SDA end of the IIC signal isolation circuit module 7, the HSCL end of the IIC signal isolation circuit module 7 is connected to the HSCL end of the FAE chip 11, the HSDA end of the IIC signal isolation circuit module 7 is connected to the HSDA end of the FAE chip 11, the SCL end of the IIC signal isolation circuit module 7 is divided into two paths and is respectively connected to the SCL pin of the MCU and the SCL end of the FAE chip 10, the isolated HGND of the IIC signal isolation circuit module 7 is connected to the isolated HGND of the isolated ground control circuit module 8, and the ground end of the IIC signal isolation circuit module 7 is connected to the ground end of the ground control circuit module 9.

[0025] Battery pack 1 is composed of several battery bodies 1 connected in series, and the voltage collection point of battery pack 1 is the positive or negative electrode of battery body 1. Battery pack 2 is composed of several battery bodies 2 connected in series, and the voltage collection point of battery pack 2 is the positive or negative electrode of battery body 2.

[0026] The model of FAE chip one 10 and FAE chip two 11 is SH367309, the model of MCU is APM32F072CBT6, and the model of DC-DC converter is MP4581.

[0027] See also Figure 2 The power control circuit module 1 includes a resistor R2, a resistor R5, a resistor R8, a power tube Q1, and a power tube Q3. The isolated power circuit module 2 includes a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, and an isolated power supply U2. The LDO buck circuit module 3 includes a capacitor C5, a capacitor C6, and an LDO buck chip U3. The input end of the power control circuit module 1 is divided into two paths and is respectively connected to one end of the resistor R2 and the drain electrode of the power tube Q1. The other end of the resistor R2 is divided into three paths and is respectively connected to the gate of the power tube Q1 and the drain electrode of the power tube Q3. The gate of the power tube Q3 is respectively connected to one end of the resistor R5 and one end of the resistor R8. The other end of the resistor R5 is the control end of the power control circuit module 1. The other end of the resistor R8 and the source of the power tube Q3 are grounded. The source of the power tube Q1 is divided into three paths. One end of capacitor C1 is divided into three paths and respectively connected to one end of capacitor C1, one end of capacitor C2, and pin 2 of isolated power supply U2; the other end of capacitor C1, the other end of capacitor C2, and pin 1 of isolated power supply U2 are grounded; pin 4 of isolated power supply U2 is divided into four paths and respectively connected to one end of capacitor C3, one end of capacitor C4, one end of capacitor C5, and pin 2 of LDO buck chip U3; pin 3 of LDO buck chip U3 is connected to one end of capacitor C6; pin 3 of LDO buck chip U3 is the output end of LDO buck circuit module 3; pin 3 of isolated power supply U2, pin 1 of LDO buck chip U3, the other end of capacitor C3, the other end of capacitor C4, the other end of capacitor C5, the other end of capacitor C6, and one end of resistor R4 are connected to isolation ground; and the other end of resistor R4 is connected to HGND.

[0028] See also Figure 3, the LDO buck circuit module 2 4 includes an LDO buck chip 2 U1, a capacitor 7 C7, a capacitor 8 C8, a capacitor 9 C9, and a capacitor 10 C10, the 3.3V control circuit module 5 includes a resistor 1 R1, a power tube 2 Q2, and a resistor 3 R3, the LSDA communication control circuit module 6 includes a resistor 6 R6, a resistor 7 R7, and a power tube 4 Q4, the input end of the LDO buck circuit module 2 4 is divided into two paths and respectively connected to the No. 2 pin of the LDO buck chip 2 U1 and one end of the capacitor 10 C10, the No. 3 pin of the LDO buck chip 2 U1 is divided into six paths and respectively connected to one end of the capacitor 7 C7, one end of the capacitor 8 C8, one end of the capacitor 9 C9, one end of the resistor 1 R1, the drain electrode of the power tube 2 Q2, and the power supply end of the MCU, the other end of the capacitor 10 C10, the other end of the capacitor 7 C7, and the capacitor 8 C 8, the other end of capacitor C9, and pin 1 of LDO buck chip U1 are grounded, the source of power tube Q2 is the control signal end of 3.3V control circuit module 5, the gate of power tube Q2 is divided into two paths and respectively connected with the other end of resistor R1 and one end of resistor R3, the other end of resistor R3 is divided into three paths and respectively connected with one end of resistor R6, the gate of power tube Q4, and PD_EN pin of MCU, the source of power tube Q4 is connected with the other end of resistor R6, the source of power tube Q4 is the SDA end of LSDA communication control circuit module 6, the drain electrode of power tube Q4 is connected with one end of resistor R7, the drain electrode of power tube Q4 is the LSDA end of LSDA communication control circuit module 6, and the other end of resistor R7 is connected with the power supply end of MCU.

[0029] See also Figure 4The IIC signal isolation circuit module 7 includes an IIC signal isolation chip U4, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a capacitor C11, and a capacitor C12. The high-voltage isolation signal input end of the IIC signal isolation circuit module 7 is divided into four paths, which are respectively connected to one end of the resistor R9, one end of the resistor R10, one end of the capacitor C11, and pin 1 of the IIC signal isolation chip U4. The other end of the resistor R9 is connected to pin 2 of the IIC signal isolation chip U4. Pin 2 of the IIC signal isolation chip U4 is the HSDA end of the IIC signal isolation circuit module 7. The other end of the resistor R10 is connected to pin 3 of the IIC signal isolation chip U4. Pin 3 of the IIC signal isolation chip U4 is the HSCL end of the IIC signal isolation circuit module 7. The capacitor C11 is connected to the HSDA end of the IIC signal isolation circuit module 7. The other end of resistor R11 and pin 4 of the IIC signal isolation chip U4 are respectively connected to the isolated HGND, the low-voltage non-isolated signal input end of the IIC signal isolation circuit module 7 is divided into four paths and are respectively connected to one end of resistor R11, one end of resistor R12, one end of capacitor C12, and pin 8 of the IIC signal isolation chip U4, the other end of resistor R11 is connected to pin 7 of the IIC signal isolation chip U4, pin 7 of the IIC signal isolation chip U4 is the SDA end of the IIC signal isolation circuit module 7, the other end of resistor R12 is connected to pin 6 of the IIC signal isolation chip U4, pin 6 of the IIC signal isolation chip U4 is the SCL end of the IIC signal isolation circuit module 7, the other end of capacitor C12 and pin 5 of the IIC signal isolation chip U4 are respectively connected to the ground end.

[0030] The model of the isolated power supply U2 is B0505S-1WR2, the model of the LDO buck chip U3 is HT7550-1, the model of the LDO buck chip U1 is HT7533-1, and the model of the IIC signal isolation chip U4 is π220N31.

[0031] See also Figure 5 The isolated ground control circuit module 8 includes a photocoupler U5, a resistor thirteen R13, a resistor fourteen R14, a resistor sixteen R16, and a power tube five Q5. The power supply end of the MCU is connected in series with the resistor thirteen R13 and then connected to pin 1 of the photocoupler U5. Pin 2 of the photocoupler U5 is the control end of the isolated ground control circuit module 8. The isolated power supply end of the isolated ground control circuit module 8 is connected in series with the resistor fourteen R14 and then connected to pin 4 of the photocoupler U5. Pin 3 of the photocoupler U5 is divided into two paths and is respectively connected to one end of the resistor sixteen R16 and the gate of the power tube five Q5. The drain electrode of the power tube five Q5 is connected to the isolated HGND, and the other end of the resistor sixteen R16 and the source of the power tube five Q5 are connected to HGND.

[0032] See also Figure 6 The grounding control circuit module 9 includes a resistor R15, a resistor R17, and a power tube Q6. After the control end of the grounding control circuit module 9 is connected in series with the resistor R15, it is divided into two paths and respectively connected to one end of the resistor R17 and the gate of the power tube Q6. The drain electrode of the power tube Q6 is connected to the ground end, and the other end of the resistor R17 and the power tube Q6 are grounded.

[0033] In order to facilitate discharge detection and pre-discharge, the negative electrode of battery group 1 is connected in series with a current detection resistor, and then divided into two paths, which are respectively connected to one end of the discharge switch and one end of the pre-discharge switch. The other end of the pre-discharge switch is connected to one end of the pre-discharge resistor, and the other end of the discharge switch is connected to the other end of the pre-discharge resistor. When discharge detection is required, the discharge switch is closed; when pre-discharge is required, the pre-discharge switch is closed.

[0034] When the utility model is working, the DC-DC converter takes power from the whole battery pack and steps it down to 5.0V output. When the PD_EN pin of the MCU outputs a low level, it controls the 3.3V-I2C output, and 3.3V-I2C supplies power to the low-voltage non-isolated end of the IIC signal isolation chip U4. At the same time, the power tube Q3 is turned on, and the power tube Q1 is turned on, thereby controlling the power control circuit module 1 to output a 5V-Com power supply. The 5V-Com power supply is converted into an isolated power supply through U2, and is then stepped down to 3.3V through the LDO step-down chip U3 to ensure the stability of the power supply. Another 5.0V power supply output by the DC-DC converter is stepped down to 3.3V through the LDO step-down chip U1 and output to the power supply end of the MCU.

[0035] When the PD_EN pin of the MCU outputs a low level, the SDA pin of the MCU is controlled to be connected to the HSDA end of the high-string FAE chip 2 11, and the MCU can communicate with the high-string FAE chip 2 11. When the PD_EN pin of the MCU outputs a high level, the SDA pin of the MCU is controlled to be connected to the LSDA end of the low-string FAE chip 10, and the MCU can communicate with the low-string FAE chip 10. Only by using the PD_EN pin of the MCU, the MCU can communicate with the high-string FAE chip 2 11 and the low-string FAE chip 10 respectively, saving the occupation of the IO port, and the IIC signal isolation chip U4 is completely powered off when there is no communication, realizing low power consumption control.

[0036] The left side of the IIC signal isolation chip U4 is the high voltage signal that needs to be isolated, and the right side is the safe low voltage signal. HSDA and HSCL are the IIC signals of the high-series FAE chip 211, and SDA and SCL are the IIC signals of the MCU.

[0037] When the MCU's PD_EN pin outputs a low level, the optocoupler U5 works, the power tube Q5 is turned on, and HGND is connected to pin 4 of the IIC signal isolation chip U4 through the isolated HGND. When the MCU's PD_EN pin outputs a low level, it also controls the 3.3V-I2C output, and then the power tube Q6 is turned on, and the ground is connected to pin 5 of the IIC signal isolation chip U4 through the ground terminal. When the MCU's PD_EN pin outputs a high level, the optocoupler U5 stops working, the power tube Q5 is turned off, and HGND is disconnected from pin 4 of the IIC signal isolation chip U4; at the same time, the 3.3V-I2C stops outputting, and then the power tube Q6 is turned off, and the ground is disconnected from pin 5 of the IIC signal isolation chip U4.

[0038] As mentioned above, after PD_EN outputs a low level, the utility model can be applied to a dual battery system of light electric vehicles such as electric scooters, electric bicycles, electric power-assisted vehicles, and electric motorcycles.

[0039] The utility model designs a one-to-two IIC communication circuit, which takes power from the battery pack to avoid the imbalance of the battery cells after long-term work; by controlling the on-off of the ground loop, the power consumption and leakage problems are solved; and the communication between the MCU and the two FAE chips can be realized through one pin of the MCU. The utility model has the advantages of balanced power consumption, high protection, and less IO port occupation.

Claims

1. A low-power isolated power supply one-to-two IIC communication circuit, comprising a DC-DC converter, a battery pack, a FAE chip, an MCU, a power control circuit module, an isolated power circuit module, an LDO step-down circuit module, an IIC signal isolation circuit module, a 3.3V control circuit module, a grounding control circuit module, an LSDA communication control circuit module, and an isolated ground control circuit module, characterized in that: The battery pack 1 and the battery pack 2 are connected in series, the voltage collection end of the FAE chip 1 (10) is connected to the voltage collection point of the battery pack 1 in sequence, the voltage collection end of the FAE chip 2 (11) is connected to the voltage collection point of the battery pack 2 in sequence, the positive electrode of the battery pack 2 is connected to the input end of the DC-DC converter, the 5V output end of the DC-DC converter is respectively connected to the input end of the power control circuit module (1) and the input end of the LDO step-down circuit module 2 (4), the output end of the power control circuit module (1) is connected to the input end of the isolation power circuit module (2), and the output end of the isolation power circuit module (2) is connected to the LDO step-down circuit module 2 (4). The output end of the LDO buck circuit module (3) is divided into two paths and respectively connected to the high voltage isolation signal input end of the IIC signal isolation circuit module (7) and the isolation power supply end of the isolation ground control circuit module (8); the output end of the LDO buck circuit module (4) is divided into two paths and respectively connected to the power supply end of the MCU and the input end of the 3.3V control circuit module (5); the control signal end of the 3.3V control circuit module (5) is divided into three paths and respectively connected to the control end of the power control circuit module (1) and the low voltage non-isolated signal input end of the IIC signal isolation circuit module (7). The PD_EN pin of the MCU is connected to the control end of the 3.3V control circuit module (5), the control end of the LSDA communication control circuit module (6), and the control end of the isolation ground control circuit module (8). The LSDA end of the LSDA communication control circuit module (6) is connected to the LSDA end of the FAE chip 1 (10). The SDA end of the LSDA communication control circuit module (6) is connected to the SDA pin of the MCU and the SDA end of the IIC signal isolation circuit module (7). The IIC signal isolation circuit module The HSCL end of the IIC signal isolation circuit module (7) is connected to the HSCL end of the FAE chip 2 (11), the HSDA end of the IIC signal isolation circuit module (7) is connected to the HSDA end of the FAE chip 2 (11), the SCL end of the IIC signal isolation circuit module (7) is divided into two paths and respectively connected to the SCL pin of the MCU and the SCL end of the FAE chip 1 (10), the isolated HGND of the IIC signal isolation circuit module (7) is connected to the isolated HGND of the isolated ground control circuit module (8), and the ground end of the IIC signal isolation circuit module (7) is connected to the ground end of the ground control circuit module (9).

2. A one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The battery pack 1 is composed of several battery bodies 1 connected in series, and the voltage collection point of the battery pack 1 is the positive pole or negative pole of the battery body 1. The battery pack 2 is composed of several battery bodies 2 connected in series, and the voltage collection point of the battery pack 2 is the positive pole or negative pole of the battery body 2.

3. A one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The models of the FAE chip 1 (10) and the FAE chip 2 (11) are SH367309, the model of the MCU is APM32F072CBT6, and the model of the DC-DC converter is MP4581.

4. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The power control circuit module (1) comprises a resistor 2 (R2), a resistor 5 (R5), a resistor 8 (R8), a power tube 1 (Q1), and a power tube 3 (Q3); the isolated power circuit module (2) comprises a resistor 4 (R4), a capacitor 1 (C1), a capacitor 2 (C2), a capacitor 3 (C3), a capacitor 4 (C4), and an isolated power supply (U2); the LDO buck circuit module 1 (3) comprises a capacitor 5 (C5), a capacitor 6 (C6), an LDO buck chip 1 (U3); the power control circuit module ( The input end of the power control circuit module (1) is divided into two paths and is respectively connected to one end of the resistor 2 (R2) and the drain electrode of the power tube 1 (Q1). The other end of the resistor 2 (R2) is divided into three paths and is respectively connected to the gate of the power tube 1 (Q1) and the drain electrode of the power tube 3 (Q3). The gate of the power tube 3 (Q3) is respectively connected to one end of the resistor 5 (R5) and one end of the resistor 8 (R8). The other end of the resistor 5 (R5) is the control end of the power control circuit module (1). The other end of the resistor 8 (R8) and the source of the power tube 3 (Q3) are grounded. The power tube 1 ( The source of Q1 is divided into three paths and connected to one end of capacitor 1 (C1), one end of capacitor 2 (C2), and pin 2 of the isolated power supply (U2). The other end of capacitor 1 (C1), the other end of capacitor 2 (C2), and pin 1 of the isolated power supply (U2) are grounded. Pin 4 of the isolated power supply (U2) is divided into four paths and connected to one end of capacitor 3 (C3), one end of capacitor 4 (C4), one end of capacitor 5 (C5), and pin 2 of LDO buck chip 1 (U3). Pin 3 of DO buck chip 1 (U3) is connected to one end of capacitor 6 (C6), pin 3 of LDO buck chip 1 (U3) is the output end of LDO buck circuit module 1 (3), pin 3 of isolated power supply (U2), pin 1 of LDO buck chip 1 (U3), the other end of capacitor 3 (C3), the other end of capacitor 4 (C4), the other end of capacitor 5 (C5), the other end of capacitor 6 (C6), and one end of resistor 4 (R4) are connected to the isolation ground, and the other end of resistor 4 (R4) is connected to HGND.

5. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The LDO buck circuit module 2 (4) comprises an LDO buck chip 2 (U1), a capacitor 7 (C7), a capacitor 8 (C8), a capacitor 9 (C9), and a capacitor 10 (C10); the 3.3V control circuit module (5) comprises a resistor 1 (R1), a power tube 2 (Q2), and a resistor 3 (R3); the LSDA communication control circuit module (6) comprises a resistor 6 (R6), a resistor 7 (R7), and a power tube 4 (Q4); the input end of the LDO buck circuit module 2 (4) is divided into two paths and respectively connected to pin 2 of the LDO buck chip 2 (U1) and one end of the capacitor 10 (C10); the pin 3 of the LDO buck chip 2 (U1) is divided into six paths and respectively connected to one end of the capacitor 7 (C7), one end of the capacitor 8 (C8), one end of the capacitor 9 (C9), one end of the resistor 1 (R1), the drain electrode of the power tube 2 (Q2), and the power supply end of the MCU; the other end of the capacitor 10 (C10), the capacitor 7 (C7) and the drain electrode of the power tube 2 (Q2) are connected to the power supply end of the MCU; The other end of the capacitor eight (C8), the other end of the capacitor nine (C9), and the No. 1 pin of the LDO buck chip two (U1) are grounded, the source of the power tube two (Q2) is the control signal end of the 3.3V control circuit module (5), the gate of the power tube two (Q2) is divided into two paths and is respectively connected to the other end of the resistor one (R1) and one end of the resistor three (R3), the other end of the resistor three (R3) is divided into three paths and is respectively connected to one end of the resistor six (R6), the gate of the power tube four (Q4), and the PD_EN pin of the MCU, the source of the power tube four (Q4) is connected to the other end of the resistor six (R6), the source of the power tube four (Q4) is the SDA end of the LSDA communication control circuit module (6), the drain electrode of the power tube four (Q4) is connected to one end of the resistor seven (R7), the drain electrode of the power tube four (Q4) is the LSDA end of the LSDA communication control circuit module (6), and the other end of the resistor seven (R7) is connected to the power supply end of the MCU.

6. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The IIC signal isolation circuit module (7) comprises an IIC signal isolation chip (U4), a resistor nine (R9), a resistor ten (R10), a resistor eleven (R11), a resistor twelve (R12), a capacitor eleven (C11), and a capacitor twelve (C12). The high-voltage isolation signal input end of the IIC signal isolation circuit module (7) is divided into four paths, which are respectively connected to one end of the resistor nine (R9), one end of the resistor ten (R10), one end of the capacitor eleven (C11), and pin 1 of the IIC signal isolation chip (U4). The other end of the resistor nine (R9) is connected to pin 2 of the IIC signal isolation chip (U4). Pin 2 of the IIC signal isolation chip (U4) is the HSDA end of the IIC signal isolation circuit module (7). The other end of the resistor ten (R10) is connected to pin 3 of the IIC signal isolation chip (U4). Pin 3 of the IIC signal isolation chip (U4) is the HSCL end of the IIC signal isolation circuit module (7). The other end of the capacitor eleven (C11) and the No. 4 pin of the IIC signal isolation chip (U4) are respectively connected to the isolated HGND. The low-voltage non-isolated signal input end of the IIC signal isolation circuit module (7) is divided into four paths and respectively connected to one end of the resistor eleven (R11), one end of the resistor twelve (R12), one end of the capacitor twelve (C12), and the No. 8 pin of the IIC signal isolation chip (U4). The other end of the resistor eleven (R11) is connected to the No. 7 pin of the IIC signal isolation chip (U4). The No. 7 pin of the IIC signal isolation chip (U4) is the SDA end of the IIC signal isolation circuit module (7). The other end of the resistor twelve (R12) is connected to the No. 6 pin of the IIC signal isolation chip (U4). The No. 6 pin of the IIC signal isolation chip (U4) is the SCL end of the IIC signal isolation circuit module (7). The other end of the capacitor twelve (C12) and the No. 5 pin of the IIC signal isolation chip (U4) are respectively connected to the ground end.

7. A one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 4, 5 or 6, characterized in that: The model of the isolated power supply (U2) is B0505S-1WR2, the model of the LDO buck chip 1 (U3) is HT7550-1, the model of the LDO buck chip 2 (U1) is HT7533-1, and the model of the IIC signal isolation chip (U4) is π220N31.

8. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The isolated ground control circuit module (8) comprises a photocoupler (U5), a resistor thirteen (R13), a resistor fourteen (R14), a resistor sixteen (R16), and a power tube five (Q5). The power supply end of the MCU is connected in series with the resistor thirteen (R13) and then connected to pin 1 of the photocoupler (U5). Pin 2 of the photocoupler (U5) is the control end of the isolated ground control circuit module (8). The isolated power supply end of the isolated ground control circuit module (8) is connected in series with the resistor fourteen (R14) and then connected to pin 4 of the photocoupler (U5). Pin 3 of the photocoupler (U5) is divided into two paths and respectively connected to one end of the resistor sixteen (R16) and the gate of the power tube five (Q5). The drain electrode of the power tube five (Q5) is connected to the isolated HGND. The other end of the resistor sixteen (R16) and the source of the power tube five (Q5) are connected to the HGND.

9. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: The grounding control circuit module (9) comprises a resistor fifteen (R15), a resistor seventeen (R17), and a power tube six (Q6). After the control end of the grounding control circuit module (9) is connected in series with the resistor fifteen (R15), it is divided into two paths and respectively connected to one end of the resistor seventeen (R17) and the gate of the power tube six (Q6). The drain electrode of the power tube six (Q6) is connected to the ground end, and the other end of the resistor seventeen (R17) and the power tube six (Q6) are grounded.

10. The one-to-two IIC communication circuit with low power consumption and isolated power supply according to claim 1, characterized in that: After the negative electrode of the battery pack 1 is connected in series with a current-sensing resistor, it is divided into two paths and respectively connected to one end of the discharge switch and one end of the pre-discharge switch, the other end of the pre-discharge switch is connected to one end of the pre-discharge resistor, and the other end of the discharge switch is connected to the other end of the pre-discharge resistor.

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