Static random access memory unit

Abstract

A static random access memory cell includes a first n-channel layer bonded with a first gate layer to form a first device; a first p-channel layer bonded to the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer; a second n-channel layer bonded to the second gate layer to form a third device, the second n-channel layer coupled to the first n-channel layer; a third n-channel layer bonded to the third gate layer to form a fourth device, the third n-channel layer spaced apart from the second n-channel layer; a second p-channel layer bonded to a third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer; and a fourth n-channel layer bonded with the fourth gate layer to form a sixth device, and the fourth n-channel layer is coupled to the third n-channel layer.

Description

Technical Field

[0001] The present disclosure relates to static random access memory cells. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in many different fields. Some of these digital devices are configured to store data. Static random-access memory (SRAM) devices are a type of volatile semiconductor memory in which data bits are stored using circuitry that does not require refreshing. SRAM devices generally include one or more memory arrays, where each array includes a plurality of SRAM cells. SRAM cells are generally referred to as bit cells because they store one information bit represented by the logic state of two cross-coupled inverters. Although existing implementations of SRAM cells as part of the front-end-of-line (FEOL) process are generally adequate, these implementations are not completely satisfactory in all aspects. For example, the device density of FEOL SRAM devices is generally limited by the planar surface area of ​​the IC chip, and an increase in device density requires an increased chip area and, therefore, a higher cost associated with the manufacture of the device. Therefore, there is a need for improvements in the structure of memory devices such as SRAM devices to reduce area consumption. Utility Model Content

[0003] According to some embodiments of the present disclosure, a static random access memory cell is provided. The static random access memory cell includes a first n-channel layer, which is bonded to a first gate layer to form a first device; a first p-channel layer, which is bonded to the first gate layer to form a second device, wherein the first gate layer is stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer, which is bonded to a second gate layer to form a third device, wherein the second gate layer is coupled to a first word line, and the second n-channel layer is coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer, which is bonded to the first word line; a third gate layer joined to form a fourth device, wherein the third n-channel layer is spaced apart from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer joined to the third gate layer to form a fifth device, wherein the third gate layer is stacked between the third n-channel layer and the second p-channel layer along the first direction; and a fourth n-channel layer joined to a fourth gate layer to form a sixth device, wherein the fourth gate layer is coupled to a second word line, and the fourth n-channel layer is coupled to the third n-channel layer along the second direction.

[0004] According to some embodiments of the present disclosure, a static random access memory cell is provided. The static random access memory cell includes a first n-type metal oxide semiconductor device, including a first channel layer, connected to a first gate layer; a first p-type metal oxide semiconductor device, including a second channel layer, connected to the first gate layer, wherein the first gate layer is interposed between the first channel layer and the second channel layer along a first direction, and wherein the first n-type metal oxide semiconductor device and the first p-type metal oxide semiconductor device form a first inverter; a second n-type metal oxide semiconductor device, adjacent to the first n-type metal oxide semiconductor device along a second direction perpendicular to the first direction and including a third channel layer, connected to the second gate layer; a third ... A metal oxide semiconductor device comprises a fourth channel layer joined to a third gate layer, wherein the fourth channel layer is separated from the third channel layer along a third direction perpendicular to the first direction and the second direction; a second p-type metal oxide semiconductor device comprises a fifth channel layer joined to the third gate layer, wherein the third gate layer is interposed between the fourth channel layer and the fifth channel layer along the first direction, and wherein the third n-type metal oxide semiconductor device and the second p-type metal oxide semiconductor device form a second inverter; and a fourth n-type metal oxide semiconductor device adjacent to the third n-type metal oxide semiconductor device along the second direction and comprising a sixth channel layer joined to a fourth gate layer.

[0005] According to some embodiments of the present disclosure, a static random access memory cell is provided. The static random access memory cell includes: a first n-channel layer coupled to a first contact along a first direction; an interconnect structure including a vertical portion and a horizontal portion, the vertical portion of the interconnect structure being adjacent to the first n-channel layer, wherein the first n-channel layer is interposed between the first contact and the vertical portion of the interconnect structure along the first direction; a first gate layer located above the first n-channel layer; a first p-channel layer located above the first gate layer, wherein the first gate layer is interposed between the first n-channel layer and the first p-channel layer along a second direction perpendicular to the first direction, the vertical portion of the interconnect structure extending along the second direction, the first n-channel layer and the first p-channel layer having a plurality of different conductivity types; a second contact, which is opposite to the first p-channel layer. a second n-channel layer coupled to the first n-channel layer along the first direction; a second gate layer adjacent to and located above the second n-channel layer; a third n-channel layer spaced apart from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer located above the third n-channel layer; a third gate layer interposed between the second n-channel layer and the second p-channel layer along the second direction perpendicular to the second direction; a fourth n-channel layer coupled to the third n-channel layer along the first direction; and a fourth gate layer adjacent to and located above the fourth n-channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 The various aspects of the present disclosure can be best understood from the following detailed description when read together. It should be noted that various features are not drawn to scale according to standard practice in the industry. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram illustrating a semiconductor device including a plurality of memory cells according to some embodiments;

[0008] Figure 2 A three-dimensional (3D) perspective view of an illustrative semiconductor device including a plurality of memory cells according to some embodiments;

[0009] Figure 3 An implementation circuit diagram is provided to illustrate some embodiments;

[0010] Figure 4 Description of the method according to some embodiments Figure 3A 3D perspective view of an implementation memory cell of a circuit diagram;

[0011] Figure 5 Description of some embodiments Figure 4 A plan view of a memory cell;

[0012] Figure 6 Description of some embodiments Figure 5 A cross-sectional view of a memory cell along line A-A';

[0013] Figure 7 illustrates a 3D perspective view of an illustrative semiconductor device including a plurality of memory cells arranged in a stacked configuration according to some embodiments;

[0014] Figure 8 An implementation circuit diagram is provided to illustrate some embodiments;

[0015] Fig. 9 Description of the method according to some embodiments Figure 8 A 3D perspective view of an implementation memory cell of a circuit diagram;

[0016] Fig.10 Description of some embodiments Fig. 9 A plan view of a memory cell;

[0017] Fig.11 Description of the method according to some embodiments Figure 8 A 3D perspective view of an implementation memory cell of a circuit diagram;

[0018] Fig.12 , Fig.13 , Fig.14 and Fig.15 Each of the embodiments of the present invention is described in detail. Figure 5 A cross-sectional view of a memory cell along lines AA' and BB';

[0019] Fig.16 , Fig.17 , Fig.18 and Fig.19 Each of the embodiments of the present invention is described in detail. Fig.10 A cross-sectional view of a memory cell along lines C-C', D-D' and E-E';

[0020] Fig. 20 Description of the formation according to some embodiments Figure 4 , Fig. 9 or Fig.10 Implementation method of memory unit;

[0021] Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 Each of the following describes some embodiments Fig. 20 A cross-sectional view of a memory cell at an intermediate stage of the method.

[0022]

Explanation of symbols

[0023] 10: Memory Device

[0024] 10, 50, 80: Semiconductor devices

[0025] 12, 52, 82: Memory array

[0026] 13, 53, 100, 300, 350, 500: memory units

[0027] 100:BEOL SRAM Cell

[0028] 14: Line Decoder

[0029] 16: Column decoder

[0030] 18:I / O circuit

[0031] 20, 60, 90: PC

[0032] 22: Control logic circuit

[0033] 101:Vdd

[0034] 101a, 101b: first contact

[0035] 103: Grounding

[0036] 103a, 103b, 103c: second contact

[0037] 105: Write character line

[0038] 105a, 105b: word line, WL

[0039] 107: bit line, BL

[0040] 109: bit line, BBL

[0041] 110, 114: Internal structure

[0042] 112, 116: Node

[0043] 202: Dielectric layer

[0044] 202a: first patterned dielectric layer

[0045] 202b: second patterned dielectric layer

[0046] 202c: third patterned dielectric layer

[0047] 202d: fourth patterned dielectric layer

[0048] 202e: fifth patterned dielectric layer

[0049] 206, 226, 246, 266, 286, 288: Gate layer

[0050] 210, 240: p channel layer

[0051] 212, 232, 252, 272, 282, 283, 284, 285: n channel layer

[0052] 214, 216, 218, 220, 254, 258, 260, 290, 292, 294: gate dielectric layer

[0053] 291: Third contact

[0054] 301: Read character line

[0055] 303: Read bit line

[0056] 400: Method

[0057] 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422: Operation

[0058] 501:Substrate

[0059] 502, 503, 504, 506, 508, 510, 512, 514, 518, 520, 522, 524: Groove A-A', B-B', C-C', D-D', E-E': Line

[0060] C1, C2, C3, ..., C N :List

[0061] CW: Channel Width

[0062] L1, L2: length

[0063] M1, M2, M3, M4, M5, M6, M7, M8: transistors

[0064] M7', M8': dual-channel NMOS devices, transistors

[0065] R1, R2, R3, ..., R M :OK DETAILED DESCRIPTION

[0066] The following disclosure provides many different implementations or embodiments for realizing the different features of the provided mark. The specific embodiments of the components and configurations described below are for simplifying the disclosure. Of course, these are only embodiments and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an implementation in which the first feature and the second feature are directly contacted, and may also include an implementation in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various implementations and / or configurations discussed.

[0067] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0068] Figure 1 An exemplary block diagram of a semiconductor (eg, memory) device 10 is shown according to various embodiments. Figure 1 In the illustrated embodiment, the memory device 10 includes a memory array 12, a row decoder 14, a column decoder 16, an input / output (I / O) circuit 18, and a control logic circuit 22. Figure 1 Although not explicitly shown in FIG. 1 , the elements of semiconductor device 10 may be operably coupled to each other and to control logic circuit 22. For example, control logic circuit 22, I / O circuit 18, column decoder 16, and row decoder 14 may be electrically coupled to memory array 12. Figure 1In the illustrated embodiment of the present invention, the components are shown as separate blocks for the purpose of clarity, but in some other embodiments, some or all of the components may be integrated together. For example, the memory array 12 may include embedded I / O circuits 18. In some embodiments, the row decoder 14, the column decoder 16, the I / O circuits 18, and the control logic circuits 22 may be collectively referred to as peripheral circuits (PC) 20. The PC 20 may also include other components not depicted herein, such as drivers (e.g., word line drivers).

[0069] The memory array 12 is a hardware element for storing data. In one aspect, the memory array 12 is embodied as a semiconductor memory device. The memory array 12 includes a plurality of memory cells (or storage cells) 13. The memory array 12 includes a plurality of rows R1, R2, R3, ..., R4, each extending in a first direction (e.g., X direction). M and a plurality of columns C1, C2, C3, . . . , C each extending in a second direction (eg, the Y direction). N Each of the rows / columns may include one or more conductive structures. In some embodiments, each memory cell 13 is disposed at the intersection of a corresponding row and a corresponding column and may be operated according to a voltage or current passing through the respective conductive structures of the column and the row. In the disclosed embodiment, each memory cell 13 corresponds to a static random-access memory (SRAM) cell.

[0070] The row decoder 14 is a hardware element that can receive a row address of the memory array 12 and enable a conductive structure (e.g., a word line) at the row address. The column decoder 16 is a hardware element that can receive a column address of the memory array 12 and enable one or more conductive structures (e.g., a bit line, a source line) at the column address. The I / O circuit 18 is a hardware element that can access (e.g., read, program) each of the memory cells 13 enabled via the row decoder 14 and the column decoder 16. The control logic circuit 22 is a hardware element that can control the coupled elements (e.g., 12 to 18).

[0071] refer to Figure 2, illustrates a schematic diagram of an illustrative semiconductor device 50. The semiconductor device 50 includes a plurality of memory arrays 52 coupled to a plurality of PCs 60, each of the plurality of memory arrays 52 being similar to the memory array 12, and each of the plurality of PCs 60 may include one or more elements similar to the elements of the PC 20. As used in the present disclosure, terms such as "coupled" and "connected" refer to electrical and / or physical connections between two elements of a semiconductor device with or without any intermediate layers or elements. Each of the memory arrays 52 includes a plurality of memory cells 53 similar to the memory cell 13. For example, the memory cell 53 may be an SRAM cell. In another embodiment, the memory cell 53 may be an SRAM cell formed by a front-end-of-line (FEOL) process. In some embodiments, the memory arrays 52 and the PCs 60 are coupled to each other in a network structure extending above the same plane. In this regard, the density of the memory cells 53 in the semiconductor device 50 will be limited by the planar area of ​​the chip (or wafer). Increased density may result in a need for larger chip areas and, therefore, higher costs associated with device manufacturing. In this regard, as IC technology continues to advance, limitations on the density of memory cells in semiconductor memory devices may limit the development of devices with higher processing speeds at reduced length scales. Therefore, improvements in the structure of semiconductor memory devices are needed to reduce area consumption.

[0072] The present disclosure provides structures for SRAM cells formed in a back-end-of-line (BEOL) network. In embodiments of the present disclosure, the BEOL network enables the transistors of each SRAM cell to be formed in a stacked configuration rather than a planar configuration, which reduces the need for chip area and reduces the costs associated with device manufacturing. In addition, the BEOL network provides additional design flexibility with respect to cell architecture and wiring structures when compared to planar SRAM cells manufactured as part of a FEOL network, which generally includes device features along a major surface of a semiconductor substrate. In contrast, the BEOL network generally includes various interconnect structures, such as horizontal interconnect structures (e.g., metal lines) and vertical interconnect structures (e.g., vias), for connecting device features of the FEOL network with additional features to form, for example, an IC chip. The present disclosure provides memory devices including SRAM cells formed as part of a BEOL network rather than a FEOL network, as discussed in detail below.

[0073] refer to Figure 3, illustrates an example circuit diagram of a memory cell (memory bit or bit cell; similar to memory cells 13 and 53) 100. According to some embodiments of the present disclosure, the memory cell 100 is configured as an SRAM cell including a plurality of transistors. For example, as depicted herein, the memory cell 100 includes six transistors (six-transistor; 6T), and is therefore referred to as a 6T SRAM cell. For example, in some embodiments, the memory cell 100 can be implemented as any of a variety of SRAM cells such as a two-transistor-two-resistor (2T-2R) SRAM cell, a four-transistor (4T)-SRAM cell, an eight-transistor (8T)-SRAM cell, a ten-transistor (10T)-SRAM cell, and the like. Although the present disclosure is discussed with respect to SRAM cells, it should be understood that other embodiments of the present disclosure may also be used in any of memory cells such as, for example, dynamic random access memory (DRAM) cells.

[0074] like Figure 3 As shown in , the memory cell 100 includes 6 transistors: M1, M2, M3, M4, M5 and M6. Transistors M1 and M2 are formed as a first inverter (or a first cross-coupled inverter), and transistors M3 and M4 are formed as a second inverter (or a second cross-coupled inverter), wherein the first inverter and the second inverter are cross-coupled with each other. Specifically, the first inverter and the second inverter are each coupled between a first contact 101a / 101b to which a supply voltage Vdd is applied and a second contact 103a / 103b connected to ground. In this regard, the first contact 101a / 101b is marked with "Vdd" and the second contact 103a / 103b is marked with "Vss". In addition to being coupled to the first inverter and the second inverter, transistors M6 and M5 are each coupled to word lines (WL) 105a and 105b, respectively. Transistors M6 and M5 are further coupled to a bit line (BL) 107 and a bit bar line (BBL) 109, respectively. It should be noted that in some embodiments, the first contacts 101a and 101b may be coupled together, the second contacts 103a and 103b may be coupled together, and the WLs 105a and 105b may be coupled together.

[0075] In some embodiments, transistors M1 and M3 are referred to as pull-up transistors of memory cell 100; transistors M2 and M4 are referred to as pull-down transistors of memory cell 100; and transistors M5 and M6 are referred to as access transistors of memory cell 100. In some embodiments, transistors M2, M4, M5, and M6 each include an n-type metal-oxide-semiconductor (NMOS) transistor, and M1 and M3 each include a p-type metal-oxide-semiconductor (PMOS) transistor. In some embodiments, as described herein, memory cell 100 includes four NMOS transistors and two PMOS transistors. In some embodiments, memory cell 100 includes two NMOS transistors and four PMOS transistors. Although Figure 3 The illustrated embodiments show that the transistors M1 to M6 are either NMOS or PMOS transistors, but any of a variety of transistors or devices suitable for memory devices may be implemented as at least one of the transistors M1 to M6, such as, for example, a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc.

[0076] Access transistors M5 and M6 have gates (e.g., gate layers or gate electrodes) coupled to WL 105a and WL 105b, respectively. The gates of transistors M5 and M6 are used to receive pulse signals through WL 105a / 105b, respectively, to allow or prevent access to memory cell 100 accordingly. Transistors M2 and M5 are coupled to each other at a Q bar (Q bar; QB) node with the drain of transistor M2 and the source of transistor M5. The QB node is further coupled to the drain of transistor M1 and node 112. Transistors M4 and M6 are coupled to each other at a Q node with the drain of transistor M4 and the source of transistor M6. The Q node is further coupled to the drain of transistor M3 and node 116.

[0077] When a memory cell (e.g., memory cell 100) stores a data bit, a first node of the bit cell is configured to be in a first logic state (either logic 1 or logic 0), and a second node of the bit cell is configured to be in a second logic state (either logic 0 or logic 1). The first logic state and the second logic state are complementary to each other. In some embodiments, the first logic state at the first node may represent the logic state of the data bit stored in the memory cell. For example, in Figure 3In the illustrated embodiment, when the memory cell 100 stores a data bit at a logic 1 state, the QB node is configured to be at a logic 1 state, and the Q node is configured to be at a logic 0 state.

[0078] To read the logic state of the data bit stored in the memory cell 100, the BL 107 and the BBL 109 are precharged to Vdd (e.g., logic high, such as using a capacitor to hold the charge). Next, by asserting the valid signal or activating WL 105 to logic high, this turns on the access transistors M5 and M6. Specifically, the rising edge of the valid signal is received at the gates of the access transistors M5 and M6, respectively, so as to turn on the access transistors M5 and M6. Once the access transistors M5 and M6 based on the logic state of the data bit are turned on, the precharged BL 107 or BBL 109 may begin to discharge. For example, when the memory cell 100 stores a logic 0, the Q node may present a voltage corresponding to a logic 1, and the QB node may present a voltage corresponding to a complementary logic 0. In response to turning on the access transistors M5 and M6, a discharge path may be provided starting from the precharged BBL 109, through the access transistor M5 and the pull-down transistor M2, and to the ground 103. When the voltage level on BBL 109 is pulled down through this discharge path, the pull-down transistor M4 can remain off. As a result, BL 107 and BBL 109 can each present a voltage level to generate a sufficiently large voltage difference between BL 107 and BBL 109. Therefore, the sense amplifier coupled to BL 107 and BBL 109 can use the polarity of the voltage difference to determine whether the logic state of the data bit is logic 1 or logic 0.

[0079] To write the logic state of a data bit stored in memory cell 100, the data to be written is applied to BL 107 and / or BBL 109. For example, using a low impedance connection, BBL 109 is connected / shorted to 0V, such as Vss. Next, by asserting or activating WL 105a / 105b to a logic high with a valid signal, this turns on access transistors M5 and M6. Once access transistors M5 and M6 are turned on based on the logic state of BBL 109, the QB node may begin to discharge. For example, before M5 and M6 are turned on, BBL 109 may present a voltage corresponding to a logic 0, and the QB node may present a voltage corresponding to a complementary logic 1. In response to turning on access transistors M5 and M6, a discharge path may be provided from the QB node, through access transistor M5 to ground 103. Once the voltage level on the QB node is pulled down below the Vth (threshold voltage) of the pull-down transistor M4, M4 may be turned off and M3 may be turned on, causing the Q node to be pulled up to Vdd 101. Once the Q node is less than Vth from Vdd, M1 may be turned off and M2 may be turned on, causing the QB node to be pulled down to ground 103. Then, when WL105a / 105b is deactivated, the logic state applied to BL 107 and / or BBL 109 has been stored in the memory cell 100.

[0080] Common Reference Figures 4 to 6 , illustrates an embodiment of a memory cell 100 showing a detailed configuration of various transistors. Figure 4 A 3D perspective view of the memory cell 100 is depicted; Figure 5 depicts a top view of the memory cell 100 in the XY plane; and Figure 6 Depicted is a memory cell 100 along Figure 5 It should be noted that for the sake of clarity, part of the memory cell 100 may be omitted. Figures 4 to 6 Portions of the dielectric (or insulating) layer 202 surrounding the various components of the memory cell 100 are omitted.

[0081] As discussed above, the exemplary memory cell 100 is configured as a 6T SRAM cell having two inverters each coupled to an access transistor. In the disclosed embodiment, the first inverter comprises transistors M1 and M2 coupled together, and the second inverter comprises transistors M3 and M4 coupled together, wherein M1 and M3 each comprise a PMOS transistor, and M2 and M4 each comprise an NMOS transistor. Access transistors M5 and M6 each comprise an NMOS transistor.

[0082] In the disclosed embodiments, the memory cell 100 is configured as part of the BEOL network of the IC device, rather than as part of the FEOL network. In other words, the memory cell 100 is formed in one or more metallization layers above a semiconductor substrate (not depicted), and the memory cell 100 may include multiple FEOL devices and / or features. In this regard, the memory cell 100 may alternatively be referred to as a BEOL SRAM cell 100. According to various embodiments of the present disclosure, although the BEOL SRAM cell 100 may function in a similar manner to a FEOL SRAM cell (i.e., according to Figure 3 ), but the BEOL SRAM cell 100 has a different structure than the FEOL SRAM cell, as discussed in detail below.

[0083] In the present disclosure, reference is made to Figure 4 and Figure 6 , transistor M1 as a PMOS device includes a channel layer (hereinafter referred to as "p-channel layer") 210 disposed above and bonded to a gate layer (or gate electrode) 206, such that the p-channel layer 210 is vertically stacked above the gate layer 206 along the Z-axis. Transistor M1 also includes a gate dielectric layer 214 disposed between the p-channel layer 210 and the gate layer 206. In addition, the p-channel layer 210 is laterally interposed between the first contact 101a (i.e., Vdd) and a vertical portion of the interconnect structure 110 along the X-axis, wherein the first contact 101a and the interconnect structure 110 each serve as a source / drain of transistor M1.

[0084] The transistor M2 as an NMOS device includes a channel layer (hereinafter referred to as "n-channel layer") 212 bonded to the gate layer 206, wherein the gate layer 206 is vertically stacked above the n-channel layer 212 along the Z-axis. In other words, the n-channel layer 212 and the p-channel layer 210 are disposed above opposite surfaces of the gate layer 206 along the Z-axis. The transistor M2 also includes a gate dielectric layer 216 disposed between the n-channel layer 212 and the gate layer 206. In this regard, the transistor M1 is vertically stacked above the transistor M2, wherein their common gate layer 206 is interposed between the p-channel layer 210 and the n-channel layer 212 along the Z-axis. In addition, the n-channel layer 212 is laterally interposed between the second contact 103a (i.e., Vss) and the vertical portion of the interconnect structure 110 along the X-axis, wherein the second contact 103a and the interconnect structure 110 each serve as a source / drain of the transistor M2. As shown, the interconnect structure 110 extends vertically along the Z-axis to couple the transistor M1 to the transistor M2. Figure 3 1. The memory cell 100 is depicted in the same manner as in FIG.

[0085] Still refer to Figure 4 and Figure 6, transistor M5, also as an NMOS device, includes an n-channel layer 232 bonded to a gate layer 226, wherein the gate layer 226 is vertically stacked above the n-channel layer 232 along the Z-axis. In other words, the n-channel layer 232 and the n-channel layer 212 are laterally adjacent to each other along the X-axis, and are separated from the n-channel layer 232 and the n-channel layer 212 along a vertical portion of the X-axis interconnect structure 110. In addition, the n-channel layer 232 and the n-channel layer 212 are flush or substantially flush along the Z-axis (i.e., disposed in the same XY plane), while the p-channel layer 210 and the n-channel layer 232 are offset along the Z-axis (i.e., disposed in different XY planes separated along the Z-axis).

[0086] According to some embodiments, the transistor M5 further includes a gate dielectric layer 218 disposed between the n-channel layer 232 and the gate layer 226 (see Figure 6 ). As shown, gate layer 226 is laterally adjacent to gate layer 206 along the X-axis, and gate layer 226 is separated from gate layer 206 by dielectric layer 202 and portions of interconnect structure 110. In some embodiments, an additional gate dielectric layer 220 is formed over gate layer 226 such that gate dielectric layer 218 and gate dielectric layer 220 are formed over opposing surfaces of gate layer 226 along the Z-axis. n-channel layer 232 is interposed between interconnect structure 110 and BBL 109 along the X-axis, wherein interconnect structure 110 and BBL 109 each function as (or are each coupled to) a source / drain of transistor M5. In addition, referring to Figure 4 and Figure 5 , transistor M5 is coupled to WL 105a at gate layer 226. Further, Figure 3 , interconnect structure 110 extends vertically along the Z-axis to couple transistors M1, M2, and M5 together at the source / drain of each transistor.

[0087] To provide isolation for gate layers 206 and 226, the X-axis (eg, Figure 4 and Figure 6 ) and forming a dielectric layer 202 adjacent to each gate layer 206 and 226 along the Y axis (not depicted). For example, a portion of the dielectric layer 202 separates the gate layer 206 from the interconnect structure 110 along the X axis. In some embodiments, reference Figure 5 , gate layers 206 and 226 each extend along the Y-axis away from their respective channel layers (e.g., p-channel layer 210 and n-channel layer 212 of gate layer 206 and n-channel layer 232 of gate layer 226) to provide coupling of the transistor to other portions of memory cell 100. In one embodiment, the extended portion of gate layer 206 provides coupling of transistors M1 and M2 at node 116, which is connected to interconnect structure 114. In another embodiment, the extended portion of gate layer 226 provides coupling of transistor M5 to WL 105a.

[0088] refer to Figure 4 and Figure 5 , transistors M3, M4 and M6 are configured with structures similar to those of transistors M1, M2 and M5, respectively. For example, transistor M3 as a PMOS device includes a p-channel layer 240 disposed above and bonded to a gate layer 246, wherein a gate dielectric layer 254 is disposed between the p-channel layer 240 and the gate layer 246. The p-channel layer 240 is stacked above the gate layer 246 along the Z-axis and interposed between the first contact 101b (i.e., Vdd) and a vertical portion of the interconnect structure 114 along the X-axis, wherein the first contact 101b and the interconnect structure 114 each serve as a source / drain of the transistor M3.

[0089] refer to Figure 4 , transistor M4 as an NMOS device includes an n-channel layer 252 bonded to a gate layer 246, wherein the gate layer 246 is stacked above the n-channel layer 252 along the Z-axis. In this regard, similar to the configuration of the p-channel layer 210, the n-channel layer 212, and the gate layer 206, the n-channel layer 252 and the p-channel layer 240 are disposed above opposite surfaces of the gate layer 246 along the Z-axis. Transistor M4 also includes a gate dielectric layer (not depicted herein) similar to any of the above-described gate dielectric layers 214, 216, 218, 220, and 254. The n-channel layer 252 is interposed between the second contact 103b (i.e., Vss) and a vertical portion of the interconnect structure 114 along the X-axis, wherein the second contact 103b and the interconnect structure 114 each serve as a source / drain of transistor M4.

[0090] Still refer to Figure 4, transistor M6, also as an NMOS device, includes an n-channel layer 272 bonded to a gate layer 266, wherein the gate layer 266 is stacked above the n-channel layer 272 along the Z-axis. In other words, the n-channel layer 272 and the n-channel layer 252 are laterally adjacent to each other along the X-axis, and the interconnect structure 114 separates the n-channel layer 272 and the n-channel layer 252. Transistor M6 also includes a gate dielectric layer 258 disposed between the n-channel layer 272 and the gate layer 266. In some embodiments, an additional gate dielectric layer 260 is formed above the gate layer 266, such that the gate dielectric layer 258 and the gate dielectric layer 260 are formed above opposite surfaces of the gate layer 266 along the Z-axis. In addition, the n-channel layer 272 is disposed between the interconnect structure 114 and the BL 107 along the X-axis, wherein the interconnect structure 114 and the BL 107 each serve as (or are each coupled to) the source / drain of transistor M6. In addition, similar to the configuration of n-channel layer 212, n-channel layer 232 and p-channel layer 210, n-channel layer 272 and n-channel layer 252 are flush or substantially flush along the Z-axis (i.e., disposed in the same XY plane), while p-channel layer 240 and n-channel layer 272 are offset along the Z-axis (i.e., disposed in different XY planes separated along the Z-axis).

[0091] In order to provide isolation for gate layers 246 and 266 (in the same or different memory cells 100), it is also possible to provide isolation along the X-axis (e.g., Figure 4 ) and forms a dielectric layer 202 adjacent to each gate layer 246 and 266 along the Y axis (not depicted). For example, a portion of the dielectric layer 202 separates the gate layer 246 from the interconnect structure 110 along the X axis. In some embodiments, reference Figure 4 And similar to gate layers 206 and 226, gate layers 246 and 266 each extend along the Y-axis away from their respective channel layers (e.g., p-channel layer 240 and n-channel layer 252 of gate layer 246 and n-channel layer 272 of gate layer 266) to provide transistor coupling to other portions of memory cell 100. In one embodiment, the extended portion of gate layer 246 provides coupling of transistors M3 and M4 at node 112, which is connected to interconnect structure 110. In another embodiment, the extended portion of gate layer 266 provides coupling of transistor M6 to WL 105b.

[0092] In some embodiments, reference Figure 6, gate layer 206, gate dielectric layer 214, and gate dielectric layer 216 each extend along the X-axis by a length L1, while p-channel layer 210 and n-channel layer 212 each extend along the X-axis by a length L2 (i.e., the channel length of each of transistors M1 and M2), and length L2 is greater than length L1. In some embodiments, this difference between lengths L1 and L2 allows each of p-channel layer 210 and n-channel layer 212 to completely overlap with gate layer 206 (and the corresponding gate dielectric layer), thereby allowing the device to operate normally. Return to Reference Figure 5 , the p-channel layer 210 and the underlying n-channel layer 212 (not depicted) can each be defined by a channel width CW along the Y-axis. In some embodiments, the channel widths of the p-channel layer 210 and the n-channel layer 212 are independently adjusted to different values ​​to implement different read or write functions in the memory cell 100.

[0093] In the disclosed embodiment, the first inverter of the memory cell 100 includes a common gate (e.g., gate layer 206 and a corresponding gate dielectric layer), which is vertically stacked and bonded with a p-channel layer (e.g., p-channel layer 210) and an n-channel layer (e.g., n-channel layer 212) to form transistors M1 and M2, respectively. Similarly, the second inverter of the memory cell 100 includes a common gate (e.g., gate layer 246 and a corresponding gate dielectric layer), which is vertically stacked and bonded with a p-channel layer (e.g., p-channel layer 240) and an n-channel layer (e.g., n-channel layer 252) to form transistors M3 and M4, respectively.

[0094] In the disclosed embodiment, the interconnect structure 110 corresponds to the QB node, and the interconnect structure 114 corresponds to the Q node. Figure 3 . Each of the interconnect structures 110 and 114 includes a vertical portion extending along the Z axis, a first lateral portion extending along the X axis, and a second lateral portion extending along the Y axis. Thus, as part of the BEOL network, the interconnect structures 110 and 114 provide connections between different vertically stacked transistors within the memory cell 100, thereby allowing the transistors to be configured in a 3D configuration rather than a planar configuration and reducing the wafer area requirements and costs associated with device manufacturing.

[0095] refer to Figure 7, illustrates a schematic diagram of an illustrative semiconductor device 80. The semiconductor device 80 includes a plurality of memory arrays 82 coupled to one or more PCs 90, each of which may be similar to the PC 20. In the depicted embodiment, the PCs 90 are disposed below the memory arrays 82. Each memory array 82 includes a plurality of memory cells 100 as described herein. In the disclosed embodiment, the semiconductor device 80 differs from the semiconductor device 50 in that the memory arrays 82 (i.e., the memory cells 100) are stacked vertically along a stacking direction (i.e., the Z-axis as depicted), resulting in the semiconductor device 80 having a 3D stacked configuration, rather than a planar configuration, as is the case with the semiconductor device 50.

[0096] For the purpose of discussion, the stacking direction of the memory array 82 points to the direction away from the semiconductor substrate (not depicted) of the semiconductor device 80, wherein the semiconductor substrate is disposed below the memory array 82 (e.g., disposed at the same level as the PC 90 or disposed below the PC 90). In this regard, for two adjacent memory arrays 82 (or memory cells 100) disposed along the stacking direction, the memory array 82 (or memory cell 100) closer to the semiconductor substrate may be considered as the bottom memory array 82 (or bottom memory cell 100), while the other memory array 82 (or memory cell 100) further away from the semiconductor substrate may be considered as the top memory array 82 (or top memory cell 100). This convention in the stacking direction also applies to the transistors within each memory cell 100. For example, the transistor closer to the semiconductor substrate is disposed at the bottom level of the memory cell 100, while the transistor further away from the semiconductor substrate is disposed at the top level of the memory cell 100.

[0097] refer to Figure 8 , illustrates an implementation circuit diagram of the memory cell 300. The memory cell 300 is similar to the memory cell 300 except that the memory cell 300 includes two additional transistors (pull-down transistor M7 and access transistor M8), making the memory cell 300 referred to as an eight-transistor (8T) SRAM cell. Figure 3 The implementation circuit diagram of the memory cell 100 is similar.

[0098] As shown, the gate of the pull-down transistor (hereinafter referred to as transistor) M7 is coupled to the output of the first inverter formed by transistors M1 and M2. One of the source / drain of the access transistor (hereinafter referred to as transistor) M8 is coupled to the drain of the transistor M7. The source of the transistor M7 is coupled to ground, which is the other of the second contact 103c or Vss. In some embodiments, the transistor M7 can be implemented as a pull-up transistor. The gate of the transistor M8 is coupled to the read word line (RWL) 301. The second of the source / drain of the transistor M8 is coupled to the read bit line (RBL) 303. WL 105a / 105b, BL 107, and BBL 109 are referred to herein as write word line (WWL) 105, write bit line (WBL) 107, and write bit barline (WBBL) 109, respectively.

[0099] In some embodiments, as depicted herein, memory cell 300 includes six NMOS transistors and two PMOS transistors, wherein two of the NMOS transistors are configured as read ports. In some embodiments, memory cell 100 includes two NMOS transistors and six PMOS transistors, wherein two of the PMOS transistors are configured as read ports. In some embodiments, memory cell 100 includes four NMOS transistors and four PMOS transistors, wherein two of the NMOS transistors or two of the PMOS transistors are configured as read ports. In some embodiments, memory cell 300 may include more than eight transistors, such as ten transistors used to form a ten-transistor (10T) SRAM cell.

[0100] To read the logic state of a data bit stored in memory cell 300, RBL 303 is precharged to Vdd. Next, the valid signal is asserted or activated RWL 301 to logic high, which turns on access transistor M8. Once transistor M8 is turned on based on the logic state of the data bit, the precharged RBL 303 can begin to discharge. In some embodiments, a sense amplifier coupled to RBL 303 and a reference voltage can use the polarity of the voltage difference between RBL 303 and the reference voltage to determine whether the logic state of the data bit is a logic 1 or a logic 0. To write the logic state of a data bit stored in memory cell 300, a sense amplifier is connected to RBL 303 and a reference voltage to determine whether the logic state of the data bit is a logic 1 or a logic 0. Figure 3 The same operation is performed in the memory unit 100.

[0101] Common Reference Figures 9 and 10, illustrates an embodiment of a memory cell 300 showing a detailed configuration of various components. Fig. 9 depicts a 3D perspective view of a memory cell 300; and Fig.10 300 is depicted as a top view in the XY plane. It should be noted that portions of the memory cell 300 may be omitted for clarity. Fig. 9 and Fig.10 3. Portions of dielectric layer 202 surrounding various elements of memory cell 300 are omitted. It should be further noted that memory cell 300 is structurally similar to memory cell 100 according to embodiments of the present disclosure. For example, six of the eight transistors of memory cell 300 are configured in the same manner as transistors M1 to M6 of memory cell 100. Therefore, for the sake of brevity, only portions of memory cell 300 that differ in structure from memory cell 100, namely, transistors M7 and M8, are discussed in detail below, and elements of memory cell 300 that are similar to elements of memory cell 100 are described using the same reference numerals.

[0102] Transistors M7 and M8 each have a structure similar to that of transistors M5 or M6 discussed in detail above. For example, according to some embodiments, transistor M7 is an NMOS device including an n-channel layer 282 bonded to a gate layer 286, wherein the gate layer 286 is vertically stacked above the n-channel layer 282 along the Z-axis. Transistor M7 also includes a gate dielectric layer (not depicted herein) disposed between the n-channel layer 282 and the gate layer 286. As shown, the gate layer 286 is laterally adjacent to the gate layer 288 of transistor M8 along the X-axis and is separated by a portion of the dielectric layer 202 and a third contact 291 that couples transistor M7 to transistor M8. In some embodiments, an additional gate dielectric layer 290 is formed above the gate layer 286. The n-channel layer 282 is interposed between the second contact 103c and the third contact 291 along the X-axis, wherein the second contact 103c and the third contact 291 each serve as (or are each coupled to) the source / drain of transistor M7. In addition, as shown Fig. 9 and Fig.10 As shown in FIG. 1 , coupled transistors M7 and M8 are further coupled to interconnect structure 114 at gate layer 286. In this regard, interconnect structure 114 extends along the Y-axis to couple gate layer 286 to gate layer 266 of transistor M6 and gate layer 206 of transistor M1.

[0103] In some embodiments, transistor M8 is an NMOS device including an n-channel layer 284 bonded to a gate layer 288, wherein the gate layer 288 is stacked vertically above the n-channel layer 284 along the Z-axis. Transistor M8 also includes a gate dielectric layer 292 disposed between the n-channel layer 284 and the gate layer 288. As shown, the gate layer 288 is laterally adjacent to the gate layer 286 of transistor M7 along the X-axis and is separated by a portion of the dielectric layer 202 and a third contact 291 that couples transistor M7 to transistor M8. In some embodiments, an additional gate dielectric layer 294 is formed above the gate layer 286 such that the gate dielectric layers 292 and 294 are disposed above opposing surfaces of the gate layer 288 along the Z-axis. The n-channel layer 284 is interposed between the third contact 291 and the RBL 303 along the X-axis, wherein the third contact 291 and the RBL 303 each function as (or are each coupled to) the source / drain of transistor M8. In addition, as shown in FIG. Fig.10 As shown in , RWL 301 is coupled to a portion of gate layer 288 that extends away from n-channel layer 284 along the Y direction.

[0104] refer to Fig.11 , an implementation of the memory cell 350 is illustrated in a 3D perspective view. The memory cell 350 and Fig. 9 and Fig.10 The memory unit 300 is similar in that the memory unit 350 includes a Figure 8 3 and 4. The circuit diagram of memory cell 350 is shown as eight transistors coupled together and thus is considered an 8T SRAM cell. However, unlike memory cell 300, memory cell 350 includes two dual-channel NMOS devices M7' and M8' corresponding to transistors M7 and M8 of memory cell 300, respectively. In some embodiments, transistor M7' is a pull-down transistor having two n-channel layers 282 and 283 bonded to gate layer 286. For example, n-channel layer 282, gate layer 286, and n-channel layer 283 are arranged in a vertical stack along the Z-axis in a configuration similar to that of transistors M1 and M2. Similarly, transistor M8' is an access transistor having two n-channel layers 284 and 285, which are bonded to gate layer 288 and arranged in a vertical stack along the Z-axis. In some embodiments, by adopting a dual channel structure, transistors M7' and M8' are configured as dual read port NMOS devices in memory cell 350 with increased channel length to achieve higher device speed.

[0105] In some implementations, the stacking configurations of various transistors in the memory cell 100, the memory cell 300, and the memory cell 350 of the embodiment may be adjusted to accommodate different design requirements and device wiring architectures. Figures 12 to 15 Each of the above reference Figure 7The stacking direction (i.e., the Z-axis) is defined as follows: Figure 5 Schematic cross-sectional view of each of the lines AA' and BB' of the memory cell 100 shown in FIG. The lines AA' and BB' are each taken along the X-axis through one of the inverters of the memory cell 100 and its corresponding access transistor. Figures 16 to 19 Each of the Figure 7 The defined stacking direction describes the Fig.10 Schematic cross-sectional view of each of the lines C-C', D-D', and EE' of the memory cell 300 shown in . For illustrative purposes, the transistors M1 and M3 of the memory cells 100 and 300 are collectively referred to as PMOS devices, and the transistors M2 to M8 of the memory cells 100 and 300 are collectively referred to as NMOS devices. The lines C-C' and D-D' are each taken along the X-axis through one of the inverters and its corresponding access transistor, while the line D-D' is taken along the X-axis through the transistors M7 and M8 of the memory cell 300.

[0106] In some embodiments, reference Fig.12 , both PMOS devices are arranged at the top level of the memory cell 100, and their corresponding NMOS devices are arranged at the bottom level of the memory cell 100. This configuration is similar to Figures 4 to 6 In some embodiments, the configuration described in Fig.13 The positions of the PMOS devices are opposite to those of the NMOS devices along the stacking direction (relative to Fig.12 ), such that the PMOS device is disposed at the bottom level of the memory cell 100 and the NMOS device is disposed at the top level of the memory cell 100. In some embodiments, reference Fig.14 and Fig.15 , the position of one of the PMOS devices is reversed from its corresponding NMOS device, while the position of the other of the PMOS devices and its corresponding NMOS device remain the same Fig.12 The situation is the same in the configuration of .

[0107] In some embodiments, reference Fig.16 , both PMOS devices are arranged at the top level of the memory cell 300, and the NMOS device is arranged at the bottom level of the memory cell 300. This configuration is similar to Fig. 9 and Fig.10 In some embodiments, the configuration described in Fig.17 The positions of the PMOS devices are opposite to those of the NMOS devices along the stacking direction (relative to Fig.16), such that the PMOS device is disposed at the bottom level of the memory cell 300 and the NMOS device is disposed at the top level of the memory cell 300. In some embodiments, reference Fig.18 and Fig.19 , the position of one of the PMOS devices is reversed from its corresponding NMOS device, while the position of the other of the PMOS devices and its corresponding NMOS device remain the same Fig.16 The transistors M7 and M8, both of which are NMOS devices, can be arranged at the same level as other NMOS devices. In some embodiments, the stacking configuration of the transistors M1 to M6 of the memory cell 350 can be adjusted in a manner similar to the manner of the transistors M1 to M6 of the memory cell 300 described herein.

[0108] Fig. 20 is a flow chart of a method 400 for forming a memory cell 500 (eg, a semiconductor structure) according to some embodiments. The operations of the method 400 are described with reference to Figures 21 to 39 Described, Figures 21 to 39 4 is a cross-sectional view of a portion of a memory cell 500 at an intermediate stage of method 400 according to some embodiments. Memory cell 500 may be configured as follows: Figures 3 to 19 For example, the memory cell 100, 300 or 350 depicted in one or more of the embodiments of the present invention may be formed. Figures 21 to 39 1 and 1. The memory cell 500 is shown in cross-sectional views, each of which is similar to the Figure 6 The memory cell 100 depicted in FIG. Figure 5 In this regard, the same reference numerals are used to describe elements of memory cell 500 that are similar to elements of memory cell 100, memory cell 300, and memory cell 350. In addition, for the sake of clarity and brevity, the description of reference method 400 only depicts a portion of memory cell 500, and other portions of memory cell 500 may be described along Figures 21 to 39 The parts shown in FIG.

[0109] In some embodiments, the method 400 is performed as follows: Fig. 20 In some embodiments, some operations of method 400 are performed simultaneously and / or in the order described in the method 400. Fig. 20 In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 400.

[0110] refer to Fig. 20 and Fig.21, method 400 provides, in operation 402, a memory cell 500 including a substrate 501, wherein the substrate 501 includes a plurality of device features (e.g., transistors, diodes, resistors, etc.) formed as part of a FEOL network. Such device features may be formed along a major surface of the substrate 501. The substrate 501 may include a semiconductor material, such as a bulk semiconductor, a semiconductor-on-insulator (SOI), or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the substrate 501 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP) and / or indium gallium arsenide phosphide (GaInAsP); other suitable materials; or combinations thereof.

[0111] The substrate 501 may include a middle-end-of-line (MEOL) network of features for interconnecting the FEOL network with the BEOL network, within which a plurality of BEOL SRAM cells (e.g., memory cell 100, memory cell 300, and memory cell 350) are provided. The MEOL network may include various contact features, such as source / drain contacts and gate contacts, coupled to device features of the FEOL network. For purposes of clarity, device features of the FEOL and MEOL networks are omitted in the depicted embodiment.

[0112] Still refer to Fig. 20 and Fig.21, the method 400 forms a first patterned dielectric layer 202a over the substrate 501 in operation 404, wherein the first patterned dielectric layer 202a includes trenches 502 and 503. The first patterned dielectric layer 202a can be an interlayer dielectric (ILD) layer or an intermetal dielectric (IMD) layer, and includes any suitable dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a low-k dielectric material (a dielectric material having a dielectric constant less than that of silicon oxide (which is about 3.9)), the like, or a combination thereof. The first patterned dielectric layer 202a may be formed using a series of deposition, lithography, and etching processes, which include depositing a dielectric layer over the substrate 501 (by processes such as spin coating, chemical vapor deposition (CVD), flow CVD, etc.); forming a photoresist layer (not depicted) over the dielectric layer; exposing the photoresist layer to a suitable light source; developing the photoresist layer to form a patterned photoresist layer; etching the dielectric layer using the patterned photoresist layer as an etch mask to form the first patterned dielectric layer 202a; and then removing the patterned photoresist layer by a suitable method such as photoresist stripping or plasma ashing.

[0113] refer to Fig. 20 and Fig. 22 , method 400 forms n-channel layers 212 and 232 in trenches 502 and 503, respectively, at operation 406. In some embodiments, other n-channel layers, such as n-channel layers 252, 272, 282, and 284, disposed at the same level as n-channel layers 212 and 232 are also formed at operation 406.

[0114] The n-channel layers 212 and 232 include doped or undoped semiconductor materials, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), tin oxide (SnO2), indium gallium arsenide (InGaAs), carbon nanotube (CNT), transition metal dichalcogenide (TMD), black phosphorus nanoribbon (BPNR), the like, or a combination thereof. To form the n-channel layers 212 and 232, a suitable dielectric material provided herein may be deposited over the first patterned dielectric layer 202a to fill the trenches 502 and 503 by any suitable deposition process, such as CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), the like, or a combination thereof. A planarization process such as a chemical-mechanical polishing / planarization (CMP) process may then be performed to form the n-channel layers 212 and 232 .

[0115] refer to Fig. 20 , Fig.23 and Fig.24 , the method 400 forms conductive features adjacent to the n-channel layers 212 and 232 in the first patterned dielectric layer 202a, including, for example, the second contact 103a, the BBL 109, and the lower portion of the interconnect structure 110, in operation 408. In some embodiments, other conductive features disposed at the same level as the second contact 103a, the BBL 109, and the lower portion of the interconnect structure 110, such as the BL 107, the second contact 103b, the lower portion of the interconnect structure 114, the RBL 303, and the second contact 103c, are also formed in operation 408.

[0116] refer to Fig.23 , the first patterned dielectric layer 202a is patterned at a portion adjacent to the n-channel layers 212 and 232 by any suitable patterning process such as the process described herein for forming the first patterned dielectric layer 202a to form trenches 504, 506, and 508. Fig.24A conductive material is deposited over the first patterned dielectric layer 202 a to fill the trenches 504 to 508 and then planarized by, for example, a CMP process to form the second contact 103 a , the BBL 109 , and the lower portion of the interconnect structure 110 adjacent to the n-channel layers 212 and 232 .

[0117] The conductive material may include any suitable material, such as tungsten (W), aluminum (Al), polysilicon, ruthenium (Ru), cobalt (Co), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), the like, or a combination thereof. The conductive material may be deposited by any suitable method, such as CVD, ALD, PVD, electroplating, electroless plating, the like, or a combination thereof. Prior to depositing the conductive material, a barrier layer and / or a seed layer may first be formed in the trenches 504 to 508.

[0118] refer to Fig. 20 , Fig.25 and Fig.26 , the method 400 forms a second patterned dielectric layer 202b over the memory cell 500 in operation 410. The second patterned dielectric layer 202b exposes at least a portion of the n-channel layers 212 and 232 in the trenches 510 and 512, respectively, and then a gate layer is formed in the trenches 510 and 512. The second patterned dielectric layer 202b has a composition similar to that of the first patterned dielectric layer 202a and can be formed in a manner similar to that of the first patterned dielectric layer 202a.

[0119] In some embodiments, trenches 510 and 512 are the same or substantially the same in size. For example, trenches 510 and 512 are each defined by a length L1 along the X-axis, which corresponds to the length of the gate layer formed in trenches 510 and 512. Each of n-channel layers 212 and 232 is defined by a length L2 along the X-axis, wherein the length L2 is greater than the length L1.

[0120] refer to Fig. 20 and Fig. 27 , the method 400 forms gate layers 206 and 226 in trenches 510 and 512, respectively, at operation 412. In some embodiments, other gate layers (and their corresponding gate dielectric layers), such as gate layers 246, 266, 286, and 288, are also formed at the same level as gate layers 206 and 226 at operation 412.

[0121] Prior to forming gate layers 206 and 226, gate dielectric layers 216 and 218 are first formed in trenches 510 and 512, respectively. After forming gate layers 206 and 226, gate dielectric layers 214 and 220 are subsequently formed in trenches 510 and 512, respectively. In this regard, gate layer 206 is interposed between gate dielectric layers 214 and 216, and gate layer 226 is interposed between gate dielectric layers 218 and 220 along the Z-axis. The resulting gate layer 206 is joined with n-channel layer 212 to form transistor M2, and gate layer 226 is joined with n-channel layer 212 to form transistor M5.

[0122] The gate dielectric layers 214, 216, 218, and 220 may each include any suitable dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), or a high-k dielectric material (a dielectric material having a dielectric constant greater than that of silicon oxide, which is about 3.9), including oxides or silicates of hafnium (Hf), aluminum (Al), zinc (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), the like, or combinations thereof. Non-limiting examples of high-k dielectric materials include hafnium oxide (HfO2) and aluminum oxide (Al2O3). The gate layers 206 and 226 may include any suitable conductive material, such as W, Al, polysilicon, TaN, TiN, the like, or a combination thereof. The gate dielectric layers 214 to 220 and the gate layers 206 and 226 may be formed by any suitable deposition process, such as CVD, ALD, PVD, electroplating, electroless plating, the like, or a combination thereof.

[0123] refer to Fig. 20 , Fig.28 and Fig.29 In operation 414, method 400 vertically extends the lower portion of interconnect structure 110 along the Z axis such that the vertical portion of interconnect structure 110 is disposed between gate layers 206 and 226. In some embodiments, in operation 414, interconnect structure 114 is also vertically extended along the Z axis.

[0124] refer to Fig.28 , the second patterned dielectric layer 202b is first patterned to form a trench 514 between the n-channel layers 212 and 232, thereby exposing a lower portion of the interconnect structure 110. The trench 514 may be formed by a patterning process similar to the patterning process for forming the first patterned dielectric layer 202a. Fig.29 A conductive material having a composition consistent with the lower portion of the interconnect structure 110 is deposited over the second patterned dielectric layer 202b to fill the trench 514. A planarization process may then be performed to form the vertically extending interconnect structure 110.

[0125] refer to Fig. 20 , Fig.30 and Fig.31 , the method 400 forms a third patterned dielectric layer 202c over the gate dielectric layers 214 and 220 in operation 416. Fig.30 , first depositing a dielectric layer as a blanket layer over the memory cell 500, and then, referring to Fig.31 , the dielectric layer is patterned to form trench 518. The third patterned dielectric layer 202c may include a dielectric material similar to the dielectric material of the first patterned dielectric layer 202a, and may be deposited and patterned in a manner similar to the first patterned dielectric layer 202a. It should be noted that the third patterned dielectric layer 202c only exposes the gate layer 206 (and its corresponding gate dielectric layer) above the n-channel layer 212, and does not expose the gate layer 226 (or its corresponding gate dielectric layer) above the n-channel layer 232. In the disclosed embodiment, the trench 518 corresponds to the location of the p-channel layer 210 formed above the gate layer 206.

[0126] refer to Fig. 20 and Fig.32 In operation 418, method 400 forms p-channel layer 210 in trench 518 to interface with gate layer 206 and gate dielectric layer 214. In some embodiments, other p-channel layers, such as p-channel layer 240, disposed at the same level as p-channel layer 210 are also formed in operation 418.

[0127] The p-channel layer 210 includes a doped or undoped semiconductor material, such as nickel oxide (NiO), copper oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper indium oxide (CuInO2), strontium copper oxide (SrCu2O2), tin oxide (SnO), the like, or a combination thereof. The p-channel layer 210 may be formed by any suitable deposition process, such as CVD, ALD, PVD, the like, or a combination thereof. In the disclosed embodiment, the p-channel layer 210 is bonded to the gate layer 206 and the gate dielectric layer 214 to form the transistor M1. In other words, the transistors M1 and M2 share the gate layer 206 and are arranged in a stacked configuration along the Z axis.

[0128] refer to Fig. 20 and Figures 33 to 38 For example, the method in operation 420 forms additional conductive features coupled to the p-channel layer 210, such as the first contact 101a and the top and lateral portions of the interconnect structure 110. In some embodiments, other conductive features disposed at the same level as the first contact 101a and portions of the interconnect structure 110, such as the first contact 101b and the lateral portions of the interconnect structure 114, are also formed in operation 420.

[0129] For example, refer to Figure 33 to Figure 35 , replacing a portion of the p-channel layer 210 with a conductive material to form the first contact 101a and the top portion of the interconnect structure 110. Fig.33 , firstly forming a dielectric layer having a composition similar to that of the first patterned dielectric layer 202a over the p-channel layer 210, and then Fig.34 As shown in , it is patterned to form trenches 520 and 522 in the fourth patterned dielectric layer 202d. In some embodiments, the portion of the p-channel layer 210 exposed in the trenches 520 and 522 is removed, so that the trench 520 exposes the underlying second patterned dielectric layer 202b, and the trench 522 exposes the underlying interconnect structure 110. Thereafter, referring to Fig.35 , conductive material is deposited in trenches 520 and 522 to respectively form first contact 101a and top portion of interconnect structure 110. The conductive material may include any suitable material, such as one or more of the materials described above with respect to forming first contact 101a and BBL 109.

[0130] refer to Fig.36 and Fig.37 , a fifth patterned dielectric layer 202e is formed over the first contact 101a, the fifth patterned dielectric layer 202e comprising a trench 524 extending laterally from the interconnect structure 110 along the X-axis. The fifth patterned dielectric layer 202e may comprise a dielectric material similar to the dielectric material of the first patterned dielectric layer 202a, and may be formed and patterned in a manner similar to the manner in which the first patterned dielectric layer 202a is formed. Fig.38 , a conductive material having a composition consistent with the composition of interconnect structure 110 is deposited in trench 524 to laterally extend interconnect structure 110. The conductive material may be deposited by any suitable deposition process such as CVD, ALD, PVD, the like, or a combination thereof. In the disclosed embodiment, the lateral portion of interconnect structure 110 extends in both the X-axis and the Y-axis (see Figure 4 , Fig. 9 and Fig.11 ) to couple the transistors M1, M2 and M5 to the common gate (eg, gate layer 246) of the transistors M3 and M4.

[0131] In some embodiments, although not depicted, WL 105a and WL 105b are formed in the fifth patterned dielectric layer 202e such that WL 105a is coupled to the gate layer 226 and WL 105b is coupled to the gate layer 266. For example, WL 105a / 105b may each include a suitable conductive material similar to the conductive material of the second contact 103a and the interconnect structure 110.

[0132] refer to Fig. 20 and Fig.39 , method 400 performs additional operations at operation 422 to complete the formation of memory cell 500. For example, a dielectric layer (not depicted) may be deposited over the lateral portion of interconnect structure 110 to fill trench 524 and then planarized by a CMP process. Thus, the various transistors of memory cell 500 are encapsulated by dielectric layer 202, which refers to a collection of multiple dielectric layers (part of which are in the Fig.39 In some embodiments, additional interconnect structures may be formed to couple the components of the memory cell 500 to adjacent memory cells or portions of peripheral circuits.

[0133] One aspect of the present specification is related to an SRAM cell. The SRAM cell includes a first n-channel layer bonded to a first gate layer to form a first device. The SRAM cell includes a first p-channel layer bonded to the first gate layer to form a second device, the first gate layer being stacked between the first n-channel layer and the first p-channel layer along a first direction. The SRAM cell includes a second n-channel layer bonded to the second gate layer to form a third device, the second gate layer being coupled to a first word line, and the second n-channel layer being coupled to the first n-channel layer along a second direction perpendicular to the first direction. The SRAM cell includes a third n-channel layer bonded to the third gate layer to form a fourth device, the third n-channel layer being separated from the second n-channel layer along a third direction perpendicular to the first direction and the second direction. The SRAM cell includes a second p-channel layer bonded to the third gate layer to form a fifth device, the third gate layer being stacked between the third n-channel layer and the second p-channel layer along the first direction. The SRAM cell includes a fourth n-channel layer bonded to the fourth gate layer to form a sixth device, the fourth gate layer being coupled to a second word line, and the fourth n-channel layer being coupled to the third n-channel layer along the second direction.

[0134] In some embodiments, each of the first n-channel layers, the second n-channel layers, the third n-channel layers, and the fourth n-channel layers includes at least one material selected from the group consisting of indium gallium zinc oxide, zinc oxide, indium oxide, tin oxide, indium gallium arsenide, carbon nanotubes, transition metal dichalcogenides, and black phosphorus nanoribbons.

[0135] In some embodiments, each of the first p-channel layers and the second p-channel layers includes at least one material selected from the group consisting of nickel oxide, copper oxide, copper aluminum oxide, copper gallium oxide, copper indium oxide, strontium copper oxide, tin oxide, and combinations thereof.

[0136] In some implementations, the first device and the second device form a first cross-coupled inverter, and the fourth device and the fifth device form a second cross-coupled inverter.

[0137] In some embodiments, a gate dielectric layer is further included, wherein the gate dielectric layer is respectively located between each of the first n-channel layers, the second n-channel layers, the third n-channel layers, and the fourth n-channel layers and each of the first gate layers, the second gate layers, the third gate layers, and the fourth gate layers, and is respectively located between each of the first p-channel layers and the second p-channel layers and each of the first gate layers and the second gate layers.

[0138] In some embodiments, the first n-channel layer is coupled to the second n-channel layer via a first interconnect structure along the second direction, and the third n-channel layer is coupled to the fourth n-channel layer via a second interconnect structure along the second direction.

[0139] In some embodiments, the first interconnect structure extends along the third direction to be further coupled to the third gate layer, and the second interconnect structure extends along the third direction to be further coupled to the first gate layer.

[0140] In some embodiments, a fifth n-channel layer and a sixth n-channel layer are further included, wherein the fifth n-channel layer is bonded to a fifth gate layer to form a seventh device, the fifth n-channel layer and the sixth n-channel layer are bonded to a sixth gate layer to form a sixth n-channel layer of an eighth device adjacent to the seventh device along the second direction, the sixth gate layer is coupled to a read word line, and the second interconnect structure extends along the third direction to be further coupled to the fifth gate layer.

[0141] In some embodiments, the first p-channel layer is flush with the second p-channel layer along the first direction.

[0142] In some embodiments, the first p-channel layer is flush with the third n-channel layer along the first direction.

[0143] Another aspect of the present specification is related to an SRAM cell. The SRAM cell includes a first n-type metal-oxide-semiconductor (NMOS) device, the first n-type metal-oxide-semiconductor device includes a first channel layer bonded to a first gate layer. The SRAM cell includes a first p-type metal-oxide-semiconductor (PMOS) device, the first p-type metal-oxide-semiconductor device includes a second channel layer bonded to a first gate layer, wherein the first gate layer is interposed between the first channel layer and the second channel layer along a first direction, and wherein the first NMOS device and the first PMOS device form a first inverter. The SRAM cell includes a second NMOS device, the second NMOS device is adjacent to the first NMOS device along a second direction perpendicular to the first direction and includes a third channel layer bonded to the second gate layer. The SRAM cell includes a third NMOS device, the third NMOS device includes a fourth channel layer bonded to a third gate layer, and the fourth channel layer is separated from the third channel layer along a third direction perpendicular to the first direction and the second direction. The SRAM cell includes a second PMOS device, the second PMOS device includes a fifth channel layer bonded to a third gate layer, wherein the third gate layer is interposed between a fourth channel layer and a fifth channel layer along a first direction, and wherein the third NMOS device and the second PMOS device form a second inverter. The SRAM cell includes a fourth NMOS device, the fourth NMOS device is adjacent to the third NMOS device along a second direction and includes a sixth channel layer bonded to the fourth gate layer.

[0144] In some embodiments, the second gate layer is coupled to a first word line; the fourth gate layer is coupled to a second word line; a source / drain of the first p-type metal oxide semiconductor device and a source / drain of the second p-type metal oxide semiconductor device are each coupled to a reference voltage Vdd; and a source / drain of the first n-type metal oxide semiconductor device and a source / drain of the third n-type metal oxide semiconductor device are each coupled to ground Vss.

[0145] In some embodiments, each of the first channel layers, the third channel layers, the fourth channel layers, and the sixth channel layers comprises at least one material selected from the group consisting of indium gallium zinc oxide, zinc oxide, indium oxide, tin oxide, indium gallium arsenide, carbon nanotubes, a variety of transition metal dichalcogenides, black phosphorus nanoribbons, or a plurality of combinations thereof.

[0146] In some embodiments, each of the second channel layers and the fifth channel layers includes at least one material selected from the group consisting of nickel oxide, copper oxide, copper aluminum oxide, copper gallium oxide, copper indium oxide, strontium copper oxide, tin oxide, and combinations thereof.

[0147] In some embodiments, the second channel layer is flush with the top of the fifth channel layer along the first direction.

[0148] In some embodiments, the second channel layer is flush with the fourth channel layer along the first direction.

[0149] In some embodiments, a first interconnect structure is further included to couple the first n-type metal oxide semiconductor device, the first p-type metal oxide semiconductor device and the second n-type metal oxide semiconductor device to the third gate layer; and a second interconnect structure is used to couple the third n-type metal oxide semiconductor device, the second p-type metal oxide semiconductor device and the fourth n-type metal oxide semiconductor device to the first gate layer.

[0150] Another aspect of the present specification is a method of forming a memory cell. The method includes providing a semiconductor substrate including a plurality of devices. The method includes forming a first dielectric layer above the semiconductor substrate. The method includes forming a first channel layer in the first dielectric layer. The method includes forming a first contact and a vertical portion of an interconnect structure adjacent to the first channel layer, such that the first channel layer is interposed between the first contact and the vertical portion of the interconnect structure along a first direction. The method includes forming a gate layer above the first channel layer. The method includes forming a second channel layer above the gate layer, such that the gate layer is interposed between the first channel layer and the second channel layer along a second direction perpendicular to the first direction, the first channel layer and the second channel layer having different conductivity types. The method includes extending the vertical portion of the interconnect structure along a second direction. The method includes forming a third contact adjacent to the second channel layer, such that the second channel layer is interposed between the third contact and the extended vertical portion of the interconnect structure along the first direction. The method includes forming a lateral portion of the interconnect structure extending away from the second channel layer along the first direction.

[0151] In some embodiments, a first gate dielectric layer is formed between the first channel layer and the gate layer; and a second gate dielectric layer is formed between the second channel layer and the gate layer.

[0152] In some embodiments, the first channel layer is bonded to the gate layer to form a pull-down transistor, and the second channel layer is bonded to the gate layer to form a pull-up transistor. The pull-down transistor and the pull-up transistor are coupled to form an inverter of a static random access memory cell.

[0153] Another aspect of the present specification is related to a static random access memory cell. The static random access memory cell includes a static random access memory cell, including: a first n-channel layer coupled to a first contact along a first direction; an interconnect structure including a vertical portion and a horizontal portion, the vertical portion of the interconnect structure being adjacent to the first n-channel layer, wherein the first n-channel layer is interposed between the first contact and the vertical portion of the interconnect structure along the first direction; a first gate layer located above the first n-channel layer; a first p-channel layer located above the first gate layer, wherein the first gate layer is interposed between the first n-channel layer and the first p-channel layer along a second direction perpendicular to the first direction, the vertical portion of the interconnect structure extending along the second direction, the first n-channel layer and the first p-channel layer having a plurality of different conductivity types; a second contact connected to the first contact; the first p-channel layer being adjacent, wherein the first p-channel layer is interposed between the second contact and the vertical portion of the interconnect structure along the first direction, wherein the lateral portion of the interconnect structure extends away from the first p-channel layer along the first direction; a second n-channel layer coupled to the first n-channel layer along the first direction; a second gate layer being adjacent to and located above the second n-channel layer; a third n-channel layer being spaced apart from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer being located above the third n-channel layer; a third gate layer being interposed between the second n-channel layer and the second p-channel layer along the second direction perpendicular to the second direction; a fourth n-channel layer coupled to the third n-channel layer along the first direction; and a fourth gate layer being adjacent to and located above the fourth n-channel layer.

[0154] In some embodiments, the static random access memory cell, wherein the first n-channel layer and the first gate layer are combined to form a pull-down transistor, the first p-channel layer and the first gate layer are combined to form a pull-up transistor, and the pull-down transistor and the pull-up transistor are coupled to form an inverter.

[0155] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A static random access memory unit, characterized in that: include: a first n-channel layer bonded to a first gate layer to form a first device; a first p-channel layer bonded to the first gate layer to form a second device, wherein the first gate layer is stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer bonded to a second gate layer to form a third device, wherein the second gate layer is coupled to a first word line, and the second n-channel layer is coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer bonded to a third gate layer to form a fourth device, wherein the third n-channel layer is separated from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer bonded to the third gate layer to form a fifth device, wherein the third gate layer is stacked between the third n-channel layer and the second p-channel layer along the first direction; and A fourth n-channel layer is bonded to a fourth gate layer to form a sixth device, wherein the fourth gate layer is coupled to a second word line, and the fourth n-channel layer is coupled to the third n-channel layer along the second direction.

2. The static random access memory unit according to claim 1, wherein: A gate dielectric layer is also included, wherein the gate dielectric layer is respectively located between each of the first n-channel layer, the second n-channel layer, the third n-channel layer and the fourth n-channel layer and each of the first gate layer, the second gate layer, the third gate layer and the fourth gate layer, and is respectively located between each of the first p-channel layer and the second p-channel layer and each of the first gate layer and the second gate layer.

3. The static random access memory unit according to claim 1 or 2, characterized in that: The first n-channel layer is coupled to the second n-channel layer through a first interconnection structure along the second direction, and the third n-channel layer is coupled to the fourth n-channel layer through a second interconnection structure along the second direction.

4. The static random access memory unit according to claim 3, wherein: The first interconnect structure extends along the third direction to be further coupled to the third gate layer, and the second interconnect structure extends along the third direction to be further coupled to the first gate layer.

5. The static random access memory unit according to claim 3, wherein: The device further includes a fifth n-channel layer and a sixth n-channel layer, wherein the fifth n-channel layer is bonded to a fifth gate layer to form a seventh device, the sixth n-channel layer is bonded to a sixth gate layer to form an eighth device adjacent to the seventh device along the second direction, the sixth gate layer is coupled to a read word line, and the second interconnect structure extends along the third direction to be further coupled to the fifth gate layer.

6. A static random access memory unit, characterized in that: include: A first n-type metal oxide semiconductor device includes a first channel layer connected to a first gate layer; a first p-type metal oxide semiconductor device, comprising a second channel layer joined to the first gate layer, wherein the first gate layer is interposed between the first channel layer and the second channel layer along a first direction, and wherein the first n-type metal oxide semiconductor device and the first p-type metal oxide semiconductor device form a first inverter; a second n-type metal oxide semiconductor device, adjacent to the first n-type metal oxide semiconductor device along a second direction perpendicular to the first direction and comprising a third channel layer joined to a second gate layer; a third n-type metal oxide semiconductor device, comprising a fourth channel layer joined to a third gate layer, wherein the fourth channel layer is separated from the third channel layer along a third direction perpendicular to the first direction and the second direction; a second p-type metal oxide semiconductor device, comprising a fifth channel layer joined to the third gate layer, wherein the third gate layer is interposed between the fourth channel layer and the fifth channel layer along the first direction, and wherein the third n-type metal oxide semiconductor device and the second p-type metal oxide semiconductor device form a second inverter; and A fourth n-type metal oxide semiconductor device is adjacent to the third n-type metal oxide semiconductor device along the second direction and includes a sixth channel layer joined to a fourth gate layer.

7. The static random access memory unit according to claim 6, wherein: in: The second gate layer is coupled to a first word line; The fourth gate layer is coupled to a second word line; A source / drain of the first p-type metal oxide semiconductor device and a source / drain of the second p-type metal oxide semiconductor device are each coupled to a reference voltage; and A source / drain of the first n-type metal oxide semiconductor device and a source / drain of the third n-type metal oxide semiconductor device are respectively coupled to the ground.

8. The static random access memory unit according to claim 6 or 7, wherein: Also includes: a first interconnect structure for coupling the first n-type metal oxide semiconductor device, the first p-type metal oxide semiconductor device and the second n-type metal oxide semiconductor device to the third gate layer; and A second interconnect structure is used to couple the third n-type metal oxide semiconductor device, the second p-type metal oxide semiconductor device and the fourth n-type metal oxide semiconductor device to the first gate layer.

9. A static random access memory unit, characterized in that: include: a first n-channel layer coupled to a first contact along a first direction; an interconnect structure comprising a vertical portion and a lateral portion, the vertical portion of the interconnect structure being adjacent to the first n-channel layer, wherein the first n-channel layer is interposed between the first contact and the vertical portion of the interconnect structure along the first direction; a first gate layer, located above the first n-channel layer; a first p-channel layer located above the first gate layer, wherein the first gate layer is interposed between the first n-channel layer and the first p-channel layer along a second direction perpendicular to the first direction, the vertical portion of the interconnect structure extends along the second direction, and the first n-channel layer and the first p-channel layer have a plurality of different conductivity types; a second contact adjacent to the first p-channel layer, wherein the first p-channel layer is interposed between the second contact and the vertical portion of the interconnect structure along the first direction, wherein the lateral portion of the interconnect structure extends away from the first p-channel layer along the first direction; a second n-channel layer coupled to the first n-channel layer along the first direction; a second gate layer, adjacent to and located above the second n-channel layer; a third n-channel layer, spaced apart from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer located above the third n-channel layer; a third gate layer interposed between the second n-channel layer and the second p-channel layer along a direction perpendicular to the second direction; a fourth n-channel layer coupled to the third n-channel layer along the first direction; and A fourth gate layer is adjacent to and located above the fourth n-channel layer.

10. The static random access memory unit according to claim 9, wherein: in The first n-channel layer is joined to the first gate layer to form a pull-down transistor, the first p-channel layer is joined to the first gate layer to form a pull-up transistor, and the pull-down transistor and the pull-up transistor are coupled to form an inverter.

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