Test board
By setting up multiple functional test lines and the first disk on the functional test area of the test board, and setting up the second disk at the edge of the test area to be tested, the problem of limited application scope of traditional test boards is solved, and flexible adaptation to different chip pin arrangement methods is achieved, and design and manufacturing costs are reduced.
Patent Information
- Application Number
- CN202421033081.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-05-20
- Estimated Expiration
- 2034-05-13
AI Technical Summary
The scope of application of traditional test boards is limited, resulting in increased design time, manufacturing time and cost, and it is impossible to adapt to functional testing of different chip pin arrangement methods.
A test board is designed, including a substrate, a functional test area and a test area. A plurality of functional test lines are provided on the functional test area. Several first pads are arranged in the first direction on each functional test line. The second pad at the edge of the test area is used to connect the functional pins and the first pads of the chip to be tested.
Through this design, the test board can adapt to the arrangement of various functional pins, which improves the scope of application of the test board and reduces design time, manufacturing time and cost.
Smart Images
Figure CN222887709U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductors, and particularly to a test board. Background Art
[0002] When verifying chip products, the functional test lines of the traditional test board are fixedly arranged in one-to-one correspondence with the chip pins. Therefore, when performing functional tests on chips with different pin arrangements, different test boards are required, and the applicable range of the test board is limited, which will lead to an increase in the design time, manufacturing time, and cost of the test board.
[0003] Therefore, how to expand the applicable range of the test board, reduce the design time, manufacturing time, and cost of the test board has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Utility Model
[0004] The utility model provides a test board to solve the problem of how to expand the applicable range of the test board and reduce the design time, manufacturing time, and cost of the test board.
[0005] According to a first aspect of the utility model, a test board is provided, including:
[0006] A substrate, the substrate includes a functional test area and a to-be-tested area, and the to-be-tested area is used for placing a to-be-tested chip;
[0007] A plurality of mutually discrete functional test lines located in the functional test area, the plurality of functional test lines are parallel to a first direction, and each functional test line includes a plurality of first pads arranged along the first direction;
[0008] A plurality of second pads located at the edge of the to-be-tested area, each second pad is used for connecting to any functional pin of the to-be-tested chip, and each second pad is used for connecting to any first pad.
[0009] Optionally, the number of the functional test areas is multiple, the to-be-tested area is located between adjacent functional test areas, and the to-be-tested area and the functional test area are arranged along a second direction, and the second direction is perpendicular to the first direction.
[0010] Optionally, the distance between adjacent first pads on each functional test line is: 0.30 mm to 2.54 mm.
[0011] Optionally, the functional test line further includes a lead-out end, the lead-out end has a third pad, and the functional test lines in different functional test areas are connected through the third pad.
[0012] Optionally, the edge of the to-be-tested chip has a plurality of functional pins, and each functional pin is respectively connected to the corresponding second pad.
[0013] Optionally, on each of the function test lines, the number of the first pads is determined according to the number of the function pins of the chip under test.
[0014] Optionally, the number of the first pads on each of the function test lines is: N / n; where N is the number of the function pins of the chip under test, and n is the number of function test areas.
[0015] Optionally, the number of the function test lines on each of the function test lines is: N; where N is the number of the function pins of the chip under test and N ranges from 2 to 128.
[0016] Optionally, the test board further includes:
[0017] A plurality of wires, and each of the second pads is connected to any one of the first pads through a corresponding wire.
[0018] Optionally, the plurality of wires are movably connected to each of the second pads and the first pads.
[0019] Compared with the prior art, the technical solution of the present utility model has the following advantages:
[0020] A test board provided by the present utility model arranges a plurality of first pads along the first direction on each of the function test lines, so that: the function pins can find the first pads corresponding to their functions on the function test lines along the second direction perpendicular to the first direction; thus, the test board can be applicable to various arrangements of function pins. Therefore, the technical solution provided by the present utility model improves the applicable range of the test board, and solves the problems of limited applicability of the test board, long design time, long manufacturing time and high cost of the test board.
[0021] Further, the present utility model further proposes to arrange N / n first pads on each function test line, and in each function test area, each function test line is provided with the plurality of first pads arranged along the first direction, so that on each function test line, each function pin can find the first pad corresponding to its function along the second direction; thus, for any arrangement of function pins, the test board can test the test board with any pin arrangement by changing the first pads connected to the chip under test on each function test line. Description of the Drawings
[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0023] Figure 1 And Figure 2 is a schematic structural diagram of a test board provided in a typical example of the present invention;
[0024] Explanation of reference numerals:
[0025] 1 - Test board;
[0026] 10 - Functional test area;
[0027] 101 - Functional test line;
[0028] 1011 - First pad;
[0029] 1012 - Third pad;
[0030] 11 - Area to be tested;
[0031] 110 - Chip to be tested;
[0032] 1101 - Functional pin;
[0033] 111 - Second pad. Detailed implementation manners
[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0035] In the description, claims and the above-mentioned drawings of the present utility model, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. The terms "on" and "above" and any variations thereof are intended to describe the positional relationship and do not represent a direct contact relationship between the described objects.
[0036] As described in the background art, the applicability of the test board is limited, and the design time, manufacturing time and cost of the test board are high.
[0037] The functional test lines of the traditional test board are fixedly arranged in one-to-one correspondence with the chip pins. For chips of the same package form, the pin arrangements are often diverse. Therefore, when verifying the functions of chip products with chips having different pin arrangements, different test boards are required to correspond to different pin arrangement methods, resulting in a narrow applicability of the test board, which will increase the design time, manufacturing time and cost of the test board.
[0038] To solve the above problems, the present utility model provides a test board structure, including a substrate. The substrate includes a functional test area and a to-be-tested area for placing the to-be-tested chips. A number of mutually discrete functional test lines are located in the functional test area. The functional test lines are parallel to a first direction, and each functional test line includes a number of first pads arranged along the first direction. A number of second pads are located at the edge of the to-be-tested area. Each second pad is used to connect to any functional pin of the to-be-tested chip and is used to connect to any first pad.
[0039] In the above technical solution provided by the present utility model, by arranging a number of first pads arranged along the first direction in a number of mutually discrete functional test lines, the functional pins can find the first pads corresponding to their functions on the functional test lines. Thus, the test board can be applicable to various pin arrangement methods of functional pins. Therefore, the technical solution provided by the present utility model improves the applicable range of the test board and solves the problems of limited applicability of the test board, long design time, long manufacturing time and high cost.
[0040] The technical solution of the present utility model will be described in detail below with specific embodiments. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0041] The present utility model provides a test board, including: a substrate, the substrate includes a functional test area and a to-be-tested area, the to-be-tested area is used for placing a to-be-tested chip; several mutually discrete functional test lines located in the functional test area, the several functional test lines are parallel to a first direction, and each of the functional test lines includes several first pads arranged along the first direction; several second pads at the edge of the to-be-tested area, each of the second pads is used to connect to any functional pin of the to-be-tested chip, and each of the second pads is used to connect to any first pad.
[0042] The technical solution provided by the present utility model, by arranging several first pads arranged along the first direction on each of the functional test lines, enables: the functional pins can find the first pads corresponding to their functions on the functional test lines along a second direction perpendicular to the first direction; thus, the test board can be applicable to various arrangements of functional pins. Therefore, the technical solution provided by the present utility model improves the applicable range of the test board and solves the problems of limited applicability of the test board, long design time, long manufacturing time and high cost of the test board.
[0043] Figure 1 It is a schematic structural diagram of a test board according to an embodiment of the present utility model.
[0044] The test board 1 includes: a substrate, the substrate includes a functional test area 10 and a to-be-tested area 11, and the to-be-tested area 11 is used for placing a to-be-tested chip 110.
[0045] In one embodiment, the number of the functional test areas 10 is multiple, the to-be-tested area 11 is located between adjacent functional test areas 10, and the to-be-tested area 11 and the functional test areas 10 are arranged along a second direction. Wherein, the second direction is parallel to the surface of the substrate. In one embodiment, the number of the functional test areas 10 is more than 2.
[0046] Several mutually discrete functional test lines 101 located in the functional test area 10, the several functional test lines 101 are parallel to a first direction; the first direction is perpendicular to the second direction.
[0047] In one embodiment, the functional test lines 101 are parallel to each other, and each of the functional test lines 101 is parallel to the first direction.
[0048] In one embodiment, the edge of the to-be-tested chip 110 has several functional pins.
[0049] In one embodiment, each functional pin 1101 corresponds to a functional test line 101 for testing the corresponding function of the chip under test 110, and the total number of functional test lines in all the functional test areas 10 on the substrate is equal to the total number of functional pins 1101 of the chip under test 110.
[0050] In one embodiment, the number of the functional test lines 101 in each of the functional test areas 10 is: N / n, where N is the number of the functional pins 1101 of the chip under test 110, and n is the number of the functional test areas 10.
[0051] In a specific example, the number of the functional pins 1101 in the chip under test is 8, 16, 32, etc., and the number of the functional test lines 101 in each of the functional test areas 10 corresponding thereto is 4, 8, 16, etc. For example: Figure 1 The functional pins 1101 shown in: 1 to 8; the functional test lines 101: A to H; the second pads 111: a to h.
[0052] Each of the functional test lines 101 includes a plurality of first pads 1011 arranged along the first direction.
[0053] In each functional test area 10, at least a plurality of the functional test lines 101 are provided with the plurality of the first pads 1011 arranged along the first direction, so that on at least a plurality of the functional test lines 101, a plurality of the functional pins 1101 can all find the first pads 1011 corresponding to their functions along the second direction; thus, for at least a plurality of the arrangement modes of the functional pins 1101, the test board 1 can test the test board 1 with at least a plurality of the pin arrangement modes by changing the first pads 1011 connected to the chip under test 110 on the corresponding functional test lines 101, thereby improving the applicable range of the test board 1.
[0054] In one embodiment, on each of the functional test lines 101, the number of the first pads 1011 is determined according to the number of the functional pins 1101 of the chip under test.
[0055] In one embodiment, the number of the first pads 1011 on each of the functional test lines 101 is: N / n.
[0056] When N / n first pads 1011 are set on each functional test line 101, in each functional test area 10, the several first pads 1011 arranged along the first direction are set on each functional test line 101, so that on each functional test line 101, each functional pin 1101 can find the first pad 1011 corresponding to its function along the second direction; thus, for any arrangement of functional pins 1101, the test board 1 can test the test board 1 with any pin arrangement by changing the first pads 1011 connected to the chip under test 110 on each functional test line 101.
[0057] In one embodiment, the number of functional test lines on each of the functional test lines is: N; where N is the number of functional pins of the chip under test, and N is from 2 to 128.
[0058] In one embodiment, the distance between adjacent first pads 1011 on each functional test line 101 is the same as the distance between adjacent functional pins 1101 in the chip under test 110.
[0059] In one implementation, the distance between adjacent first pads 1011 on each functional test line 101 is: 0.30 - 2.54 mm.
[0060] In one embodiment, the test board 1 further includes: several second pads 111 located at the edge of the area under test 11. Each of the second pads 111 is used to connect to any functional pin of the chip under test 110, and each of the second pads 111 is used to connect to any first pad 1011.
[0061] In one embodiment, several functional pins at the edge of the chip under test 110 are respectively connected to the corresponding second pads 111.
[0062] In one embodiment, the test board 1 further includes: several wires. Each of the second pads 111 is connected to any first pad 1011 through the corresponding wire.
[0063] In one embodiment, the functional test line 101 further includes a lead-out end, and the lead-out end has a third pad 1012. The functional test lines 101 in different functional test areas 10 are connected through the third pad 1012, so that each functional circuit forms a complete loop for testing various functions of the chip under test 110.
[0064] In one implementation, a plurality of the wires are movably connected between each of the second welds and the first pad 1011. After the test is completed, the plurality of wires can also be disassembled to connect to a new chip under test 110 to perform tests on other chips under test 110 with the same or different arrangement methods.
[0065] According to actual requirements, the technical solution provided by the present utility model can prepare different test boards, which are respectively applicable to chips under test with different pin arrangement methods.
[0066] In summary, a test board provided by the present utility model, by arranging a plurality of first pads arranged along the first direction on each of the functional test lines, is used to flexibly match and apply to chips under test with various arrangements of functional pins, improving the applicable range of the test board and solving the problems of limited applicability of the test board, long design time, long manufacturing time, and high cost of the test board.
[0067] In a typical example of the present utility model, the structure of the test board 1 is as Figure 2 shown ( Figure 2 illustrated by taking a test board with 4 first pads as an example), the test board 1 includes: a substrate, the substrate includes 2 functional test areas 10 and 1 area under test 11, the area under test 11 and the functional test areas 10 are arranged in the vertical direction, the area under test 11 is located between the functional test areas 10, and a chip under test 110 is placed in the area under test 11. Among them, the edge of the chip under test 110 has functional pins 1101: 1 to 8.
[0068] Two functional test lines 101: A to H that are mutually separated and parallel to the horizontal direction are provided in each of the two functional test areas 10. Each of the functional test lines 101 includes 4 first pads 1011 arranged along the horizontal direction.
[0069] Second pads 111a to d and e to h are provided at the edge of the area under test 11 and are respectively close to the two functional test areas 10. Each of the second pads 111 is used to connect to the functional pins 1101: 1 to 4 and 5 to 8 of the chip under test 110 in sequence, and each of the second pads 111a to h is connected to the first pads 1011A to H in sequence through corresponding wires.
[0070] The functional test line 101 further includes an extraction end, the extraction end has a third pad 1012, and the functional test lines 101 with the same function in different functional test areas 10 are connected through the third pad 1012, so that each functional circuit forms a complete loop.
[0071] In this specific example, for the chip under test with 8 functional pins, in each functional test area, 4 first pads arranged horizontally are provided on each functional test line, so that each functional pin in the chip under test can find the first pad corresponding to its function along the vertical direction on any functional test line; thus, for any arrangement of functional pins, the test board can test the chip under test with any pin arrangement by changing the first pads connected to the chip under test on each functional test line. In Figure 2 it, by providing 4 first pads arranged horizontally on each of the functional test lines, it is used to flexibly match and apply the 8-pin chips under test with various arrangements of functional pins, improving the applicable range of the test board for 8-pin chips under test, and can solve the problems of limited applicability of the test board, long design time, long manufacturing time and high cost of the test board.
[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A test board, characterized in that: include: A substrate, the substrate comprising a functional test area and a test area, the test area being used to place a chip to be tested; A plurality of mutually independent functional test lines located in the functional test area, wherein the plurality of functional test lines are parallel to a first direction, and each of the functional test lines comprises a plurality of first pads arranged along the first direction; A plurality of second pads are located at the edge of the test area, each of the second pads is used to be connected to any functional pin of the test chip, and each of the second pads is used to be connected to any first pad.
2. The test board according to claim 1, characterized in that: There are a plurality of functional test areas, the areas to be tested are located between adjacent functional test areas, and the areas to be tested and the functional test areas are arranged along a second direction, which is perpendicular to the first direction.
3. The test board according to claim 1, characterized in that: The distance between adjacent first pads on each of the functional test lines is 0.30 mm to 2.54 mm.
4. The test board according to claim 1, characterized in that: The functional test line also includes a lead-out end having a third pad, and the functional test lines in different functional test areas are connected via the third pad.
5. The test board according to claim 1, characterized in that: The edge of the chip to be tested has a plurality of functional pins, and each of the functional pins is connected to a corresponding second pad.
6. The test board according to claim 5, characterized in that: On each of the functional test lines, the number of the first pads is determined according to the number of the functional pins of the chip to be tested.
7. The test board according to claim 6, characterized in that: The number of the first pads on each of the functional test lines is: N / n; wherein N is the number of functional pins of the chip to be tested, and n is the number of functional test areas.
8. The test board according to claim 7, characterized in that: The number of the functional test lines on each of the functional test lines is: N; wherein N is the number of functional pins of the chip to be tested and is in a range of 2 to 128.
9. The test board according to claim 1, characterized in that: Also includes: A plurality of wires, each of the second pads is connected to any of the first pads through the corresponding wire.
10. The test board according to claim 9, characterized in that: A plurality of the conductive wires are movably connected to the second solder pads and the first solder pads.