Packaging structure

Abstract

The utility model discloses a packaging structure, which comprises a first metal frame, a second metal frame, an insulating layer, a first bonding layer and a chip to be packaged, the second metal frame is arranged on the side, away from the first metal frame, of the to-be-packaged chip, the second metal frame comprises at least two first sub-frames which are insulated from each other, and the surface, close to the to-be-packaged chip, of each first sub-frame is provided with a protruding part; the surface, adjacent to the second metal frame, of the to-be-packaged chip is provided with a first chip pin; the protruding parts are electrically connected with the first chip pins in a one-to-one correspondence manner; the insulating layer is arranged between the to-be-packaged chip and the second metal frame, and the first metal frame and the second metal frame are fixedly connected together through the first bonding layer. According to the utility model, double-sided rapid heat dissipation of the to-be-packaged chip is realized, hot melting of the packaging structure is improved, damage caused by over-high transient temperature of the to-be-packaged chip is avoided, plastic deformation of the packaging structure is reduced, and reliability of the packaging structure is improved.

Description

Technical Field

[0001] The utility model relates to the field of packaging technology, and particularly relates to a packaging structure. Background Art

[0002] Figure 1 It is a schematic diagram of a packaging structure. Figure 2 It is a schematic diagram of another packaging structure. Refer to Figure 1 In the existing packaging structure, the chip 1 to be packaged transfers heat to the frame through the copper clip 10 for heat dissipation. Refer to Figure 2 The chip 1 to be packaged transfers heat to the frame through the bump 11 for heat dissipation. However, through heat dissipation by the copper clip 10 and the bump 11, the number of heat dissipation channels is small, the path is long, and the system heat dissipation effect is not good. Summary of the Utility Model

[0003] The utility model provides a packaging structure, which realizes double-sided and rapid heat dissipation of the chip to be packaged, improves the heat melting of the packaging structure, avoids damage caused by too high transient temperature of the chip to be packaged, reduces the plastic deformation of the packaging structure, and improves the reliability of the packaging structure.

[0004] According to one aspect of the utility model, an embodiment of the utility model provides a packaging structure, including:

[0005] A first metal frame, a second metal frame, an insulating layer, a first bonding layer and a chip to be packaged;

[0006] Wherein, the first metal frame includes a receiving groove, and the chip to be packaged is arranged in the receiving groove;

[0007] The second metal frame is arranged on the side of the chip to be packaged away from the first metal frame. The second metal frame includes at least two mutually insulated first sub-frames. Each surface of the first sub-frame adjacent to the chip to be packaged has a protruding portion; the surface of the chip to be packaged adjacent to the second metal frame has a first chip pin; the protruding portion is electrically connected to the first chip pin in a one-to-one correspondence;

[0008] The insulating layer is arranged between the chip to be packaged and the second metal frame, and the first metal frame and the second metal frame are fixedly connected through the first bonding layer.

[0009] Optionally, the surface of the chip to be packaged adjacent to the first metal frame further includes a second chip pin, and the second metal frame further includes a second sub-frame;

[0010] The second chip pin is electrically connected to the first metal frame through a first conductive adhesive layer, and the first metal frame is electrically connected to the second sub-frame.

[0011] Optionally, the first metal frame is electrically connected to the second sub-frame through a second conductive adhesive layer or a welding layer.

[0012] Optionally, the chip to be encapsulated is fixedly connected to the first metal frame through a second bonding layer.

[0013] Optionally, the insulating layer is also located between the first metal frame and the second metal frame; the vertical projection of the insulating layer on the first metal frame covers the receiving groove, and the area of the vertical projection of the insulating layer on the first metal frame is larger than the area of the receiving groove.

[0014] Optionally, the depth of the receiving groove is greater than or equal to the thickness of the chip to be encapsulated.

[0015] Optionally, the thickness of the insulating layer is greater than the thickness of the first bonding layer.

[0016] Optionally, the thickness of the insulating layer is greater than 20 microns;

[0017] The thickness of the first bonding layer is greater than or equal to 10 microns and less than or equal to 20 microns.

[0018] Optionally, the thickness of the second bonding layer is greater than or equal to 7 microns and less than or equal to 25 microns.

[0019] Optionally, the outer side surface of the second metal frame is flush with the outer side surface of the first metal frame.

[0020] In the embodiment of the present utility model, the first metal frame includes a receiving groove, the chip to be encapsulated is disposed in the receiving groove, the second metal frame is disposed on a side of the chip to be encapsulated away from the first metal frame, the insulating layer is disposed between the chip to be encapsulated and the second metal frame, and the first metal frame and the second metal frame are fixedly connected together through a first bonding layer, that is, the chip to be encapsulated is disposed in the receiving space between the first metal frame and the second metal frame. The front surface of the chip to be encapsulated can dissipate heat through the second metal frame, and the back surface of the chip can dissipate heat through the first metal frame, realizing double-sided rapid heat dissipation of the chip to be encapsulated. Moreover, the first metal frame and the second metal frame serve as encapsulation frames, having a relatively high melting point and no plastic encapsulant coating, improving the heat melting of the encapsulation structure, avoiding damage caused by excessive transient temperature of the chip to be encapsulated, reducing the plastic deformation of the encapsulation structure, and improving the reliability of the encapsulation structure.

[0021] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present utility model, nor is it used to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 is a schematic diagram of a packaging structure;

[0024] Figure 2 is a schematic diagram of another packaging structure;

[0025] Figure 3 is a sectional view of a packaging structure provided by an embodiment of the present utility model;

[0026] Figure 4 is a top view of a packaging structure provided by an embodiment of the present utility model;

[0027] Figure 5 is a sectional view of yet another packaging structure provided by an embodiment of the present utility model;

[0028] Figure 6 is a schematic diagram of a first metal frame and a second metal frame provided by an embodiment of the present utility model;

[0029] Figure 7 is a schematic diagram of a chip to be packaged attached to a receiving groove provided by an embodiment of the present utility model. Detailed implementation manners

[0030] To enable those skilled in the art to better understand the solutions of the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present utility model.

[0031] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present utility model are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" any variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] Figure 3 is a cross-sectional view of a packaging structure provided by an embodiment of the present utility model. Figure 4 is a top view of a packaging structure provided by an embodiment of the present utility model. Figures 3 - 4 shows a packaging structure, see Figure 3 and Figure 4 . The packaging structure includes: a first metal frame 2, a second metal frame 3, an insulating layer 4, a first bonding layer 5, and a chip to be packaged 1; wherein, the first metal frame 2 includes a receiving groove 20, and the chip to be packaged 1 is disposed in the receiving groove 20; the second metal frame 3 is disposed on a side of the chip to be packaged 1 away from the first metal frame 2, and the second metal frame 3 includes at least two mutually insulated first sub-frames 30, and each first sub-frame 30 has a protrusion 31 on a surface adjacent to the chip to be packaged 1; the chip to be packaged 1 has a first chip pin 7 on a surface adjacent to the second metal frame 3; the protrusion 31 is electrically connected to the first chip pin 7 in a one-to-one correspondence; the insulating layer 4 is disposed between the chip to be packaged 1 and the second metal frame 3, and the first metal frame 2 and the second metal frame 3 are fixedly connected through the first bonding layer 5.

[0033] Among them, the chip to be packaged 1 can be a power device. The first metal frame 2 and the second metal frame 3 are used to protect the chip to be packaged 1, dissipate heat, and electrically connect the chip to be packaged 1 to external components. The second metal frame 3 can include two mutually insulated first sub-frames 30, or can include three first sub-frames 30. The protrusion 31 is used to be electrically connected to the first chip pin 7 of the chip to be packaged 1, and the chip to be packaged 1 performs signal interaction with external components through the protrusion 31 and the second metal frame 3. The material used for the insulating layer 4 can be an insulating material such as ceramic, and the insulating layer 4 can play a role in insulation and stress buffering. The side wall of the chip to be packaged 1 and the receiving groove 20 may be in contact or may not be in contact.

[0034] In the embodiment of the present utility model, the first metal frame 2 includes a receiving groove 20. The chip to be encapsulated 1 is disposed in the receiving groove 20. The second metal frame 3 is disposed on the side of the chip to be encapsulated 1 away from the first metal frame 2. The insulating layer 4 is disposed between the chip to be encapsulated 1 and the second metal frame 3. The first metal frame 2 and the second metal frame 3 are fixedly connected together through a first bonding layer 5. That is, the chip to be encapsulated 1 is disposed in the receiving space between the first metal frame 2 and the second metal frame 3. The front surface of the chip to be encapsulated 1 can dissipate heat through the second metal frame 3, and the back surface of the chip can dissipate heat through the first metal frame 2, realizing double-sided and rapid heat dissipation of the chip to be encapsulated 1. Moreover, the first metal frame 2 and the second metal frame 3 serve as encapsulation frames, having a relatively high melting point and no plastic encapsulant coating, improving the heat melting of the encapsulation structure, avoiding damage caused by excessive transient temperature of the chip to be encapsulated, reducing the plastic deformation of the encapsulation structure, and improving the reliability of the encapsulation structure.

[0035] Figure 5 is a cross-sectional view of another encapsulation structure provided by the embodiment of the present utility model. Refer to Figure 5 Optionally, on the basis of the above embodiment, the surface of the chip to be encapsulated 1 adjacent to the first metal frame 2 further includes a second chip pin 8, and the second metal frame 3 further includes a second sub-frame 32;

[0036] The second chip pin 8 is electrically connected to the first metal frame 2 through a first conductive adhesive layer 9, and the first metal frame 2 is electrically connected to the second sub-frame 32.

[0037] Among them, the second chip pin 8 is electrically connected to an external component through the first metal frame 2, the first conductive adhesive layer 9, and the second sub-frame 32. By electrically connecting the second chip pin 8 on the back surface of the chip to be encapsulated 1 to the second sub-frame 32, all pins of the chip to be encapsulated 1 are electrically connected to external components through the second metal frame 3, facilitating the subsequent use of the encapsulation structure.

[0038] Refer to Figure 5 Optionally, on the basis of the above embodiment, the first metal frame 2 is electrically connected to the second sub-frame 32 through a second conductive adhesive layer 10 or a welding layer.

[0039] Specifically, the welding layer can be a solder layer. By connecting the first metal frame 2 and the second sub-frame 32 through the second conductive adhesive layer 10 or the welding layer, while ensuring the electrical connection between the first metal frame 2 and the second sub-frame 32, the two can be fixed and sealed, further improving the encapsulation stability.

[0040] Refer to Figure 3 Optionally, on the basis of the above embodiment, the chip to be encapsulated 1 is fixedly connected to the first metal frame 2 through a second bonding layer 6.

[0041] Specifically, when the surface of the chip 1 to be encapsulated adjacent to the first metal frame 2 does not have chip pins, the first metal frame 2 can be directly fixedly connected to the chip 1 to be encapsulated through the second bonding layer 6. The second bonding layer 6 can be made of a material with good thermal conductivity, so that the heat generated by the chip 1 to be encapsulated can be quickly conducted to the first metal frame 2, improving the heat dissipation speed.

[0042] See Figure 3 and Figure 5 Optionally, on the basis of the above embodiments, the insulating layer 4 is also located between the first metal frame 2 and the second metal frame 3; the vertical projection of the insulating layer 4 on the first metal frame 2 covers the receiving groove 20, and the area of the vertical projection of the insulating layer 4 on the first metal frame 2 is larger than the area of the receiving groove 20.

[0043] Among them, the vertical projection of the insulating layer 4 on the first metal frame 2 covers the receiving groove 20, and the area of the vertical projection of the insulating layer 4 on the first metal frame 2 is larger than the area of the receiving groove 20, that is, the insulating layer 4 covers the receiving groove 20 and at least part of the area of the first metal frame 2 surrounding the receiving groove 20. Such a setting makes the insulating layer 4 form a sealed space with the receiving groove 20, and the insulating layer 4 plays a role in sealing and protecting the chip 1 to be encapsulated. In addition, the insulating layer 4 is located between the first metal frame 2 and the second metal frame 3. When pressure is applied to the first metal frame 2 and the second metal frame 3, the insulating layer 4 can play a role in buffering the stress between the first metal frame 2 and the second metal frame 3, preventing the chip 1 to be encapsulated from being damaged.

[0044] See Figure 3 and Figure 5 Optionally, on the basis of the above embodiments, the depth of the receiving groove 20 is greater than or equal to the thickness of the chip 1 to be encapsulated.

[0045] Specifically, if the depth of the receiving groove 20 is less than the thickness of the chip 1 to be encapsulated, the chip 1 to be encapsulated cannot be completely embedded in the groove. When pressure is applied to the first metal frame 2 and the second metal frame 3, it is easy to squeeze the chip 1 to be encapsulated, causing damage to the chip 1 to be encapsulated. By setting the depth of the receiving groove 20 to be greater than or equal to the thickness of the chip 1 to be encapsulated, when pressure is applied to the first metal frame 2 and the second metal frame 3, the first metal frame 2 and the second metal frame 3 can play a supporting role, avoiding damage to the chip 1 to be encapsulated.

[0046] See Figure 3 and Figure 5 Optionally, on the basis of the above embodiments, the thickness of the insulating layer 4 is greater than the thickness of the first bonding layer 5.

[0047] Specifically, the insulating layer 4 plays a role in sealing and buffering stress for the chip 1 to be encapsulated. If the thickness of the insulating layer 4 is too small, it cannot seal the chip 1 to be encapsulated well and cannot buffer stress well. Therefore, by setting the thickness of the insulating layer 4 to be greater than the thickness of the first bonding layer 5, the insulating layer 4 can better seal the chip and buffer stress better, avoiding damage to the chip 1 to be encapsulated.

[0048] See Figure 3 and Figure 5 Optionally, on the basis of the above embodiment, the thickness of the insulating layer 4 is greater than 20 microns; the thickness of the first bonding layer 5 is greater than or equal to 10 microns and less than or equal to 20 microns.

[0049] Specifically, if the thickness of the insulating layer 4 is too large, it may waste materials, increase production costs, and increase the thickness of the encapsulation structure. If the thickness of the insulating layer 4 is too small, it cannot seal the chip 1 to be encapsulated well and cannot buffer stress well. Therefore, by setting the thickness of the insulating layer 4 to be greater than 20 microns, the insulating layer 4 can better seal the chip and buffer stress better, protect the chip 1 to be encapsulated, and can make the encapsulation structure have a smaller thickness, and can also avoid waste of materials.

[0050] If the thickness of the first bonding layer 5 is too large, it may waste materials, increase production costs, and increase the thickness of the encapsulation structure. If the thickness of the first bonding layer 5 is too small, it may reduce the bonding force between the first metal frame 2 and the second metal frame 3. Therefore, by setting the thickness of the first bonding layer 5 to be greater than or equal to 10 microns and less than or equal to 20 microns, the bonding force between the first metal frame 2 and the second metal frame 3 is increased, and the encapsulation structure can have a smaller thickness, and waste of materials is also avoided.

[0051] See Figure 3 and Figure 5 Optionally, on the basis of the above embodiment, the thickness of the second bonding layer 6 is greater than or equal to 7 microns and less than or equal to 25 microns.

[0052] Specifically, if the thickness of the second bonding layer 6 is too large, it may waste materials, increase production costs, and increase the thickness of the encapsulation structure. If the thickness of the second bonding layer 6 is too small, it may reduce the bonding force between the chip 1 to be encapsulated and the first metal frame 2. Therefore, by setting the thickness of the second bonding layer 6 to be greater than or equal to 7 microns and less than or equal to 25 microns, the bonding force between the chip 1 to be encapsulated and the first metal frame 2 is increased, while waste of materials is avoided, and the encapsulation structure can have a smaller thickness.

[0053] See Figure 3 and Figure 5, optionally, based on the above embodiments, the outer side surface of the second metal frame 3 is flush with the outer side surface of the first metal frame 2.

[0054] In the embodiment of the present utility model, by setting the outer side surface of the second metal frame 3 to be flush with the outer side surface of the first metal frame 2, it is ensured that the shape of the encapsulation structure is more regular, stress concentration can be avoided, the structural stability of the encapsulation structure is improved, and the volume of the encapsulation structure can be reduced.

[0055] Figures 6 - 7 shows the formation process of the encapsulation structure, Figure 6 is a schematic diagram of the first metal frame and the second metal frame provided by the embodiment of the present utility model, Figure 7 is a schematic diagram of the chip to be encapsulated provided by the embodiment of the present utility model attached to the receiving groove. Refer to Figure 6 , provide the first metal frame 2 and the second metal frame 3, form a receiving groove 20 on the surface of the first metal frame 2 close to the second metal frame 3, and form an insulating layer 4 and a protruding portion 31 on the surface of the second metal frame 3 close to the first metal frame 2. Refer to Figure 7 , provide a second adhesive layer 6 at the bottom of the receiving groove 20, and attach the surface of the chip 1 to be encapsulated away from the first chip pin 7 in the receiving groove 20 of the first metal frame 2. Refer to Figure 3 , provide a first adhesive layer 5 on the surface of the first metal frame 2 close to the second metal frame 3, attach the second metal frame 3 to the surface of the first metal frame 2, and then pattern the second metal frame 3 to form Figure 3 the encapsulation structure shown.

[0056] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present utility model can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present utility model can be achieved. No limitation is made herein.

[0057] The above specific embodiments do not constitute a limitation to the protection scope of the present utility model. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A packaging structure, characterized in that: include: A first metal frame, a second metal frame, an insulating layer, a first adhesive layer and a chip to be packaged; Wherein, the first metal frame comprises a receiving groove, and the chip to be packaged is arranged in the receiving groove; The second metal frame is arranged on a side of the chip to be packaged away from the first metal frame, the second metal frame comprises at least two mutually insulated first sub-frames, each of the first sub-frames has a protrusion on a surface adjacent to the chip to be packaged; the surface of the chip to be packaged adjacent to the second metal frame has a first chip pin; the protrusion is electrically connected to the first chip pin in a one-to-one correspondence; The insulating layer is disposed between the chip to be packaged and the second metal frame, and the first metal frame and the second metal frame are fixedly connected via the first adhesive layer.

2. The packaging structure according to claim 1, characterized in that: The surface of the chip to be packaged adjacent to the first metal frame further includes a second chip pin, and the second metal frame further includes a second sub-frame; The second chip pin is electrically connected to the first metal frame through a first conductive adhesive layer, and the first metal frame is electrically connected to the second sub-frame.

3. The packaging structure according to claim 2, characterized in that: The first metal frame is electrically connected to the second sub-frame through a second conductive adhesive layer or a welding layer.

4. The packaging structure according to claim 1, characterized in that: The chip to be packaged is fixedly connected to the first metal frame via a second adhesive layer.

5. The packaging structure according to claim 1, characterized in that: The insulating layer is also located between the first metal frame and the second metal frame; the vertical projection of the insulating layer on the first metal frame covers the receiving groove, and the area of ​​the vertical projection of the insulating layer on the first metal frame is larger than the area of ​​the receiving groove.

6. The packaging structure according to claim 1, characterized in that: The depth of the receiving groove is greater than or equal to the thickness of the chip to be packaged.

7. The packaging structure according to claim 1, characterized in that: The thickness of the insulating layer is greater than the thickness of the first adhesive layer.

8. The packaging structure according to claim 7, characterized in that: The thickness of the insulating layer is greater than 20 microns; The thickness of the first bonding layer is greater than or equal to 10 micrometers and less than or equal to 20 micrometers.

9. The packaging structure according to claim 4, characterized in that: The thickness of the second bonding layer is greater than or equal to 7 micrometers and less than or equal to 25 micrometers.

10. The packaging structure according to claim 1, characterized in that: The outer side surface of the second metal frame is flush with the outer side surface of the first metal frame.

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