Full-swing operational amplifier

Abstract

The utility model discloses a full-swing operational amplifier which comprises a first input geminate transistor, a second input geminate transistor, a first current source, a second current source and an adjusting unit. The first end of the first current source is connected with power voltage, the second end of the first current source is connected with the first input geminate transistor to generate first current, the first end of the second current source is connected with ground voltage, and the second end of the second current source is connected with the second input geminate transistor to generate second current. The adjusting unit is connected with the second end of the first current source so as to generate a first adjusting current used for adjusting the current on the first input geminate transistor based on the control of the input signal, and the adjusting unit is connected with the second end of the second current source so as to generate a second adjusting current used for adjusting the current on the second input geminate transistor based on the control of the input signal. According to the full-swing operational amplifier, the range of input signals can be expanded to rail-to-rail, and transconductance stability can be maintained in a wide signal range.

Description

Technical Field

[0001] The utility model belongs to the technical field of operational amplifiers, and particularly relates to a full-swing operational amplifier. Background Art

[0002] Traditional rail-to-rail operational amplifiers use complementary PMOS and NMOS differential pairs as the input stage. In the lower input voltage range, the PMOS differential input pair works and the NMOS differential pair is turned off. In the higher input voltage range, the NMOS differential input pair works and the PMOS differential pair is turned off. In the intermediate input voltage range, both the NMOS and PMOS differential pairs work. Thus, a full-swing amplifier with a wide input range is obtained.

[0003] However, since the input stage of this structure of rail-to-rail operational amplifier has three working states: PMOS or NMOS working alone and working simultaneously, the transconductance is not constant, and the maximum change is 2 times over the entire input range, which has a great impact on the common-mode rejection ratio and stability.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the utility model and should not be regarded as an admission or any form of implication that this information constitutes the prior art already known to those of ordinary skill in the art. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a full-swing operational amplifier that can maintain stable transconductance within a relatively wide input range.

[0006] To achieve the above purpose, a specific embodiment of the utility model provides a full-swing operational amplifier, which includes a first input pair transistor, a second input pair transistor, a first current source, a second current source, and an adjustment unit; the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the first input pair transistor to generate a first current, the first end of the second current source is connected to the ground voltage, and the second end of the second current source is connected to the second input pair transistor to generate a second current; the adjustment unit is connected to the second end of the first current source to generate a first adjustment current for adjusting the current on the first input pair transistor based on the control of the input signal, and the adjustment unit is connected to the second end of the second current source to generate a second adjustment current for adjusting the current on the second input pair transistor based on the control of the input signal; the first input pair transistor and the second input pair transistor are connected to the subsequent circuit.

[0007] In one or more embodiments of the present utility model, the first input pair of transistors includes a first transistor and a second transistor. The first ends of the first transistor and the second transistor are connected to the second end of a first current source. The control ends of the first transistor and the second transistor are respectively used for receiving differential input signals. The second ends of the first transistor and the second transistor are connected to a subsequent stage circuit.

[0008] In one or more embodiments of the present utility model, the second input pair of transistors includes a third transistor and a fourth transistor. The first ends of the third transistor and the fourth transistor are connected to a second current source. The control ends of the third transistor and the fourth transistor are respectively used for receiving differential input signals. The second ends of the third transistor and the fourth transistor are connected to a subsequent stage circuit.

[0009] In one or more embodiments of the present utility model, the adjustment unit includes a first adjustment circuit and a second adjustment circuit. The first adjustment circuit is connected to the second end of the first current source to generate a first adjustment current based on the control of an input signal. The second adjustment circuit is connected to the second end of the second current source to generate a second adjustment current based on the control of the input signal.

[0010] In one or more embodiments of the present utility model, the first adjustment circuit includes a third current source, a first switch unit, and a first current mirror unit. The first end of the third current source is connected to a ground voltage. The second end of the third current source is connected to the first end of the first switch unit to generate a third current. The second end of the first switch unit is connected to the first current mirror unit. The first switch unit is used to control the on-off between the second end of the third current source and the first current mirror unit based on the input signal. The first current mirror unit is connected to the second end of the first current source. The first current mirror unit generates a first adjustment current based on the mirroring of the third current to extract the current on the first input pair of transistors.

[0011] In one or more embodiments of the present utility model, the first current mirror unit includes one or more first current mirrors connected in series between the second end of the first switch unit and the second end of the first current source. The first current mirror is used to generate a first adjustment current based on the mirroring of the third current.

[0012] In one or more embodiments of the present utility model, the second adjustment circuit includes a fourth current source, a second switch unit, and a second current mirror unit. The first end of the fourth current source is connected to the power supply voltage, and the second end of the fourth current source is connected to the first end of the second switch unit to generate a fourth current. The second end of the second switch unit is connected to the second current mirror unit. The second switch unit is used to control the on-off between the second end of the fourth current source and the second current mirror unit based on an input signal. The second current mirror unit is connected to the second end of the second current source, and the second current mirror unit generates a second adjustment current based on the fourth current mirroring to extract the current on the second input pair of transistors.

[0013] In one or more embodiments of the present utility model, the second current mirror unit includes one or more second current mirrors connected in series between the second end of the second switch unit and the second end of the second current source. The second current mirror is used to generate a second adjustment current based on the fourth current mirroring.

[0014] In one or more embodiments of the present utility model, the value of the first adjustment current is half of the second current, and the value of the second adjustment current is half of the first current.

[0015] In one or more embodiments of the present utility model, the subsequent stage circuit includes a folded cascode amplifier.

[0016] Compared with the prior art, the rail-to-rail operational amplifier of the present utility model can extend the range of the input signal to rail-to-rail and maintain the transconductance stable within a wide signal range. When the input signal changes arbitrarily, it can also quickly adjust the transconductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is the circuit schematic diagram of the rail-to-rail operational amplifier in an embodiment of the present utility model.

[0019] Figure 2 It is the circuit schematic diagram of the current compensation unit in an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts shall fall within the protection scope of the present utility model.

[0021] In the specification, "coupled" or "connected" or "linked" includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch, a follower circuit, etc. In addition, in the present utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0022] As Figure 1 shown, a full-swing operational amplifier in an embodiment of the present utility model includes a first input pair of transistors, a second input pair of transistors, a first current source I1, a second current source I2, a post-stage circuit 10, and an adjustment unit 20.

[0023] Among them, the first end of the first current source I1 is connected to the power supply voltage VDD, the second end of the first current source I1 is connected to the first input pair of transistors to generate a first current I1, the first end of the second current source I2 is connected to the ground voltage GND, and the second end of the second current source I2 is connected to the second input pair of transistors to generate a second current I2.

[0024] The adjustment unit 20 is connected to the first input pair of transistors and the first current source I1 to generate a first adjustment current IB1 for adjusting the current on the first input pair of transistors based on the control of the input signal V1, and the adjustment unit 20 is connected to the second input pair of transistors and the second current source I2 to generate a second adjustment current IB2 for adjusting the current on the second input pair of transistors based on the control of the input signal V1.

[0025] The first input pair of transistors and the second input pair of transistors are connected to the post-stage circuit 10.

[0026] Specifically, the first input pair of transistors includes a first transistor M1 and a second transistor M2. The first ends of the first transistor M1 and the second transistor M2 are connected to the second end of a first current source I1 to form a node VX. The control end of the first transistor M1 is used to receive a differential input signal V1, and the control end of the second transistor M2 is used to receive a differential input signal V2. The second ends of the first transistor M1 and the second transistor M2 are connected to a subsequent circuit 10.

[0027] The second input pair of transistors includes a third transistor M3 and a fourth transistor M4. The first ends of the third transistor M3 and the fourth transistor M4 are connected to the second end of a second current source I2 to form a node VY. The control end of the third transistor M3 is used to receive a differential input signal V1, and the control end of the fourth transistor M4 is used to receive a differential input signal V2. The second ends of the third transistor M3 and the fourth transistor M4 are connected to the subsequent circuit 10.

[0028] As Figure 1 shown, the adjustment unit 20 includes a first adjustment circuit 21 and a second adjustment circuit 22. The first adjustment circuit 21 is connected to the second end of the first current source I1 to generate a first adjustment current IB1 based on the control of the input signal V1. The second adjustment circuit is connected to the first end of the second current source I2 to generate a second adjustment current IB2 based on the control of the input signal V1.

[0029] In one embodiment, the first current I1 is equal to the second current I2. The value of the first adjustment current IB1 is half of the second current I2, and the value of the second adjustment current IB2 is half of the first current I1.

[0030] Wherein, the first adjustment circuit 21 includes a third current source I3, a first switch unit, and a first current mirror unit 211. The first end of the third current source I3 is connected to the ground voltage GND, and the second end of the third current source I3 is connected to the first end of the first switch unit to generate a third current I3. The second end of the first switch unit is connected to the first current mirror unit 211. The first switch unit is used to control the on / off between the second end of the third current source I3 and the first current mirror unit 211 based on the input signal V1. The first current mirror unit 211 is connected to the second end (node VX) of the first current source I1. The first current mirror unit 211 mirrors the third current I3 to generate the first adjustment current IB1 to extract the current on the first input pair of transistors.

[0031] The second adjustment circuit 22 includes a fourth current source I4, a second switching unit, and a second current mirror unit 221. The first end of the fourth current source I4 is connected to the power supply voltage VDD, and the second end of the fourth current source I4 is connected to the first end of the second switching unit to generate a fourth current I4. The second end of the second switching unit is connected to the second current mirror unit 221. The second switching unit is used to control the connection and disconnection between the second end of the fourth current source I4 and the second current mirror unit 221 based on the input signal V1. The second current mirror unit 221 is connected to the second end (node VY) of the second current source I2 to mirror and generate a second adjustment current IB2 based on the fourth current I4.

[0032] The first switching unit includes a fifth transistor M5. The first end of the fifth transistor M5 is connected to the second end of the third current source I3, the second end of the fifth transistor M5 is connected to the first current mirror unit 211, and the control end of the fifth transistor M5 is used to receive the input signal V1.

[0033] The second switching unit includes a sixth transistor M6. The first end of the sixth transistor M6 is connected to the second end of the fourth current source I4, the second end of the sixth transistor M6 is connected to the second current mirror unit 221, and the control end of the sixth transistor M6 is used to receive the input signal V1.

[0034] As Figure 2 shown, the first current mirror unit 211 includes two first current mirrors 212 and 213 connected in series between the second end of the fifth transistor M5 and the second end (node VX) of the first current source I1.

[0035] Among them, the first current mirror 212 includes a seventh transistor M7 and an eighth transistor M8. The first ends of the seventh transistor M7 and the eighth transistor M8 are connected to the power supply voltage VDD. The second end, the control end of the seventh transistor M7, and the control ends of the eighth transistor M8 are connected to the second end of the fifth transistor M5. The second end of the eighth transistor M8 is connected to the first current mirror 213.

[0036] The first current mirror 213 includes a ninth transistor M9 and a tenth transistor M10. The first ends of the ninth transistor M9 and the tenth transistor M10 are connected to the ground voltage GND. The second end of the ninth transistor M9 is connected to the second end of the eighth transistor M8. The control end of the ninth transistor M9, the control ends of the tenth transistor M10, and the second end of the tenth transistor M10 are connected to the second end (node VX) of the first current source I1.

[0037] As Figure 2 shown, the second current mirror unit 221 includes two second current mirrors 222 and 223 connected in series between the second end of the sixth transistor M6 and the second end (node VY) of the second current source I2.

[0038] The second current mirror 222 includes an eleventh transistor M11 and a twelfth transistor M12. The first ends of the eleventh transistor M11 and the twelfth transistor M12 are connected to the ground voltage GND. The second end, the control end of the eleventh transistor M11, and the control ends of the twelfth transistor M12 are connected to the second end of the sixth transistor M6. The second end of the twelfth transistor M12 is connected to the second current mirror 223.

[0039] The second current mirror 223 includes a thirteenth transistor M13 and a fourteenth transistor M14. The first ends of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to the power supply voltage VDD. The second end, the control end of the thirteenth transistor M13, and the control ends of the fourteenth transistor M14 are connected to the second end of the twelfth transistor M12. The second end of the fourteenth transistor M14 is connected to the first end (node VY) of the second current source I2.

[0040] In one embodiment, the third current I3 = 0.5 * I2, and the current mirror ratios of the first current mirror 212 and the first current mirror 213 are both 1:1. The fourth current I4 = 0.5 * I1, and the current mirror ratios of the second current mirror 222 and the second current mirror 223 are both 1:1.

[0041] In other embodiments, the current value of the third current I3, the current value of the fourth current I4, and the current mirror ratios of the first current mirror 212, the first current mirror 213, the second current mirror 222, and the second current mirror 223 can all be adjusted, as long as the first adjustment current is 0.5 * I2 and the second adjustment current is 0.5 * I1.

[0042] As Figure 1 shown, the subsequent stage circuit 10 includes a folded cascode amplifier, which is used to superimpose the current signals generated by the first input pair of transistors and the second input pair of transistors and generate an output signal V3.

[0043] Specifically, the folded cascode amplifier includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a fifth current source I5, and a sixth current source I6.

[0044] The first terminal of the fifteenth transistor M15, the first terminal of the sixteenth transistor M16 are connected to the power supply voltage VDD. The second terminal of the fifteenth transistor M15, the first terminal of the seventeenth transistor M17 are connected to the second terminal of the third transistor M3. The second terminal of the sixteenth transistor M16, the first terminal of the eighteenth transistor M18 are connected to the second terminal of the fourth transistor M4. The control terminal of the fifteenth transistor M15, the control terminal of the sixteenth transistor M16 are connected to the second terminal of the seventeenth transistor M17 and the second terminal of the nineteenth transistor M19. The second terminal of the eighteenth transistor M18 is connected to the second terminal of the twentieth transistor M20 to generate an output signal V3. The control terminal of the seventeenth transistor M17 is connected to the control terminal of the eighteenth transistor M18 to receive a first bias voltage VB1.

[0045] The control terminal of the nineteenth transistor M19 is connected to the control terminal of the twentieth transistor M20 to receive a second bias voltage VB2. The first terminal of the nineteenth transistor M19, the first terminal of the fifth current source I5 are connected to the second terminal of the first transistor M1. The first terminal of the twentieth transistor M20, the first terminal of the sixth current source I6 are connected to the second terminal of the second transistor M2. The second terminals of the fifth current source I5, the sixth current source I6 are connected to the ground voltage GND. The fifth current source I5 is used to generate a fifth current I5, and the sixth current source I6 is used to generate a sixth current I6.

[0046] In one embodiment, the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17 and the eighteenth transistor M18 are all PMOS transistors. In other embodiments, the above transistors can also be NMOS transistors or other types of devices, and their connection manners are adjusted adaptively.

[0047] The third transistor M3, the fourth transistor M4, the fifth transistor M5, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the nineteenth transistor M19, the twentieth transistor M20 are all NMOS transistors. In other embodiments, the above transistors can also be PMOS transistors or other types of devices, and their connection manners are adjusted adaptively.

[0048] The first ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are source electrodes.

[0049] The second ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are drain electrodes.

[0050] The control ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are gate electrodes.

[0051] During the actual operation process: when the input signals satisfy V1 < VTHN and V2 < VTHN, where VTHN is the threshold voltage of the NMOS transistor, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 and the fourth transistor M4 are turned off. At this time, the signal is mainly amplified by the first input pair of transistors. The fifth transistor M5 is turned off, and the first adjustment circuit 21 is turned off. At this time, the sum of the tail currents of the first input pair of transistors and the second input pair of transistors is I1.

[0052] When the input signals satisfy VTHN < V1 < VDD - |VTHP| and VTHN < V2 < VDD - |VTHP|, where |VTHP| is the threshold voltage of the PMOS transistor, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on, and the first adjustment circuit 21 and the second adjustment circuit 22 are also turned on simultaneously. At this time, the tail current of the first input pair of transistors is I1 - IB1 = I1 - 0.5 * I2, and the tail current of the second input pair of transistors is I2 - IB2 = I2 - 0.5 * I1, that is, the sum of the tail currents of the first input pair of transistors and the second input pair of transistors is 0.5 * I1 + 0.5 * I2. When I1 = I2, that is, the sum of the tail currents is I1.

[0053] When the input signals satisfy V1 > VDD - |VTHP| and V2 > VDD - |VTHP|, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on. At this time, the signal is mainly amplified by the second input pair of transistors. The second adjustment circuit 22 is turned off. At this time, the sum of the tail currents of the first input pair of transistors and the second input pair of transistors is I2 = I1.

[0054] In summary, when the input signals change arbitrarily, whether the first input pair of transistors and the second input pair of transistors work independently or together, the sum of their tail currents is constant, so that the equivalent transconductance of the input stage of the amplifier can also be kept constant, and the amplifier can maintain stable operation.

[0055] In other embodiments, the control terminals of the fifth transistor M5 and the sixth transistor M6 can also receive the input signal V2, and the working principle and mode of the amplifier do not change.

[0056] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-described exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present utility model. Any reference signs in the claims should not be construed as limiting the claims involved.

[0057] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A full-swing operational amplifier, characterized in that: It includes a first input pair of tubes, a second input pair of tubes, a first current source, a second current source and a regulating unit; The first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the first input pair of transistors to generate a first current, the first end of the second current source is connected to the ground voltage, and the second end of the second current source is connected to the second input pair of transistors to generate a second current; The regulating unit is connected to the second end of the first current source to generate a first regulating current for regulating the current on the first input pair of tubes based on the control of the input signal, and the regulating unit is connected to the second end of the second current source to generate a second regulating current for regulating the current on the second input pair of tubes based on the control of the input signal; The first input pair of tubes and the second input pair of tubes are connected to a subsequent circuit.

2. The full-swing operational amplifier according to claim 1, characterized in that: The first input pair includes a first transistor and a second transistor, the first end of the first transistor and the first end of the second transistor are connected to the second end of the first current source, the control end of the first transistor and the control end of the second transistor are respectively used to receive differential input signals, and the second end of the first transistor and the second end of the second transistor are connected to the subsequent circuit.

3. The full-swing operational amplifier according to claim 1, characterized in that: The second input pair of transistors includes a third transistor and a fourth transistor, the first end of the third transistor and the first end of the fourth transistor are connected to the second current source, the control end of the third transistor and the control end of the fourth transistor are respectively used to receive differential input signals, and the second end of the third transistor and the second end of the fourth transistor are connected to the subsequent circuit.

4. The full-swing operational amplifier according to claim 1, wherein: The regulating unit includes a first regulating circuit and a second regulating circuit, wherein the first regulating circuit is connected to the second end of the first current source to generate a first regulating current based on the control of an input signal, and the second regulating circuit is connected to the second end of the second current source to generate a second regulating current based on the control of the input signal.

5. The full-swing operational amplifier according to claim 4, characterized in that: The first regulation circuit includes a third current source, a first switch unit and a first current mirror unit. The first end of the third current source is connected to the ground voltage, the second end of the third current source is connected to the first end of the first switch unit to generate a third current, the second end of the first switch unit is connected to the first current mirror unit, the first switch unit is used to control the on-off between the second end of the third current source and the first current mirror unit based on an input signal, the first current mirror unit is connected to the second end of the first current source, and the first current mirror unit generates a first regulation current based on the third current mirror to extract the current on the first input pair tube.

6. The full-swing operational amplifier according to claim 5, characterized in that: The first current mirror unit includes one or more first current mirrors connected in series between the second end of the first switch unit and the second end of the first current source, and the first current mirror is used to generate a first regulating current based on a third current mirror.

7. The full-swing operational amplifier according to claim 4, characterized in that: The second regulation circuit includes a fourth current source, a second switch unit and a second current mirror unit. The first end of the fourth current source is connected to the power supply voltage, the second end of the fourth current source is connected to the first end of the second switch unit to generate a fourth current, the second end of the second switch unit is connected to the second current mirror unit, the second switch unit is used to control the on-off between the second end of the fourth current source and the second current mirror unit based on the input signal, the second current mirror unit is connected to the second end of the second current source, and the second current mirror unit generates a second regulation current based on the fourth current mirror to extract the current on the second input pair tube.

8. The full-swing operational amplifier according to claim 7, characterized in that: The second current mirror unit includes one or more second current mirrors connected in series between the second end of the second switch unit and the second end of the second current source, and the second current mirror is used to generate a second regulating current based on a fourth current mirror.

9. The full-swing operational amplifier according to claim 1, characterized in that: The value of the first regulating current is half of the second current, and the value of the second regulating current is half of the first current.

10. The full-swing operational amplifier according to claim 1, wherein: The subsequent stage circuit includes a folded cascode amplifier.

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