CMOS control circuit based on FPGA algorithm

Abstract

The utility model relates to a CMOS (Complementary Metal Oxide Semiconductor) control circuit based on an FPGA (Field Programmable Gate Array) algorithm, which comprises an FPGA driving and control module, a driving time sequence module, a CMOS LDO (Low Dropout Regulator) module, a CMOS image sensor module, a signal amplification module and an A / D (Analog / Digital) conversion module which are electrically connected in sequence, a capacitor circuit is added to each pin end of the CMOS image sensor module, each capacitor circuit is connected in parallel with a plurality of capacitors with the capacitance values of 0.1 uF, 4.7 uF and 47 uF, and the FPGA driving and control module, the driving time sequence module, the CMOS LDO module, the CMOS image sensor module and the signal amplification module are electrically connected in sequence. The signal noise interference is reduced, and the transmission image quality is improved; the working voltage of the FPGA driving and control module is 3.3 V, a voltage input end is connected with a plurality of groups of capacitors in parallel and is connected with a 100R resistor in series, so that the input voltage is uniform, fluctuation is reduced, and a designed displayed image has the characteristics of high resolution, high sensitivity and low dark current noise, and is very suitable for being used as an industrial-grade image sensor.

Description

Technical Field

[0001] This application belongs to the technical field of CMOS control circuits, and particularly relates to a CMOS control circuit based on FPGA algorithms. Background Art

[0002] CMOS image sensors are a typical type of solid-state imaging sensors, having a common historical origin with CCDs. A CMOS image sensor usually consists of an image-sensitive unit array, a row driver, a column driver, a timing control logic, an AD converter, a data bus output interface, a control interface, etc. So far, with the continuous improvement of the process, the application scope of CMOS image sensors has also been continuously expanded, covering various fields such as digital products, communications, industry, and medical care. Compared with CCDs, CMOS image sensors have the characteristics of small size, low power consumption, and low cost.

[0003] In order to improve the image transmission quality of CMOS series image sensors, some people have applied FPGAs into CMOS circuits to obtain a more cost-effective CMOS control circuit. However, with the increasing maturity of integration technology, the usage accuracy of CMOS image sensors is getting higher and higher. In order to reduce the manufacturing cost and improve the image transmission quality, an improved technology is provided. Summary of the Utility Model

[0004] The utility model provides a CMOS control circuit based on FPGA algorithms that can achieve a process of higher stability in image acquisition and transmission, ensuring higher and more accurate image quality.

[0005] The technical solution adopted by the utility model to solve its technical problems is:

[0006] A CMOS control circuit based on an FPGA algorithm, comprising an FPGA driving and controlling module, a driving timing module, a CMOS LDO module, a CMOS image sensor module, a signal amplification module, and an A / D conversion module that are electrically connected in sequence. After receiving a collection command, the FPGA driving and controlling module outputs a driving signal to drive the timing module. The CMOS image sensor module outputs an analog voltage after photoelectric conversion under the signal control of the driving timing module. The signal is amplified by the signal amplification module, and after analog-to-digital conversion by the A / D conversion module, the conversion result is processed by the FPGA driving and controlling module and then transmitted to an output interface. The output end is connected to a host computer to display the signal collected by the CMOS image sensor; a capacitor circuit is added to each signal pin end of the CMOS image sensor module, and several capacitors with capacitance values of 0.1 uF, 4.7 uF, and 47 uF are connected in parallel to each circuit to reduce the noise interference of the input signal and improve the quality of the transmitted image; the working voltage of the FPGA driving and controlling module is 3.3 V, and several groups of capacitors are connected in parallel to the voltage input end to make the input voltage uniform and reduce fluctuations. The CMOS LDO module is connected to the voltage input end, a 2.2 uF capacitor is connected and then grounded for energy storage and input signal filtering, and 22 pF and 2.2 uF filtering capacitors are connected to the output end.

[0007] The beneficial effects of the present utility model are as follows:

[0008] 1. A capacitor circuit is added to each pin end of the CMOS image sensor module, and several capacitors with capacitance values of 0.1 uF, 4.7 uF, and 47 uF are connected in parallel to each capacitor circuit. The interference of the output signal can be used as the object to be filtered to prevent the interference signal from returning, thereby eliminating noise, distortion, etc. in the image data. At the same time, because noise is often not a single frequency point, adding multiple capacitors can occupy a certain frequency band and filter out noise in different frequency bands, ultimately ensuring the quality of image transmission;

[0009] 2. Several groups of capacitors are connected in parallel to the input end of the FPGA driving and controlling module, and a 100R resistor is connected in series at the same time. According to the frequency impedance characteristics of the capacitor, the input voltage is made uniform and the fluctuation is reduced; Description of the Drawings

[0010] The technical solutions of the present application will be further described below with reference to the drawings and embodiments.

[0011] Figure 1 It is a schematic structural diagram of a CMOS control circuit based on an FPGA algorithm of the present application;

[0012] Figure 2 It is a schematic circuit diagram of the CMOS image sensor module of a CMOS control circuit based on an FPGA algorithm of the present application;

[0013] Figure 3 is a schematic diagram of the parallel capacitor circuit of the CMOS image sensor module in a CMOS control circuit based on the FPGA algorithm of the present application;

[0014] Figure 4 is a schematic diagram of the circuit structure of the FPGA driving and control module of a CMOS control circuit based on the FPGA algorithm of the present application;

[0015] Figure 5 is a schematic diagram of the circuit structure of the CMOS LDO module of a CMOS control circuit based on the FPGA algorithm of the present application;

[0016] Figure 6 is a schematic diagram of the circuit structure of the signal amplification module of a CMOS control circuit based on the FPGA algorithm of the present application;

[0017] The reference numerals in the figure are:

[0018] 1. FPGA driving and control module, 2. A / D conversion module, 3. Driving timing module, 4. CMOS LDO module, 5. CMOS image sensor module, 6. Signal amplification module. Specific embodiments

[0019] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0020] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the protection scope of the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0021] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0022] The technical solution of the present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0023] Embodiment

[0024] This embodiment provides a CMOS control circuit based on an FPGA algorithm. Refer to Figure 1 , which includes an FPGA drive and control module 1, a drive timing module 3, a CMOS LDO module 4, a CMOS image sensor module 5, a signal amplification module 6, and an A / D conversion module 2 that are electrically connected in sequence. After the FPGA drive and control module 1 receives a collection command, it outputs a signal to drive the timing module 3. The CMOS image sensor module 5 outputs an analog voltage after photoelectric conversion under the control of the drive timing module 3. The signal is amplified by the signal amplification module 6, and after analog-to-digital conversion by the A / D conversion module 2, the conversion result is processed by the FPGA drive and control module 1 and then transmitted to the output interface.

[0025] Refer to Figure 2 , Figure 3, a capacitive circuit is added to each pin of the CMOS image sensor module 5. Capacitors C1 to C21 are electrically connected to the VDD33A pin, capacitors C22 to C42 are electrically connected to the VDD13D pin, capacitors C43 to C55 are electrically connected to the VDD13AD pin, capacitors C56 to C62 are electrically connected to the VDDPIX pin, capacitors C63 to C64 are electrically connected to the VDD33A_IO pin, capacitors C65 to C67 are electrically connected to the VDDCL pin, capacitors C66 to C70 are electrically connected to the VGRSTL pin, capacitors C71 to C73 are electrically connected to the VTXH pin, capacitors C74 to C76 are electrically connected to the VTXL pin, and capacitors C77 to C82 are electrically connected to the VG_RSTH pin. A number of capacitors with capacitance values of 0.1 uF, 4.7 uF, and 47 uF are connected in parallel. The interference of the output signal can be used as the object to be filtered to prevent the interference signal from returning, thereby eliminating noise, distortion, etc. in the image data. At the same time, since noise is often not a single frequency point, adding multiple capacitors can occupy a certain frequency band and filter out noise in different frequency bands, ultimately ensuring the quality of image transmission. According to the circuit characteristics, the parallel capacitors first pass through large capacitors and then through small capacitors. The large capacitors filter out low frequencies, and the small capacitors filter out high frequencies. First, filter out low frequencies and then filter out high frequencies. At the same time, capacitors are added between the power supply and the ground because the lower ESR characteristics of the capacitors can reduce power consumption, can perform AC coupling on high-frequency signals, and provide a low-impedance loop for the return current between the power supply and the ground.

[0026] Reference Figure 4 , the working voltage of the FPGA driving and control module 1 is 3.3V, and the input voltage is provided by the power supply module, and the correct input and output capacitors are selected. The FPGA inputs data through J1: FPGA_TDI, clock input: FPGA_TCK, mode selection: FPGA_TMS, data output: FPGA_TDO, inputs the control signal of the FPGA to the CMOS, and according to the frequency impedance characteristics of the capacitors, several groups of capacitors C161 to C167 are connected in parallel to the input terminal FPGA_VCC3V3, and a resistor R65 with a resistance value of 100R is connected in series, which can make the input voltage uniform, reduce fluctuations, prevent the peak voltage from entering and burning the control chip, and at the same time, it will also affect the input and output performance of the FPGA, improve the input and output speed, reduce power consumption and enhance the anti-interference ability.

[0027] Part of the design circuit of the CMOS LDO module 4 is as Figure 5 shown. A dual-channel, low-noise, low-dropout regulator is added to the circuit, which is suitable for battery-powered devices and also has current limiting, over-temperature, and output short-circuit protection. This device can operate stably with very small ceramic capacitors, thereby reducing the required board space and component cost. The input terminal S_VCC5V uses 2.2 u capacitors C93 and C102, and the capacitance can be increased without limit.

[0028] A 0R resistor R7, R12, R18, and R23 is added before each of the VDD33A_IO, VDD33A, VDDPIX, and VDD4V5 in the connection circuit between the CMOS LDO module 4 and the CMOS image sensor module 5. 0R resistors are of great significance for high-speed circuit design. During the period when a CPU is compatible with multiple peripherals, 0R can be used as the connection point for some surrounding devices.

[0029] The output voltage is set by selecting the resistor voltage division ratio. The output voltage VDD is calculated according to the formula Vout = (R1 / R2 + 1) × VFB (feedback voltage VFB = 0.8V). By calculating the ratios of R10 / R11, R13 / R16, R20 / R22, and R24 / R26, the required VDD voltage can be obtained.

[0030] Capacitors of 22pF (C96, C100, C103, C109) and 2.2uF (C94, C101, C108, C110) are added to the output terminal, which can provide a low-impedance loop for noise to flow into the ground plane nearby, so as to avoid these interferences affecting other loads of this current. And the CMOS module provided is a high-speed operating module, and rapid changing charge demands will continuously occur on this module. The power supply module cannot supply current to the device in time to supplement, and it can only rely on the nearby capacitors to solve the problem.

[0031] Combined Figure 6 , the signal amplification module 6 amplifies the image information transmitted by the CMOS image sensor module 5. Capacitors C111~C113, C115, C117, C119~C121 are added to the positive input terminal and the inverting input terminal, which absorb interference signals at the input terminal, so that the interfering AC signals are hardly amplified, thus playing the role of absorbing interference signals and stabilizing the voltage. The signal is filtered at the output terminal to reduce interference and improve the image transmission quality. Resistors R27~R29, R34~R36 are connected to the input terminal. According to the voltage division ratio, the system input voltage can be made to be between 1.65V and 5.5V.

[0032] The FPGA drive and control module 1 is model JFMK50, a high-performance and low-power FPGA product developed by Fudan Microelectronics, which provides programmable logic units, digital signal processing units, storage units, high-speed transceivers and other solutions, with 210 I / O ports and 52,160 logic units, and the quality grade is industrial grade, with high cost performance;

[0033] The CMOS image sensor module 5 is model GMAX0505, a 26-million-resolution charge-domain global shutter high-speed CMOS image sensor, which has the characteristics of high resolution, high sensitivity, and low dark current noise, and is very suitable as an industrial-grade image sensor.

[0034] When the present utility model is specifically implemented:

[0035] After the system is powered on, the parameters of each module in the CMOS control circuit are initialized first. When the FPGA driver and control module receives the acquisition command, it outputs the driving timing module of the CMOS. Under the control of the driving timing module, the CMOS outputs the analog voltage after photoelectric conversion. The signal is amplified by the signal amplification module, and after passing through the data processing and A / D conversion module, the conversion result is cached and processed by the FPGA driver and control module and then transmitted to the output interface. The host computer stores and processes the received data, and finally realizes the real-time display of the image. The displayed image has the characteristics of high resolution, high sensitivity, and low dark current noise, and is very suitable as an industrial-grade image sensor.

[0036] Inspired by the above ideal embodiments according to the present application, through the above description, relevant workers can completely make various changes and modifications without departing from the technical idea of this application. The technical scope of this application is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A CMOS control circuit based on FPGA algorithm, characterized in that: The invention comprises an FPGA driving and control module, a driving timing module, a CMOS LDO module, a CMOS image sensor module, a signal amplification module and an A / D conversion module which are electrically connected in sequence. After receiving a collection command, the FPGA driving and control module outputs a driving signal to drive the timing module. The CMOS image sensor module outputs an analog voltage after photoelectric conversion under the signal control of the driving timing module. The signal is amplified by the signal amplification module, and the analog-to-digital conversion is performed by the A / D conversion module. The conversion result is processed by the FPGA driving and control module and transmitted to the output interface. The output end is connected to a host computer to display the signal collected by the CMOS image sensor. A capacitor circuit is added to each signal pin end of the CMOS image sensor module.

2. The CMOS control circuit based on FPGA algorithm according to claim 1, characterized in that: Each pin end of the CMOS image sensor module is added with a capacitor circuit, including a VDD33A pin electrically connected to capacitors C1-C21, a VDD13D pin electrically connected to capacitors C22-C42, a VDD13AD pin electrically connected to capacitors C43-C55, a VDDPIX pin electrically connected to capacitors C56-C62, a VDD33A_IO pin electrically connected to capacitors C63-C64, a VDDCL pin electrically connected to capacitors C65-C67, a VGRSTL pin electrically connected to capacitors C66-C70, a VTXH pin electrically connected to capacitors C71-C73, a VTXL pin electrically connected to capacitors C74-C76, and a VG_RSTH pin electrically connected to capacitors C77-C82.

3. The CMOS control circuit based on FPGA algorithm according to claim 1, characterized in that: The voltage input terminal FPGA_VCC3V3 of the FPGA driving and control module is connected in parallel to a plurality of groups of capacitors C161-C167 and in series to a resistor R65 with a resistance value of 100R.

4. The CMOS control circuit based on FPGA algorithm according to claim 1, characterized in that: The CMOS LDO module is connected to the voltage input terminal, a 2.2uF capacitor and then to ground for energy storage and input signal filtering. The output terminals are connected to filter capacitors of 22pF and 2.2uF.

5. The CMOS control circuit based on FPGA algorithm according to claim 2, characterized in that: The positive input terminal and the negative input terminal of the signal amplifying module are both electrically connected to the capacitor, and the input terminal thereof is also electrically connected to the resistor.

6. A CMOS control circuit based on FPGA algorithm according to any one of claims 1 to 5, characterized in that: The model of the FPGA driving and control module is JFMK50, and the model of the CMOS image sensor module is GMAX0505.

Images