Semiconductor structure and semiconductor device

Abstract

The utility model relates to a semiconductor structure and a semiconductor device wherein the semiconductor structure includes a source electrode and a drain electrode in a substrate. The semiconductor structure includes a gate of a gallium nitride (GaN) high electron mobility transistor (HEMT) device configured to control a channel between a source and a drain. The semiconductor structure includes a resistor between a gate and a circuit on a substrate, providing the resistor between the gate of a target device (e.g., a gallium nitride (GaN) high electron mobility transistor device) and a clamping circuit improves electrostatic discharge (ESD) protection between an input / output (IO) and the target device. For example, under the human body model, the resistor can form electrostatic discharge protection, which can be at least 2 kilovolts, between the input / output and the source of the target device and between the input / output and the drain of the target device. Since electrostatic discharge protection is improved, the possibility of burnout occurring in the target device is reduced. In addition, a larger current can be applied in the clamping circuit without the risk of electrostatic discharge.

Description

Technical Field

[0001] The present utility model relates to a semiconductor structure and a semiconductor device. Background Art

[0002] In transistor structures such as complementary metal-oxide-semiconductor (CMOS) and photon structures such as pixels, a higher breakdown voltage enables the transistor to function between a wider range of input signals without breakdown. Since gallium nitride exhibits a high bandgap, gallium nitride (GaN) can be used as a material for forming transistors to increase the breakdown voltage of the transistors. Summary of the Utility Model

[0003] Some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a source and a drain located in a substrate. The semiconductor structure includes a gate of a gallium nitride (GaN) high electron mobility transistor (HEMT) device configured to control a channel between the source and the drain. The semiconductor structure includes a resistor located between the gate and a circuit on the substrate.

[0004] Some embodiments described herein provide a method. The method includes forming a contact on a source of a gallium nitride (GaN) high electron mobility transistor (HEMT) device. The method includes forming a resistor in contact with the gate of the GaN HEMT device. The method includes forming a clamping circuit connected to the contact and the resistor.

[0005] Some embodiments described herein provide a semiconductor device. The semiconductor device includes a source and a drain located in a substrate. The semiconductor device includes a gate configured to control a channel between the source and the drain. The semiconductor device includes a clamping circuit located on the substrate and configured to perform electrostatic discharge (ESD). The semiconductor device includes a resistor located between the gate and the clamping circuit.

[0006] In this way, providing a resistor between the gate of a target device (e.g., a GaN HEMT device) and the clamping circuit improves the ESD protection between the IO and the target device. For example, under HBM, the resistor can form an ESD protection of at least 2 kV between the IO and the source of the target device and between the IO and the drain of the target device. Since the ESD protection is improved, the possibility of burnout in the target device is reduced. Additionally, a larger current can be applied in the clamping circuit without the risk of ESD. Description of the Drawings

[0007] Aspects of the present utility model will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the sizes of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0009] Figure 2 is a diagram of an exemplary semiconductor structure described herein.

[0010] Figures 3A to 3D is a diagram of an exemplary implementation described herein.

[0011] Figure 4 is a diagram of an exemplary semiconductor structure described herein.

[0012] Figure 5 is a diagram of an exemplary semiconductor structure described herein.

[0013] Figure 6 is a diagram of an exemplary semiconductor structure described herein.

[0014] Figures 7A to 7B is a diagram of an exemplary semiconductor structure described herein.

[0015] Figures 8A to 8K is a diagram of an exemplary implementation described herein.

[0016] Figure 9 is described herein Figure 1 a diagram of exemplary components of one or more of the devices shown.

[0017] Figure 10 is a flowchart of an exemplary process associated with forming a semiconductor device described herein. Detailed Description

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] In some cases, since gallium nitride exhibits a high bandgap, gallium nitride (GaN) can be used as a material for forming the source, drain, and / or channel of a transistor to increase the breakdown voltage of the transistor. However, gallium nitride has a very low resistance, which results in greater gate leakage (e.g., current flowing into or out of the transistor through the gate) compared to other materials.

[0021] Electrostatic discharge (ESD) protection in semiconductor devices helps prevent short-circuit problems that can cause the device to malfunction. However, in GaN devices, the ESD protection between the input / output (IO) and the semiconductor device may be less than the ESD protection within the device (e.g., between the source and drain of the semiconductor device). In fact, under the human body model (HBM), the ESD protection between the IO and the source of the semiconductor device and between the IO and the drain of the semiconductor device may be less than 1 kilovolt (kv). Therefore, a larger voltage and / or a larger voltage change can cause excessive current to flow through the gate of the semiconductor device and damage the gate.

[0022] Some embodiments described herein provide techniques and apparatus for providing a resistor between a gate of a target device, such as a gallium nitride (GaN) transistor, and a clamping circuit. Accordingly, ESD protection between the IO and the device is improved. For example, under HBM, the resistor can form an ESD protection of at least 2 kV between the IO and the source of the target device and between the IO and the drain of the target device. Since the ESD protection is improved, the likelihood of burnout in the target device is reduced. Additionally, a greater current can be applied in the clamping circuit without the risk of ESD.

[0023] Figure 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. As Figure 1 shown, environment 100 may include a plurality of semiconductor processing tools 102-116 and a wafer / die transfer tool 118. The plurality of semiconductor processing tools 102-116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, an annealing tool 116, and / or another semiconductor processing tool. The tools included in exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and / or manufacturing facility, or another location.

[0024] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, an epitaxy tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0025] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or a similar light source), an x-ray source, an electron beam (e-beam) source, and / or a similar source. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various parts of a semiconductor device, and / or a similar pattern. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0026] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0027] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or a similar etching tool. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, and the plasma etching or plasma-assisted etching may involve using an ionized gas to perform isotropic etching or directional etching on the one or more portions.

[0028] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing the various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited material or a plated material. The planarization tool 110 may use a combination of chemical forces and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 110 may utilize an abrasive and a corrosive chemical slurry in combination with a polishing pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retainer ring. The dynamic polishing head may rotate using different axes of rotation to remove material and flatten any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0029] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or a similar device) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or a similar material) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0030] The photoresist removal tool 114 is a semiconductor processing tool capable of removing the remaining portion of the photoresist layer from the substrate after the etching tool 108 has removed some portions of the substrate. For example, the photoresist removal tool 114 may utilize a chemical stripper and / or another technique to remove the photoresist layer from the substrate.

[0031] The annealing tool 116 is a semiconductor processing tool including a semiconductor processing chamber and one or more devices capable of heating a semiconductor substrate or a semiconductor device. For example, the annealing tool 116 may include a rapid thermal annealing (RTA) tool or another type of annealing tool capable of heating a semiconductor substrate to cause a reaction between two or more materials or gases, thereby decomposing the materials. As another example, the annealing tool 116 may be configured to heat a structure or a layer (or a portion thereof) (e.g., raise or elevate the temperature of the structure or the layer (or a portion thereof)) to reflow the structure or the layer, or to crystallize the structure or the layer, thereby removing defects such as voids or seams. As yet another example, the annealing tool 116 may be configured to heat a layer (or a portion thereof) (e.g., raise or elevate the temperature of the layer (or a portion thereof)) to enable the bonding of two or more semiconductor devices.

[0032] The wafer / die transporter 118 can be included in a cluster tool or another type of tool that includes multiple processing chambers, and can be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, transport substrates and / or semiconductor devices between a processing chamber and a buffer region, transport substrates and / or semiconductor devices between a processing chamber and an interface tool (such as an equipment front end module (EFEM)), and / or transport substrates and / or semiconductor devices between a processing chamber and a transport vehicle (such as a front opening unified pod (FOUP)), and so on. In some embodiments, the wafer / die transporter 118 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from substrates and / or semiconductor devices) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0033] In some embodiments, one or more of the semiconductor processing tools 102-116 and / or the wafer / die transporter 118 can perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-116 and / or the wafer / die transporter 118 can form a contact over the source of a GaN transistor, form a resistor in contact with the gate of a GaN transistor, and / or form a clamping circuit connected to the contact and the resistor, and so on.

[0034] Figure 1 The number and arrangement of the tools shown are provided as one or more examples. In fact, compared to the tools shown Figure 1 in, there can be additional tools, fewer tools, different tools, or differently arranged tools. Additionally, Figure 1 two or more of the tools shown can be implemented within a single tool, or Figure 1 a single tool shown can be implemented as multiple distributed tools. Additionally or alternatively, a set of tools in the environment 100 (e.g., one or more tools) can perform one or more of the functions described as being performed by another set of tools in the environment 100.

[0035] Figure 2 is a diagram of an exemplary semiconductor structure 200 described herein. The exemplary semiconductor structure 200 includes a resistor over a gate to improve ESD protection. In some embodiments, Figure 2The exemplary semiconductor structure 200 shown in FIG. may be included in a processor, memory, or another type of electronic device.

[0036] As Figure 2 shown, the control device 202 may be connected to the I / O of the exemplary semiconductor structure 200. The control device 202 may be a device that supplies a voltage to operate the semiconductor structure 200 (e.g., by changing the voltage to turn on and off the semiconductor structure 200, etc.).

[0037] For ESD corresponding to an overvoltage (and / or overcurrent), the exemplary semiconductor structure 200 may include a field-effect transistor (FET) 204 configured to enable an ESD processing method (e.g., as described in conjunction with Figures 3A to 3D ). The FET 204 may be silicon-based (e.g., n-channel metal-oxide semiconductor (NMOS) or p-channel metal-oxide semiconductor (PMOS)) or may be GaN-based (e.g., n-type high-electron-mobility transistor (HEMT)). Silicon-based FETs are manufactured more quickly, while GaN-based FETs operate at higher voltage thresholds. To increase the voltage threshold of the silicon-based FET, the FET 204 may be a buried inverted gate FET (BigFET) that is generally larger than other NMOS and PMOS transistors.

[0038] As Figure 2 further shown, the FET 204 may be controlled by a series of diodes 206. Since the voltage drop across the series of diodes 206 is constant, the FET 204 will be enabled only when the voltage from the control device 202 meets a voltage threshold determined by the properties of the series of diodes 206 (e.g., a cut-off voltage based on the voltage drop of each diode and the number of diodes). Depending on the desired voltage threshold, the series of diodes 206 may include a different number (e.g., between three and eight) of diodes. However, other numbers of diodes are also within the scope of the present disclosure. The series of diodes 206 may be silicon-based (e.g., metal-oxide semiconductor (MOS) diodes) or may be GaN-based (e.g., HEMT diodes). Silicon-based diodes are manufactured more quickly, while GaN-based diodes operate at higher voltage thresholds.

[0039] Resistor 208 can protect the series of diodes 206 from excessive current. Resistor 208 can include a silicon resistor (e.g., a silicon chromium (SiCr) resistor, an oxide definition (OD) resistor, a power oxide (PO) resistor, or a metal gate resistor, and other examples), a metal nitride resistor (e.g., a titanium nitride (TiN) resistor), or a GaN resistor (e.g., a two-dimensional electron gas (2DEG) resistor).

[0040] Additionally, resistor 210 can be in parallel with FET 204. As Figure 2 shown, drain 214, source 216, and gate 218 can form a target device 220 controlled by control device 202. Thus, resistor 210 electrically (and physically) connects the clamping circuit 212 to the gate 218 of the target device. Resistor 210 can include a silicon resistor (e.g., an SiCr resistor, an OD resistor, a PO resistor, or a metal gate resistor, and other examples), a metal nitride resistor (e.g., a TiN resistor), or a GaN resistor (e.g., a 2DEG resistor). Gate 218 can be a GaN gate. As used herein, "GaN gate" can refer to a gate formed of gallium nitride and / or the gate of a GaN HEMT device (e.g., a gate formed over crystalline GaN), where the crystalline GaN serves as the channel of the GaN HEMT device.

[0041] The source 216 of the target device 220 can also be connected to the clamping circuit 212 (e.g., in parallel with FET 204). Thus, the clamping circuit 212 can use the source 216 (e.g., as described in connection with Figure 3A and Figure 3B ), or use the channel of the target device 220 (e.g., as described in connection with Figure 3C and Figure 3D ), to perform ESD from the source 216 to the drain 214.

[0042] Resistor 210 protects the gate 218 during ESD (e.g., as described in connection with Figures 3A to 3C ). This protection is particularly important when the target device 220 is a GaN transistor, such that under HBM, the ESD protection between the IO and the source 216 and between the IO and the drain 214 is at least 2 kV. Without at least 2 kV of ESD protection, the gate 218 is likely to burn out during ESD. Additionally, when the target device 220 is a GaN transistor, resistor 210 turns on the channel of the target device 220 during ESD from the drain 214 to the gate 218 (e.g., as described in connection with Figure 3DAs described above, this prevents the gate 218 from being burned out due to gate leakage caused by ESD.

[0043] As described above, Figure 2 is provided as an example. Other examples may be different from those Figure 2 described herein.

[0044] Figure 3A is a diagram of the exemplary embodiment 300 described herein. The exemplary embodiment 300 may be an exemplary processing method for implementing ESD in the exemplary semiconductor structure 200 described in connection with Figure 2 In some embodiments, the exemplary techniques and procedures described in connection with Figure 3A may be used in combination with other semiconductor structures described herein, such as, for example: the exemplary semiconductor structure 400 described in connection with Figure 4 the exemplary semiconductor structure 500 described in connection with Figure 5 or the exemplary semiconductor structure 600 described in connection with Figure 6 The exemplary processing method shown using the exemplary embodiment 300 may be implemented in a processor, memory, or another type of electronic device.

[0045] As Figure 3A shown, when the positive voltage at the IO of the clamping circuit exceeds the cut-off voltage of the series of diodes 206, an ESD is formed (as shown by the ESD current I Figure 3A in ESD ). Since the voltage at the IO exceeds the cut-off voltage, the FET 204 is turned on to form an ESD from the IO to the source 216 (which serves as ground), as shown in Figure 3A . During the ESD, the resistor 210 protects the gate 218 from the influence of the ESD current I ESD . Specifically, the ESD current I ESD will flow through the FET 204 rather than through the gate 218 because the resistor 210 has a non-negligible resistance.

[0046] Figure 3B is a diagram of the exemplary embodiment 320 described herein. The exemplary embodiment 320 may be an exemplary processing method for implementing ESD in the exemplary semiconductor structure 200 described in connection with Figure 2 In some embodiments, the exemplary techniques and procedures described in connection with Figure 3B may be used in combination with other semiconductor structures described herein, such as, for example: the exemplary semiconductor structure 400 described in connection with Figure 4 the exemplary semiconductor structure 500 described in connection with Figure 5 or the exemplary semiconductor structure 500 described in connection with Figure 6The illustrative semiconductor structure 600 described. The illustrative processing method shown using illustrative embodiment 320 may be implemented in a processor, memory, or another type of electronic device.

[0047] As Figure 3B shown, a negative voltage at the IO of the clamping circuit forms an ESD (by the Figure 3B ESD current I in ESD shown). Specifically, the conducting FET 204 is enabled such that an ESD is formed from the source 216 to the IO, as Figure 3B shown. During the ESD, the resistor 210 protects the gate 218 from the ESD current I ESD . Specifically, the ESD current I ESD will flow through the FET 204 rather than through the gate 218 because the resistor 210 has a non-negligible resistance.

[0048] Figure 3C is a diagram of illustrative embodiment 340 described herein. Illustrative embodiment 340 may be an illustrative processing method for implementing ESD in the illustrative semiconductor structure 200 described in connection with Figure 2 . In some embodiments, the illustrative techniques and procedures described in connection with Figure 3C may be used in conjunction with other semiconductor structures described herein such as, for example: the illustrative semiconductor structure 400 described in connection with Figure 4 , the illustrative semiconductor structure 500 described in connection with Figure 5 , or the illustrative semiconductor structure 600 described in connection with Figure 6 . The illustrative processing method shown using illustrative embodiment 340 may be implemented in a processor, memory, or another type of electronic device.

[0049] As Figure 3C shown, a positive voltage at the IO of the clamping circuit exceeding the cut-off voltage of the series of diodes 206 forms an ESD (by the Figure 3C ESD current I in ESD shown). Since the voltage at the IO exceeds the cut-off voltage, the FET 204 is turned on and an ESD is formed from the IO to the drain 214 (which serves as ground), as Figure 3C shown. During the ESD, the resistor 210 protects the gate 218 from the ESD current I ESD . Specifically, the ESD current I ESD will flow through the FET 204 rather than through the gate 218 because the resistor 210 has a non-negligible resistance.

[0050] Figure 3DIt is a diagram of an exemplary implementation 360 described in this document. The exemplary implementation 360 can be an exemplary processing method for implementing ESD in the exemplary semiconductor structure 200 described in conjunction with Figure 2 In some implementations, the exemplary techniques and procedures described in conjunction with Figure 3D can be used in combination with other semiconductor structures such as those described herein, for example: the exemplary semiconductor structure 400 described in conjunction with Figure 4 the exemplary semiconductor structure 500 described in conjunction with Figure 5 or the exemplary semiconductor structure 600 described in conjunction with Figure 6 The exemplary processing method shown using the exemplary implementation 360 can be implemented in a processor, memory, or another type of electronic device.

[0051] As Figure 3D shown, a negative voltage at the IO of the clamping circuit forms an ESD (shown by the ESD current I in Figure 3D ) Specifically, the conducting FET 204 is enabled so that an ESD is formed from the drain 214 to the IO, as shown in ESD During ESD, the leakage current through the gate 218 causes a non - zero voltage drop across the resistor 210, which then enables the gate 218 and opens the channel of the target device. If there is no resistor 210, the ESD will flow through the gate 218 without causing a non - zero voltage drop, and the ESD will thus burn out the gate 218. Due to the non - zero voltage drop across the resistor 210, the ESD current I Figure 3D will flow through the channel rather than through the gate 218. ESD will flow through the channel rather than through the gate 218.

[0052] As described above, Figures 3A to 3D is provided as an example. Other examples may be different from what is described with respect to Figures 3A to 3D

[0053] Figure 4 It is a diagram of the exemplary semiconductor structure 400 described in this document. The exemplary semiconductor structure 400 is similar to the exemplary semiconductor structure 200 except that it includes a forward diode 402 in parallel with the resistor 208 that controls the FET 204. Thus, based on the negative voltage satisfying the voltage threshold value determined by the properties of the forward diode 402 (e.g., the cut - off voltage of the forward diode 402), the ESD caused by the negative voltage at the IO is triggered (e.g., as described in conjunction with Figure 3B and Figure 3DTherefore, compared to the case where the forward diode 402 is omitted, the forward diode 402 triggers ESD caused by a negative voltage faster. The forward diode 402 can be silicon-based (e.g., a MOS diode) or can be GaN-based (e.g., a HEMT diode). Silicon-based diodes are manufactured faster, while GaN-based diodes operate at a higher voltage threshold value.

[0054] Figure 5 is a diagram of an exemplary semiconductor structure 500 described herein. The exemplary semiconductor structure 500 is similar to the exemplary semiconductor structure 400, except that a capacitor 502 is used instead of the series of diodes 206 to control the FET 204. The capacitor 502 can include a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or a GaN-based capacitor (e.g., a HEMT capacitor).

[0055] In the exemplary semiconductor structure 500, the capacitor 502 and the resistor 208 form an RC circuit with a time constant. Therefore, when the rise time associated with the voltage at the IO exceeds the time constant, ESD is triggered. In other words, in Figure 5 the clamping circuit 212 is configured to perform ESD based on the time constant rather than based on a voltage threshold value as shown in Figure 2 and Figure 4 shown. Figure 5 The clamping circuit 212 shown in

[0056] Figure 6 can also be referred to as a "capacitor-resistor clamper" because the clamping circuit 212 includes the capacitor 502 followed by the resistor 208 after the IO.

[0057] In the exemplary semiconductor structure 500, the capacitor 502 and the resistor 208 form an RC circuit with a time constant. Therefore, when the rise time associated with the voltage at the IO exceeds the time constant, ESD is triggered. In other words, in Figure 6In [reference], the clamping circuit 212 is configured to perform ESD based on a time constant instead of performing ESD based on a voltage threshold value as shown in Figure 2 and Figure 4 . The clamping circuit 212 shown in Figure 6 may also be referred to as a "resistor-capacitor clamper" because the clamping circuit 212 includes a resistor 208 behind the IO, followed by a capacitor 502.

[0058] In addition, when the time constant is exceeded, the inverter 602 helps trigger the ESD by amplifying the voltage at the FET 204. Therefore, Figure 6 the clamping circuit 212 shown in

[0059] may also be referred to as a "resistor-capacitor-inverter clamper". Figures 4 to 6 As described above, Figures 4 to 6 is provided as an example. Other examples may be different from what is described with respect to Figure 4 The exemplary semiconductor structure 400 shown in Figure 5 The exemplary semiconductor structure 500 shown in Figure 6 or the exemplary semiconductor structure 600 shown in

[0060] Figure 7A is a diagram of a part of the exemplary semiconductor structure 700 described herein. The exemplary semiconductor structure 700 may be included in a memory device, a logic device, a processor, an input / output device, or another type of semiconductor device including one or more transistors.

[0061] The exemplary semiconductor structure 700 includes one or more stack layers. As Figure 7A shown in

[0062] Exemplary semiconductor structure 700 further includes a plurality of epitaxial (epi) regions grown and / or otherwise formed on and / or around some portions of fin structures 704 of substrate 702. The epitaxial regions are formed by epitaxial growth. In some embodiments, the epitaxial regions are formed in recessed portions in fin structures 704. The recessed portions can be formed by strained source drain (SSD) etching of fin structures 704 and / or another type of etching operation. The epitaxial regions serve as drain 214 and source 216 of transistors included in exemplary semiconductor structure 700.

[0063] As Figure 7A further shown, exemplary semiconductor structure 700 includes dielectric layer 706, etch stop layer (ESL) 708, dielectric layer 710, ESL 712, and dielectric layer 714, among other examples. Dielectric layers 706, 710, and 714 are used to electrically isolate various structures of exemplary semiconductor structure 700. Dielectric layers 706, 710, and 714 can each include silicon nitride (SiN x ), oxide (e.g., silicon oxide (SiO x )) and / or another oxide material), and / or another type of dielectric material. ESLs 708 and 712 can each include a layer of material configured to allow selective etching or protection from etching of respective portions of exemplary semiconductor structure 700 (or layers included in exemplary semiconductor structure 700) to form one or more of the structures included in exemplary semiconductor structure 700.

[0064] The transistor further includes gate 218 (which is sometimes referred to as "MG" even when formed of crystalline material), which is formed of polysilicon material, metal (e.g., tungsten (W) or another metal), and / or another type of conductive material. In some embodiments, gate 218 of the transistor can include multiple layers of material, such as multiple metal layers or multiple layers including at least one polysilicon layer and at least one metal layer, among other examples. Gate 218 can be isolated by spacers 716 on each side of gate 218. Spacers 716 can include silicon oxide (SiO x ), silicon nitride (Si X N y ), silicon oxycarbide (SiOC), silicon oxynitride (SiOCN), and / or another suitable material. Gate 218 is further connected to gate contact 718 (also referred to as "gate via" or "VG"). Gate contact 718 can include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), among other examples of conductive materials.

[0065] The drain 214 is electrically connected to the drain contact 720. The drain contact 720 (which is also referred to as "MD") may include cobalt (Co), ruthenium (Ru), tungsten (W), and / or another conductive or metallic material. In some embodiments, the drain contact 720 may be isolated by spacers 724 located on each side of the drain contact 720. The spacers 724 may include silicon oxide (SiO x ), silicon nitride (Si X N y ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or another suitable material. Similarly, the source 216 is electrically connected to the source contact 722. The source contact 722 (which is sometimes referred to as "MD", even though it is connected to the source 216 instead of the drain 214) may include cobalt (Co), ruthenium (Ru), tungsten (W), and / or another conductive or metallic material. In some embodiments, the source contact 722 may be isolated by spacers 724 located on each side of the source contact 722. As an alternative, the spacers 724 may be omitted from the sidewalls of the drain contact 720 and / or the sidewalls of the source contact 722.

[0066] As Figure 7A further shown, the resistor 210 is formed over the gate contact 718. As described in connection with Figures 3A to 3D , the resistor 210 protects the gate 218 during ESD. Although the exemplary semiconductor structure 700 includes the resistor 210 in the middle end of line (MEOL), other examples may include additional metallization layers between the gate 218 and the resistor 210 such that the resistor 210 is included in the back end of line (BEOL). As described in connection with Figure 2 , the resistor 210 may include a silicon resistor (e.g., SiCr resistor, OD resistor, PO resistor, or metal gate resistor, among other examples), a metal nitride resistor (e.g., TiN resistor), or a GaN resistor (e.g., 2DEG resistor).

[0067] The contact 726 may electrically connect the drain 214 to ground or another destination. Additionally, the contact 728 may electrically connect the source 216 to the clamping circuit 212 (e.g., as described in connection with Figures 4 to 6 ). Thus, the clamping circuit 212 may be included in the BEOL. In some embodiments, the exemplary semiconductor structure 700 further includes a BEOL layer that connects the exemplary semiconductor structure 700 to the package. Thus, the clamping circuit 212 may be formed over the additional BEOL layer.

[0068] Figure 7BA figure that is part of the exemplary semiconductor structure 750 described herein. The exemplary semiconductor structure 750 may be included in a memory device, a logic device, a processor, an input / output device, or another type of semiconductor device that includes one or more transistors.

[0069] The exemplary semiconductor structure 750 includes one or more stack layers. As Figure 7B shown, the exemplary semiconductor structure 750 includes a substrate 702. The substrate 702 may be described in conjunction Figure 7A with.

[0070] As Figure 7B further shown, a subsequent layer 752 (e.g., formed of an oxide such as silicon oxide) may bond a growth seed layer 754 to the substrate 702. The growth seed layer 754 may enable the channel of the exemplary semiconductor structure 750 to grow crystalline gallium nitride.

[0071] The exemplary semiconductor structure 750 may further include a seed layer 756. For example, the growth seed layer 754 may be chemically bonded to a precursor such that the seed layer 756 may be formed by epitaxial growth.

[0072] In some embodiments, the seed layer 756 also serves as a buffer layer. Although Figure 7B the seed layer 756 is depicted as a single layer, other examples may include multiple seed layers that are arranged to improve lattice matching, reduce threading dislocations, reduce tensile stress, and / or improve the quality of the drain 214, source 216, and gate 218.

[0073] As Figure 7B further shown, the exemplary semiconductor structure 750 may include a gallium nitride buffer layer 758. The buffer layer 758 provides improved lattice matching between the remainder of the exemplary semiconductor structure 750 and the seed layer 756 (and the substrate 702).

[0074] Some examples may include one or more additional buffer layers (e.g., formed between the buffer layer 758 and the seed layer 756). For example, the additional buffer layer may provide additional lattice matching between the buffer layer 758 and the seed layer 756. In some embodiments, an additional buffer layer formed of a III-V material may be included, the additional buffer layer having a varying concentration of group III elements and a varying concentration of group V elements as a function of depth.

[0075] The layer 760 formed of undoped gallium nitride can provide a channel for the exemplary semiconductor structure 750. The layer 760 formed of undoped gallium nitride can be formed over the buffer layer 758, such that the effect of lattice mismatch between the layer 758 formed of gallium nitride and the seed layer 756 is reduced. In some embodiments, the layer 760 can be unintentionally doped gallium nitride (which is also referred to as "UID-GaN"). For example, the layer 760 can have doping resulting from process contaminants rather than having intentionally placed dopants. In some embodiments, the layer 760 has n-type doping.

[0076] A layer 762 formed of aluminum gallium nitride can be formed over the layer 760 formed of undoped gallium nitride. Since the layer 762 has a different bandgap from the layer 760, the layers 760 and 762 can form a heterojunction structure of the exemplary semiconductor structure 750. For example, the layer 760 can be used as a III-V channel layer having a first bandgap, and the layer 762 can be used as a barrier layer having a second bandgap different from the first bandgap. Although Figure 7B the layer 760 is illustrated as a single layer, other examples can include stacked barrier layers.

[0077] As Figure 7B further shown, the source 216 and the drain 214 are disposed over the upper surface of the heterojunction structure. Additionally, the gate 218 can be formed over the heterojunction structure between the source 216 and the drain 214.

[0078] As Figure 7B further shown, and similar to Figure 7A , the resistor 210 is formed over the gate 218. Additionally, the contact 726 can electrically connect the drain 214 to ground or another destination, and the contact 728 can electrically connect the source 216 to the clamping circuit 212 (e.g., as described in connection with Figures 4 to 6 ). In some embodiments, the exemplary semiconductor structure 750 further includes a BEOL layer that connects the exemplary semiconductor structure 750 to the package. Thus, the clamping circuit 212 can be formed over an additional BEOL layer.

[0079] As described above, Figure 7A and Figure 7B are provided as examples. Other examples may differ from what is described with respect to Figure 7A and Figure 7B . For example, other embodiments can include the resistor 210 (and / or the clamping circuit 212) located on a separate substrate. Thus, the resistor 210 (and / or the clamping circuit 212) can be connected to the exemplary semiconductor structure 700 or the exemplary semiconductor structure 750 by wafer bonding rather than by being formed on the same substrate 702.

[0080] Figures 8A to 8K It is a diagram of exemplary implementation 800 described in this document. Exemplary implementation 800 may be an exemplary process for forming an exemplary semiconductor structure 200 having a resistor over a gate. The semiconductor structure formed using exemplary implementation 800 may be included in a processor, memory, or another type of electronic device.

[0081] As Figure 8A shown, an exemplary process for forming a semiconductor structure may be implemented in conjunction with substrate 702. As described above, substrate 702 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate on which semiconductor pixels may be formed. For example, substrate 702 may be formed of the following materials: silicon (Si) (e.g., a silicon substrate), a material containing silicon, a Group III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), SOI, or another type of semiconductor material capable of generating charge from incident light. In some embodiments, substrate 702 is formed of a doped material (e.g., a p-doped material or an n-doped material) such as doped silicon.

[0082] As Figure 8A further shown, an adhesion layer 752 may be formed over substrate 702. For example, deposition tool 102 may form adhesion layer 752 over and / or on the front surface of substrate 702. In some embodiments, deposition tool 102 may use spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique to form adhesion layer 752. Adhesion layer 752 may be planarized after deposition. For example, planarization tool 110 may perform a CMP process on adhesion layer 752.

[0083] As Figure 8A shown, a growth seed layer 754 may be formed over substrate 702. For example, deposition tool 102 may form growth seed layer 754 over and / or on the front surface of substrate 702. In some embodiments, growth seed layer 754 may include silicon (Si), such as p-silicon. Thus, deposition tool 102 may use epitaxial growth on substrate 702 to form growth seed layer 754. Deposition tool 102 may use epitaxial growth to form growth seed layer 754.

[0084] As Figure 8AAs further shown, a seed layer 756 can be formed using a growth seed layer 754. For example, the deposition tool 102 can form the seed layer 756 over and / or on the front surface of the substrate 702. In some embodiments, the seed layer 756 can comprise aluminum nitride. Thus, the deposition tool 102 can form the seed layer 756 by epitaxial growth of the growth seed layer 754.

[0085] As Figure 8B shown, one or more buffer layers can be formed. In an exemplary embodiment 800, a buffer layer 758 is formed over the seed layer 756. The deposition tool 102 can form the buffer layer 758 over and / or on the front surface of the substrate 702. In some embodiments, the buffer layer 758 can comprise gallium nitride. Thus, the deposition tool 102 can form the buffer layer 758 by epitaxial growth of the seed layer 756.

[0086] As Figure 8C shown, a heterojunction structure (e.g., formed of III-V materials) can be deposited over the buffer layer 758. For example, the heterojunction structure can include a layer 760 formed of a III-V material having a first bandgap (e.g., undoped GaN or UID-GaN) and a layer 762 formed of a III-V material having a second bandgap (e.g., AlGaN). The deposition tool 102 can form the layers 760 and 762 using spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique.

[0087] As Figure 8D shown, a HEMT process can be implemented. For example, a source 216 and a drain 214 can be formed over the heterojunction structure. The deposition tool 102 can form the source 216 and the drain 214 using spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique.

[0088] As Figure 8D further shown, the HEMT process can further include forming a gate 218 over the heterojunction structure. The deposition tool 102 can form the gate 218 using spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique.

[0089] Additionally, a dielectric layer 714 can be formed over the drain 214, the source 216, and the gate 218. For example, the deposition tool 102 can form the dielectric layer 714 over and / or on the front surface of the substrate 702. In some embodiments, the deposition tool 102 can form the dielectric layer 714 using spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique.

[0090] As shown Figure 8E in, a recess 802 may be formed over the source 216, and a recess 804 may be formed over the drain 214. For example, the etching tool 108 may form the recess 802 to expose the surface of the source 216, and form the recess 804 to expose the surface of the drain 214. In some embodiments, the deposition tool 102 may form a photoresist layer over and / or on the front surface of the substrate 702. The exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the developing tool 106 may develop and remove some portions of the photoresist layer to expose the pattern. Accordingly, the etching tool 108 may etch the portions of the dielectric layer 714 that are over the drain 214 and the source 216. For example, the etching tool 108 may use wet etching techniques, dry etching techniques, plasma enhanced etching techniques, and / or another type of etching technique to etch the said portions of the dielectric layer 714. After the dielectric layer 714 is etched, the photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, a plasma asher, and / or another technique). Although the exemplary embodiment 800 is described as forming the recesses 802 and 804 during the same etching cycle, other examples may include using one cycle for the recess 802 and another cycle for the recess 804.

[0091] As shown Figure 8F in, a contact 726 may be formed over the drain contact 720, and a contact 728 may be formed over the source contact 722. For example, the deposition tool 102 may form the contacts 726 and 728 in the recesses 804 and 802, respectively. In some embodiments, the deposition tool 102 may use spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique to form the contacts 726 and 728. As shown Figure 8D further in, the materials of the contacts 726 and 728 may overflow the recesses 802 and 804. Accordingly, as shown Figure 8G in, the planarization tool 110 uses CMP to remove the excess material. Although the exemplary embodiment 800 is described as forming the contacts 726 and 728 simultaneously, other examples may include forming the contact 726 separately from forming the contact 728.

[0092] As shown Figure 8HAs shown, a groove 806 can be formed over the gate 218. For example, an etching tool 108 can form the groove 806 to expose the surface of the gate 218. In some embodiments, a deposition tool 102 can form a photoresist layer over and / or on the front-side surface of the substrate 702, an exposure tool 104 can expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and a developing tool 106 can develop and remove some portions of the photoresist layer to expose the pattern. Accordingly, the etching tool 108 can etch a portion of the dielectric layer 714 that is located above the gate 218. For example, the etching tool 108 can use wet etching techniques, dry etching techniques, plasma-enhanced etching techniques, and / or another type of etching technique to etch the portion of the dielectric layer 714. After the dielectric layer 714 is etched, a photoresist removal tool 114 can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, a plasma asher, and / or another technique). Although the exemplary embodiment 800 is described as forming the groove 806 separately from the grooves 802 and 804, other examples can include forming the grooves 802 and 804 simultaneously with the groove 806.

[0093] As Figure 8I shown, a resistor 210 can be formed over the gate 218. For example, a deposition tool 102 can form the resistor 210 in the groove 806. In some embodiments, the deposition tool 102 can use spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique to form the resistor 210. As Figure 8I shown, the resistor 210 can physically contact the gate 218. As an alternative, as Figure 7A shown, the resistor 210 can electrically contact the gate 218. In other words, the resistor 210 can be formed to be electrically in series with the gate 218.

[0094] When the resistor 210 is a silicon resistor (e.g., a SiCr resistor, an OD resistor, a PO resistor, or a metal gate resistor, among other examples), silicon can be included as a deposition material together with a metal (for a SiCr resistor or a metal gate resistor) or an oxide (for an OD resistor or a PO resistor). When the resistor 210 is a metal nitride resistor (e.g., a TiN resistor), the metal and nitrogen can be included together in the deposition material. When the resistor 210 is a GaN resistor (e.g., a 2DEG resistor), gallium and nitrogen can be included together in the deposition material.

[0095] As Figure 8I further shown, the material of the resistor 210 can overflow the groove 806. Accordingly, as Figure 8JAs shown, planarization tool 110 utilizes CMP to remove excess material.

[0096] As Figure 8K shown, clamping circuit 212 can be formed to be electrically connected to contact 728 and resistor 210, but not connected to contact 726 (e.g., contact 726 can be connected to ground or another destination separated from clamping circuit 212). In some embodiments, deposition tool 102 can form an additional dielectric layer (optionally with additional ESL). In some embodiments, deposition tool 102 can utilize spin coating techniques, CVD techniques, PVD techniques, ALD techniques, and / or another deposition technique to form an additional dielectric layer (optionally with additional ESL). Thus, the circuit components of clamping circuit 212 can be formed in the additional dielectric layer (e.g., similar to that described above for drain 214, source 216, gate 218, and / or any contact described herein). In some embodiments, all components of clamping circuit 212 are formed after resistor 210 is formed. Alternatively, some components of clamping circuit 212 (e.g., diodes) can be formed together with resistor 210 in the front end of line (FEOL) such that the connections between any components in the FEOL and resistor 210 are formed after resistor 210 is formed.

[0097] As described above, Figures 8A to 8K is provided as an example. Other examples may be different from that described with respect to Figures 8A to 8K For example, although clamping circuit 212 using Figure 2 illustrates exemplary embodiment 800, other clamping circuits described herein can also be used, such as Figure 4 's clamping circuit, Figure 5 's clamping circuit, or Figure 6 's clamping circuit. Additionally or alternatively, although exemplary embodiment 800 is illustrated with reference to exemplary semiconductor structure 750 shown in Figure 7B , the processes described in connection with Figures 8A to 8K can be similarly used to form resistor 210 in exemplary semiconductor structure 700 shown in Figure 7A . Additionally or alternatively, although exemplary embodiment 800 is shown as forming clamping circuit 212 on substrate 702, clamping circuit 212 can alternatively be formed on a separate substrate and connected to contact 728 and resistor 210 by wafer bonding.

[0098] Figure 9FIG. is a diagram of example components of apparatus 900 described herein. In some embodiments, one or more of semiconductor processing tools 102-116 and / or wafer / die transfer tool 118 may include one or more apparatus 900 and / or one or more components of apparatus 900. As Figure 9 shown, apparatus 900 may include bus 910, processor 920, memory 930, input component 940, output component 950, and communication component 960.

[0099] Bus 910 may include one or more components enabling wired and / or wireless communication between components of apparatus 900. Bus 910 may couple Figure 9 two or more of the shown components together (e.g., by operative coupling, communication coupling, electrical coupling, and / or electro - magnetic coupling). Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing component. Processor 920 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0100] Memory 930 may include volatile memory and / or non - volatile memory. For example, memory 930 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 930 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 930 may be a non - transitory computer - readable medium. Memory 930 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of apparatus 900. In some embodiments, memory 930 may include one or more memories (e.g., via bus 910) coupled to one or more processors (e.g., processor 920).

[0101] The input component 940 enables the device 900 to receive inputs, such as user inputs and / or sensed inputs. For example, the input component 940 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a global positioning system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 950 enables the device 900 to provide outputs, such as via a display, a speaker, and / or a light-emitting diode. The communication component 960 enables the device 900 to communicate with other devices via a wired connection and / or a wireless connection. For example, the communication component 960 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0102] The device 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., the memory 930) may store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 920. The processor 920 may execute the set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 920 causes the one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some embodiments, one or more operations or processes described herein are performed using hardwired circuitry instead of or in combination with the instructions. Additionally or alternatively, the processor 920 may be configured to perform one or more operations or processes described herein. Thus, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0103] Figure 9 The number and arrangement of the components shown are provided as an example. Compared to Figure 9 the components shown, the device 900 may include additional components, fewer components, different components, or components arranged differently. Additionally or alternatively, one or more functions described as being performed by one set of components of the device 900 may be performed by another set of components of the device 900.

[0104] Figure 10 is a flowchart of an exemplary process 1000 associated with forming a semiconductor device described herein. In some embodiments, Figure 10 one or more of the process blocks shown are performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102 to 116). Additionally or alternatively, Figure 10The one or more process blocks shown may be implemented by one or more components of apparatus 900, such as processor 920, memory 930, input component 940, output component 950, and / or communication component 960.

[0105] As Figure 10 shown, process 1000 may include forming a contact (block 1010) over a source of a gallium nitride (GaN) high electron mobility transistor (HEMT) device. For example, as described herein, one or more of semiconductor processing tools 102 to 116 may form a contact 728 over a source 216 of a target device (GaN HEMT device) 220.

[0106] As Figure 10 further shown, process 1000 may include forming a resistor (block 1020) in contact with a gate of the GaN HEMT device. For example, as described herein, one or more of semiconductor processing tools 102 to 116 may form a resistor 210 in contact with a gate 218 of a target device (GaN HEMT device) 220.

[0107] As Figure 10 further shown, process 1000 may include forming a clamping circuit (block 1030) connected to the contact and the resistor. For example, one or more of semiconductor processing tools 102 to 116 may form a clamping circuit 212 connected to the contact 728 and the resistor 210, as described herein.

[0108] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes set forth below and / or in combination with other places herein.

[0109] In a first embodiment, forming contact 728 includes: forming a groove 802 over source 216, depositing metal in groove 802 to form contact 728, and removing excess metal using CMP.

[0110] In a second embodiment, process 1000 includes forming an additional contact 726 over a drain 214 of a target device (GaN HEMT device) 220, where the additional contact 726 is not connected to the clamping circuit 212.

[0111] In a third embodiment, forming resistor 210 includes: forming a groove 806 over gate 218, depositing material in groove 806 to form resistor 210, and removing excess material using CMP.

[0112] In a fourth embodiment, process 1000 includes connecting an IO of the clamping circuit 212 to a control device 202.

[0113] Although Figure 10 illustrative blocks of process 1000 are shown, in some embodiments, process 1000 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to the blocks depicted in Figure 10 . Additionally or alternatively, two or more of the blocks of process 1000 may be performed in parallel.

[0114] In this way, providing a resistor between the gate of a target device (e.g., a GaN HEMT device) and a clamping circuit improves the ESD protection between the IO and the target device. For example, under HBM, the resistor can form an ESD protection that can be at least 2 kV between the IO and the source of the target device and between the IO and the drain of the target device. Since the ESD protection is improved, the likelihood of burnout occurring in the target device is reduced. Additionally, a larger current can be applied in the clamping circuit without the risk of ESD.

[0115] As elaborated in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a source and a drain located in a substrate. The semiconductor structure includes a gate of a gallium nitride (GaN) high electron mobility transistor (HEMT) device configured to control a channel between the source and the drain. The semiconductor structure includes a resistor located between the gate and a circuit on the substrate.

[0116] In some embodiments, the resistor includes a silicon resistor. In some embodiments, the resistor includes a metal nitride resistor. In some embodiments, the resistor includes a gallium nitride resistor. In some embodiments, under the human body model, the resistor forms an electrostatic discharge protection of at least 2 kV between the input / output and the source and between the input / output and the drain.

[0117] As elaborated in more detail above, some embodiments described herein provide a method. The method includes forming a contact over a source of a gallium nitride (GaN) high electron mobility transistor (HEMT) device. The method includes forming a resistor in contact with the gate of the GaN HEMT device. The method includes forming a clamping circuit connected to the contact and the resistor.

[0118] In some embodiments, forming the contact includes: forming a groove over the source; depositing metal in the groove to form the contact; and removing an excess portion of the metal using chemical mechanical planarization. In some embodiments, the method further includes: forming an additional contact over the drain of the gallium nitride high electron mobility transistor device, wherein the additional contact is not connected to the clamping circuit. In some embodiments, forming the resistor includes: forming a groove over the gate; depositing a material in the groove to form the resistor; and removing an excess portion of the material using chemical mechanical planarization. In some embodiments, the method further includes: connecting an input / output of the clamping circuit to a control device.

[0119] As elaborated in more detail above, some embodiments set forth herein provide a semiconductor device. The semiconductor device includes a source and a drain located in a substrate. The semiconductor device includes a gate configured to control a channel between the source and the drain. The semiconductor device includes a clamping circuit located on the substrate and configured to perform electrostatic discharge (ESD). The semiconductor device includes a resistor located between the gate and the clamping circuit.

[0120] In some embodiments, the clamping circuit includes a static clamper. In some embodiments, the clamping circuit includes a series of diodes configured to control a field effect transistor. In some embodiments, the clamping circuit includes a capacitor-resistor clamper. In some embodiments, the clamping circuit includes a resistor-capacitor clamper. In some embodiments, the clamping circuit includes a capacitor and a resistor configured to control a field effect transistor. In some embodiments, the clamping circuit includes an inverter configured to control a field effect transistor. In some embodiments, the clamping circuit includes a forward diode connected to a field effect transistor. In some embodiments, the clamping circuit is configured to perform the electrostatic discharge based on a voltage threshold value. In some embodiments, the clamping circuit is configured to perform the electrostatic discharge based on a time constant.

[0121] As used herein, "meeting a threshold value" may, depending on the context, refer to a value greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or the like.

[0122] The foregoing has outlined the features of several embodiments in order that those skilled in the art may better understand the aspects of the present utility model. Those skilled in the art should understand that they can readily use the present utility model as a basis for designing or modifying other processes and structures to achieve the same purposes as the embodiments introduced herein and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present utility model, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present utility model.

Claims

1. A semiconductor structure, characterized in that: include: A source and a drain are located in the substrate; a gate of a GaN-HEMT device configured to control a channel between the source and the drain; as well as A resistor is located between the gate and the circuit on the substrate.

2. The semiconductor structure according to claim 1, wherein: The resistor forms at least 2 kilovolts of electrostatic discharge protection between the input / output and the source and between the input / output and the drain under the human body model.

3. A semiconductor device, characterized in that: include: A source and a drain are located in the substrate; a gate configured to control a channel between the source and the drain; a clamp circuit located on the substrate and configured to perform electrostatic discharge; as well as A resistor is located between the gate and the clamping circuit.

4. The semiconductor device according to claim 3, characterized in that The clamping circuit includes a static clamp.

5. The semiconductor device according to claim 3, characterized in that The clamp circuit includes a series of diodes configured to control a field effect transistor.

6. The semiconductor device according to claim 3, characterized in that The clamping circuit includes a capacitor-resistor clamp.

7. The semiconductor device according to claim 3, characterized in that The clamping circuit includes a resistor-capacitor clamp.

8. The semiconductor device according to claim 3, characterized in that The clamping circuit includes a capacitor and a resistor configured to control a field effect transistor.

9. The semiconductor device according to claim 3, characterized in that The clamping circuit includes an inverter configured to control a field effect transistor.

10. The semiconductor device according to claim 3, characterized in that The clamping circuit includes a forward diode connected to the field effect transistor.

11. The semiconductor device according to claim 3, characterized in that The clamp circuit is configured to effectuate the electrostatic discharge based on a voltage threshold.

12. The semiconductor device according to claim 3, characterized in that The clamp circuit is configured to effectuate the electrostatic discharge based on a time constant.

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