High-brightness photoelectric device

Abstract

The utility model relates to a high-brightness photoelectric device, which comprises a driving wafer and a pixel unit, the pixel unit comprises a pixel main body and an outer edge wall body, the outer edge wall body is arranged on the side wall of the pixel main body, and the outer edge wall body comprises a first wall body layer; the pixel unit is located between the N-type semiconductor layer and the driving wafer, the pixel body comprises a P-type semiconductor layer and an active layer, and the P-type semiconductor layer is electrically connected with a corresponding anode contact on the driving wafer; the P-type semiconductor layer and the N-type semiconductor layer are insulated through a first wall body layer; the N-type semiconductor layer is electrically connected with the cathode metal piece, and the cathode metal piece is located on the side face of the pixel unit. According to the utility model, the cathode connection structure is prevented from blocking the light-emitting area of the N-type semiconductor layer, and the light-emitting brightness of the pixel unit is improved; in addition, the phenomena of short circuit and electric leakage in the pixel unit can be avoided, and the use reliability of the photoelectric device is effectively ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a high-brightness optoelectronic device. Background Art

[0002] The structure of the existing LED optoelectronic device is shown in Figure 1 , the pixel unit 30 of the existing LED optoelectronic device generally includes a P-type semiconductor layer 3011 and an N-type semiconductor layer 40. An active layer 3012 for emitting light is generally arranged between the P-type semiconductor layer 3011 and the N-type semiconductor layer 40. As Figure 1 shown, the P-type semiconductor layer 3011 needs to be electrically connected to the corresponding anode contact 201 on the driving wafer 20, and a common cathode 10 is separately arranged outside all the N-type semiconductor layers 40 to realize the cathode connection of the N-type semiconductor layers of each pixel unit through the common cathode. In this way, the common cathode covers the N-type semiconductor layer, which will block the light emitted from the N-type semiconductor layer, thereby affecting the light extraction efficiency. Even if the common cathode uses a transparent conductive film, certain light loss will still occur, thereby reducing the light extraction brightness. In addition, the internal electrical isolation effect of the pixel unit of the existing LED optoelectronic device is not good, and short-circuit leakage is likely to occur between the P-type semiconductor layer and the N-type semiconductor layer, resulting in the failure of the optoelectronic device.

[0003] Therefore, the existing LED optoelectronic device has a low brightness, and the pixel unit is likely to have leakage failure due to poor electrical isolation effect, thus affecting the use reliability of the LED optoelectronic device. Summary of the Utility Model

[0004] For this reason, the technical problem to be solved by the utility model is to overcome the defects that the LED optoelectronic device in the prior art has a low brightness and the pixel unit is likely to have leakage failure, so as to improve the use reliability of the LED optoelectronic device.

[0005] To solve the above technical problem, the utility model provides a high-brightness optoelectronic device, including

[0006] a driving wafer, which includes anode contacts;

[0007] a pixel unit, which is arranged on the driving wafer and corresponds to the anode contacts. The pixel unit includes a pixel main body and an outer edge wall body. The outer edge wall body is arranged on the side wall of the pixel main body. The outer edge wall body includes a first wall body layer, and the first wall body layer is an insulator and is attached to the side wall of the pixel main body;

[0008] The pixel unit is located between the N-type semiconductor layer and the driving wafer. The pixel body includes a P-type semiconductor layer and an active layer. The active layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The P-type semiconductor layer is electrically connected to the corresponding anode contact on the driving wafer; between the P-type semiconductor layer and the N-type semiconductor layer of each pixel unit is insulated by a first wall layer;

[0009] The N-type semiconductor layer is electrically connected to the cathode metal part. The cathode metal part is located on the side of the pixel unit to expose the light-emitting area of the N-type semiconductor layer.

[0010] In an embodiment of the present invention, each pixel unit is coated with a first insulating dielectric layer on the outside. An anode metal part is provided on the first insulating dielectric layer. The P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal part.

[0011] In an embodiment of the present invention, a cathode contact corresponding to the cathode metal part is also provided on the driving wafer. The cathode contact and the anode contact are insulated from each other by a second insulating dielectric layer. One end of the cathode metal part is connected to the N-type semiconductor layer, and the other end is connected to the corresponding cathode contact.

[0012] In an embodiment of the present invention, a metal reinforcement is provided between the cathode metal part and the N-type semiconductor layer.

[0013] In an embodiment of the present invention, metal reinforcements are provided on both sides of each pixel unit. There is a gap between the outer edge wall of the pixel unit and the adjacent metal reinforcement, or the outer edge wall of the pixel unit is in contact with the adjacent metal reinforcement.

[0014] In an embodiment of the present invention, the N-type semiconductor layer has a first surface and a second surface arranged opposite to each other. The light-emitting area of the N-type semiconductor layer is located on the first surface. The pixel unit is located between the second surface and the driving wafer. The contact surface between the cathode metal part and the N-type semiconductor layer is located on the second surface, or the contact surface between the cathode metal part and the N-type semiconductor layer covers part of the first surface and exposes the light-emitting area of the N-type semiconductor layer.

[0015] In an embodiment of the present invention, there is a gap between the outer edge wall of the pixel unit and the adjacent cathode metal part, or the outer edge wall of the pixel unit is in contact with the adjacent cathode metal part.

[0016] In an embodiment of the present invention, the outer edge wall further includes a second wall layer, and the second wall layer is attached to the outer wall of the first wall layer.

[0017] In one embodiment of the present utility model, the second wall layer is one of a reflective layer or a conductive layer, or a composite layer composed of a reflective layer and a conductive layer.

[0018] In one embodiment of the present utility model, a plurality of protrusions are formed in the light-emitting region of the N-type semiconductor layer.

[0019] The above technical solution of the present utility model has the following advantages compared with the prior art:

[0020] For the high-brightness optoelectronic device of the present utility model, a cathode metal part is directly arranged on the side of the N-type semiconductor layer and connected thereto to achieve cathode connection, thereby avoiding the cathode connection structure from blocking the light-emitting region of the N-type semiconductor layer, greatly improving the light-emitting brightness and light-emitting efficiency of the pixel unit; in addition, through the arrangement of the outer edge wall body, the phenomenon of short circuit and leakage inside the pixel unit can also be well avoided, thereby effectively ensuring the use reliability of the optoelectronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the content of the present utility model easier to be clearly understood, the present utility model will be further described in detail below according to the specific embodiments of the present utility model in conjunction with the drawings.

[0022] Figure 1 is a schematic structural diagram of an LED optoelectronic device in the prior art;

[0023] Figure 2 is a schematic structural diagram of the first embodiment of the high-brightness optoelectronic device of the present utility model;

[0024] Figure 3 is a schematic structural diagram of the second embodiment of the high-brightness optoelectronic device of the present utility model;

[0025] Figure 4 is a schematic structural diagram of the third embodiment of the high-brightness optoelectronic device of the present utility model;

[0026] Figure 5 is a schematic structural diagram of the fourth embodiment of the high-brightness optoelectronic device of the present utility model;

[0027] Figure 6 is a schematic structural diagram of the fifth embodiment of the high-brightness optoelectronic device of the present utility model;

[0028] Figure 7 is a preparation flow chart of the optoelectronic device of the present utility model;

[0029] Figure 8 is a preparation flow chart of one embodiment of the outer edge wall body of the optoelectronic device of the present utility model;

[0030] Figure 9 It is a schematic diagram of an arrangement mode of the metal reinforcing member of the present utility model;

[0031] Figure 10 It is a schematic diagram of another arrangement mode of the metal reinforcing member of the present utility model;

[0032] Figure 11 It is a schematic diagram of an arrangement mode of the cathode metal member of the present utility model;

[0033] Figure 12 It is a schematic diagram of another arrangement mode of the cathode metal member of the present utility model;

[0034] Explanation of reference numerals in the accompanying drawings of the specification:

[0035] 10. Common cathode;

[0036] 20. Driving wafer; 201. Anode contact;

[0037] 30. Pixel unit; 301. Pixel main body; 3011. P-type semiconductor layer; 3012. Active layer; 302. Outer edge wall body; 3021. First wall body layer; 30211. Step portion; 3022. Second wall body layer;

[0038] 40. N-type semiconductor layer; 401. First surface; 4011. Protrusion; 402. Second surface; 50. Cathode metal member; 60. First insulating dielectric layer; 70. Anode metal member; 80. Cathode contact; 90. Second insulating dielectric layer; 100. Metal reinforcing member; 110. Compound semiconductor; 1101. Substrate; 120. Hard mask. Detailed implementation manners

[0039] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it, but the specific embodiments cited are not intended to limit the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present disclosure, its application or use.

[0040] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise stated, the meaning of "a plurality" is two or more.

[0041] This embodiment provides a high-brightness optoelectronic device, which can effectively improve the brightness of the LED optoelectronic device, and at the same time avoid the phenomenon of easy leakage failure of the pixel unit, thereby effectively improving the use reliability of the LED optoelectronic device.

[0042] The following will be combined with Figures 2 - 12 to further describe the structure of this embodiment. Embodiment 1

[0043] Refer to Figure 2 , this embodiment discloses a high-brightness optoelectronic device, including a driving wafer 20 and a pixel unit 30;

[0044] Among them, the driving wafer 20 includes an anode contact 201;

[0045] The pixel unit 30 is disposed on the driving wafer 20 and corresponds to the anode contact 201. The pixel unit 30 includes a pixel body 301 and an outer edge wall body 302. The outer edge wall body 302 is disposed on the side wall of the pixel body 301. The outer edge wall body 302 includes a first wall layer 3021, and the first wall layer 3021 is an insulator, and the first wall layer 3021 is attached to the side wall of the pixel body 301;

[0046] The pixel unit 30 is located between the N-type semiconductor layer 40 and the driving wafer 20. The pixel body 301 includes a P-type semiconductor layer 3011 and an active layer 3012. The active layer 3012 is used for emitting light. The light emitted through the active layer 3012 will finally pass through the N-type semiconductor layer 40 and be emitted through the N-type semiconductor layer; the active layer 3012 is located between the N-type semiconductor layer 40 and the P-type semiconductor layer 3011, and the P-type semiconductor layer 3011 is electrically connected to the corresponding anode contact 201 on the driving wafer 20 to achieve anode connection;

[0047] The P-type semiconductor layer 3011 and the N-type semiconductor layer 40 of each pixel unit 30 are insulated from each other by a first wall layer 3021;

[0048] The N-type semiconductor layer 40 is electrically connected to the cathode metal part 50 to achieve cathode connection. The cathode metal part 50 is located on the side of the pixel unit 30 so that the light-emitting area of the N-type semiconductor layer is exposed and not blocked.

[0049] It can be understood that the "light-emitting area of the N-type semiconductor layer" here refers to the area where the light emitted from the active layer 3012 inside the pixel unit 30 is emitted through the N-type semiconductor layer 40.

[0050] The above structure does not require a separate common cathode to be provided outside the N-type semiconductor layer 40. Instead, the cathode metal part 50 is directly provided on the side of the N-type semiconductor layer 40 and connected thereto to achieve cathode connection, so that the N-type semiconductor layer 40 is exposed, thereby avoiding the cathode metal part 50 from blocking the light-emitting area of the N-type semiconductor layer 40, greatly improving the light-emitting brightness of the pixel unit 30, achieving the best light-emitting efficiency, improving the use reliability, and at the same time enabling the full utilization of the N-type semiconductor layer, reducing the waste of manufacturing materials, and being beneficial to cost saving; in addition, by providing an outer edge wall 302 at the side wall of the pixel main body 301 of the optical element, the N-type semiconductor layer 40 and the P-type semiconductor layer 3011 are insulated from each other by the first wall layer 3021, which can better avoid the occurrence of short-circuit leakage between the N-type semiconductor layer 40 and the P-type semiconductor layer 3011, and can also effectively ensure the use reliability of the optoelectronic device.

[0051] In one embodiment, each pixel unit 30 is coated with a first insulating dielectric layer 60. An anode metal part 70 is provided on the first insulating dielectric layer 60. The P-type semiconductor layer 3011 of the pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20 through the anode metal part 70 to facilitate anode connection, and the arrangement is simple and the connection is reliable.

[0052] Through the first insulating dielectric layer 60, isolation insulation between adjacent pixel units 30 can be achieved to avoid mutual interference between adjacent pixel units 30.

[0053] In one embodiment, as Figure 2 、 Figure 3 、 Figure 4 and Figure 6 shown, the driving wafer 20 is also provided with a cathode contact 80 corresponding to the cathode metal part 50. The cathode contact 80 and the anode contact 201 are insulated from each other by a second insulating dielectric layer 90. One end of the cathode metal part 50 is connected to the N-type semiconductor layer 40, and the other end is connected to the corresponding cathode contact 80.

[0054] By providing a cathode contact 80 on the driving wafer 20, the cathode transmission distance can be effectively shortened, which is more conducive to the transmission of cathode current.

[0055] Furthermore, the material of the second insulating dielectric layer 90 can be any one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0056] Furthermore, a second insulating dielectric layer 90 is deposited on the driving wafer 20, and the anode contact 201 can be embedded in the second insulating dielectric layer 90; the cathode contact 80 can also be embedded in the second insulating dielectric layer 90.

[0057] In one embodiment, the N-type semiconductor layer 40 has a first surface 401 and a second surface 402 arranged opposite to each other. The light-emitting region of the N-type semiconductor layer 40 is located on the first surface 401, and the pixel unit 30 is located between the second surface 402 and the driving wafer 20. As Figure 2 shown, the contact surface between the cathode metal part 50 and the N-type semiconductor layer 40 is located on the second surface 402;

[0058] Or, as Figure 4 shown, the contact surface between the cathode metal part 50 and the N-type semiconductor layer 40 covers a part of the first surface 401 and does not block the light-emitting region of the N-type semiconductor layer 40, so that the light-emitting region of the N-type semiconductor layer 40 is always exposed.

[0059] In one embodiment, as Figure 11 shown, there is a gap between the outer edge wall body 302 of the pixel unit 30 and the adjacent cathode metal part 50;

[0060] Or, in the extreme case, as Figure 12 shown, the outer edge wall body 302 of the pixel unit 30 is in contact with the adjacent cathode metal part 50 to maximize the transmission of cathode current.

[0061] Furthermore, a first insulating dielectric layer 60 is filled between the cathode metal part 50 and the adjacent pixel unit 30.

[0062] In one embodiment, as Figures 2 - 6 shown, the outer edge wall body 302 further includes a second wall layer 3022, and the second wall layer 3022 is attached to the outer wall of the first wall layer 3021 so that there is no gap between them.

[0063] Furthermore, the second wall layer 3022 is made of a metal layer to achieve the function of enhancing cathode electrical connection or enhancing reflection.

[0064] Furthermore, the second wall layer 3022 is one of a reflective layer or a conductive layer, or a composite layer composed of a reflective layer and a conductive layer, so as to enhance the optical or electrical function.

[0065] By providing a reflective layer in the second wall layer 3022, the effect of side reflection can be achieved, which is more conducive to the realization of omnidirectional reflection, greatly improving the brightness of the pixel unit 30 and the collimation of light, thereby obtaining better performance and a smaller divergence angle.

[0066] By providing a conductive layer in the second wall layer 3022, it is more conducive to the electrical connection between the pixel unit 30 and other components.

[0067] Among them, the reflective layer can be formed by depositing high-reflectivity metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt);

[0068] The conductive layer can be formed by depositing highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), or titanium (Ti).

[0069] The second wall layer 3022 can also be a laminate of a transparent conductive layer and a metal layer, such as stacking silver and titanium tungsten film layers on zinc oxide.

[0070] In one embodiment, as Figure 3 shown, a stepped portion 30211 is formed at one end of the first wall layer 3021 close to the N-type semiconductor layer 40, and the second wall layer 3022 is located on the stepped portion 30211.

[0071] In another embodiment, as Figure 2 shown, the structure without the stepped portion 30211 can also be adopted at one end of the first wall layer 3021 close to the N-type semiconductor layer 40.

[0072] In one embodiment, as Figure 2 shown, a plurality of protruding portions 4011 are formed in the light-emitting region of the N-type semiconductor layer 40, so that the surface of the light-emitting region presents an uneven state, thereby reducing or destroying the total reflection at the interface between the semiconductor material and air, and thus improving the light extraction efficiency of the LED.

[0073] In one embodiment, as Figure 7 shown in stage b of [reference], the angle θ between the pixel body 301 and the N-type semiconductor layer 40 is about 90°, specifically it can be 60° to 120°, preferably 75° to 105°.

[0074] In one embodiment, as Figure 3 shown, the length L2 of the pixel body 301 is 0.5 um to 50 um.

[0075] In one embodiment, the thickness L1 of the first wall layer 3021 is 50 nm to 1500 nm. The selection of this thickness range can maximize the thickness requirements of the dielectric layer of the omnidirectional reflection structure for different wavelengths while achieving an ideal insulation wrap.

[0076] As Figure 7 shown, this embodiment also discloses a method for manufacturing a high-brightness optoelectronic device, including,

[0077] 1) Prepare a driving wafer 20 such that the driving wafer 20 includes an anode contact 201;

[0078] And prepare a compound semiconductor 110. As Figure 7 in stage a, the compound semiconductor 110 includes a substrate 1101, and an N-type semiconductor layer 40, an active layer 3012, and a P-type semiconductor layer 3011 formed in sequence along the direction away from the substrate 1101;

[0079] 2) As Figure 7 in stages b-d, process the compound semiconductor 110 to obtain a pixel unit 30 corresponding to the anode contact 201. The pixel unit 30 includes a pixel body 301 and an outer edge wall 302. The outer edge wall 302 is disposed on the side wall of the pixel body 301. The outer edge wall 302 includes a first wall layer 3021. The first wall layer 3021 is an insulator, and the first wall layer 3021 is in contact with the side wall of the pixel body 301; the pixel body 301 includes a P-type semiconductor layer 3011 and an active layer 3012. The active layer 3012 is located between the P-type semiconductor layer 3011 and the N-type semiconductor layer 40, and the N-type semiconductor layer 40 is exposed outside the pixel unit 30;

[0080] 3) As Figure 7 in stage e, connect the compound semiconductor 110 having the pixel unit 30 to the driving wafer 20 such that the pixel unit 30 is located between the N-type semiconductor layer 40 and the driving wafer 20, and the P-type semiconductor layer 3011 of each pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20;

[0081] 4) Remove the substrate 1101 of the compound semiconductor 110;

[0082] Further, after removing the substrate 1101, the N-type semiconductor layer 40 can be directly exposed;

[0083] 5) As Figure 7 in stage g, electrically connect the N-type semiconductor layer 40 to the cathode metal part 50 such that the cathode metal part 50 is located on the side of the pixel unit 30 to expose the light-emitting area of the N-type semiconductor layer 40.

[0084] In one embodiment, as Figure 7 In the f stage, the light-emitting region of the N-type semiconductor layer 40 can be formed with a plurality of protrusions 4011 through surface roughening treatment to improve the light extraction efficiency of the light-emitting region. This roughening treatment can be carried out after removing the substrate 1101 in step 4, or after completing step 5, and can be specifically selected according to the actual situation.

[0085] Furthermore, as Figure 7 In the a stage, when preparing the compound semiconductor 110, a hard mask 120 can also be prepared on the side of the P-type semiconductor layer 3011 away from the substrate 1101 to more easily realize the P-type ohmic contact function and the subsequent pixel patterning etching mask function.

[0086] Among them, the compound semiconductor 110 generally refers to a compound formed by two or more elements. For example, the compound semiconductor here is mainly light-emitting diode epitaxial material, such as InGaN ternary material system or AlGaInP quaternary material system, etc., and its emission wavelength can cover the entire band from ultraviolet, visible light to infrared.

[0087] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are as shown in Table 1 below. In some actual applications, the compound film layer will be more complex, or there will be cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials, and the active layer (MQW quantum well) sandwiched between the two:

[0088] Table 1 Compound film layer material table

[0089] Layer Name Material Material Material Material Material Material Material P - type Semiconductor Layer GaP GaAs GaAs GaAs AlGaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP InGaAs AlGaAs InGaN InGaN InGaN N - type Semiconductor Layer GaAs AlGaAs AlGaAs GaAs GaN GaN GaN Substrate GaAs GaAs GaAs GaAs GaN Si Sapphire

[0090] In one embodiment, before connecting the compound semiconductor 110 having pixel units to the driving wafer 20, as Figure 7 In the d stage, a first insulating dielectric layer 60 is further coated outside each pixel unit, and an anode metal part 70 is provided on the first insulating dielectric layer 60. Then, the P-type semiconductor layer 3011 of the pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20 through the anode metal part 70, thereby realizing anode connection. For example, one end of the anode metal part 70 can be in contact with the P-type semiconductor, and the other end can be in contact with the corresponding anode contact 201 on the driving wafer 20 to realize electrical connection.

[0091] Among them, the method of providing the anode metal part 70 on the first insulating dielectric layer 60 can be realized by the damascene process, so that the anode metal part 70 is embedded on the first insulating dielectric layer 60.

[0092] The material of the anode metal member 70 may include one or more of TiN (titanium nitride), Al (aluminum), TaN (tantalum nitride), and Cu (copper).

[0093] In one embodiment, the material of the first insulating dielectric layer 60 may be one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0094] During fabrication, the first insulating dielectric layer 60 may be formed by depositing the corresponding material over the entire surface outside the pixel unit.

[0095] In one embodiment, the cathode metal member 50 may be fabricated simultaneously with the anode metal member 70 to thicken the cathode metal so as to carry a larger current.

[0096] The formation of the anode contact 201 on the driving wafer 20 may also adopt the damascene process.

[0097] In one embodiment, the method of processing the compound semiconductor 110 to obtain the pixel unit 30 corresponding to the anode contact 201 includes the following steps:

[0098] Step S1), as in Figure 7 in stage b, the compound semiconductor 110 is etched by a first etching method until the etching stops at the N-type semiconductor layer 40 or continues to etch after reaching the N-type semiconductor layer 40 and stops at most at 50% of the thickness of the N-type semiconductor layer, thereby obtaining the pixel body 301 corresponding to the anode contact 201;

[0099] That is, if the etching stop position is inside the N-type semiconductor layer 40, the etching depth of the N-type semiconductor layer 40 should be less than or equal to 50% of the thickness of the N-type semiconductor layer.

[0100] Furthermore, the above first etching method is a dry etching method or a wet etching method.

[0101] Step S2), deposit the first wall layer 3021 outside the pixel body 301, and etch the first wall layer 3021 by a dry etching method, and only the first wall layer 3021 located at the sidewall of the pixel body 301 is retained after etching.

[0102] Among them, the first wall layer 3021 includes one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0103] In one embodiment, in step S2), the preparation of the second wall layer 3022 is also required. Specifically, two methods can be adopted during preparation. One is the overall etching method, and the other is the layer-by-layer etching method:

[0104] The overall etching method (refer to Figure 8 ) is as follows: In step S2), after depositing the first wall layer 3021 outside the pixel body 301, the second wall layer 3022 needs to be deposited. After all depositions are completed, the overall structure composed of the first wall layer 3021 and the second wall layer 3022 is etched using a dry etching method. After etching, only the first wall layer 3021 and the second wall layer 3022 located at the side wall of the pixel body 301 are retained;

[0105] In the pixel unit obtained by the above preparation method, a step portion 30211 is formed at one end of the first wall layer 3021 close to the N-type semiconductor layer 40, and the second wall layer 3022 is located on the step portion 30211.

[0106] The layer-by-layer etching method is as follows: In step S2), after depositing the first wall layer 3021 outside the pixel body 301, the first wall layer 3021 is etched using a dry etching method. After etching, only the first wall layer 3021 located at the side wall of the pixel body 301 is retained. Then, the second wall layer 3022 is deposited outside the first wall layer 3021. After the deposition is completed, the second wall layer 3022 is etched using a dry etching method. After etching, only the second wall layer 3022 located at the side wall of the pixel body 301 is retained.

[0107] In the pixel unit obtained by the above preparation method, there is no step portion between the first wall layer 3021 and the second wall layer 3022.

[0108] The preparation method of the outer edge wall body 302 of the above pixel unit 30 is realized by using a dry etching method without using a lithography machine during preparation, which can get rid of the need for a more advanced lithography machine, without an exposure process, and avoid defects such as patterning failure, large overlay shift, and high production cost caused by using a lithography machine for patterning etching in the prior art. At the same time, it can effectively ensure the preparation accuracy, and can achieve the accuracy of in-situ or self-alignment type, and achieve sub-micron accuracy with micron-level equipment technology.

[0109] In the high-brightness optoelectronic device and its preparation method of the above embodiment, the cathode metal part 50 is directly arranged on the side of the N-type semiconductor layer 40 and connected thereto to realize cathode connection, thereby avoiding the cathode metal part 50 from blocking the light-emitting area of the N-type semiconductor layer 40, greatly improving the light-emitting brightness and light-emitting efficiency of the pixel unit 30, and improving the use reliability; in addition, the N-type semiconductor layer 40 and the P-type semiconductor layer 3011 are insulated from each other through the first wall layer 3021, which can better avoid the occurrence of short-circuit leakage between the N-type semiconductor layer 40 and the P-type semiconductor layer 3011, and can also effectively ensure the use reliability of the optoelectronic device. Embodiment 2

[0110] As Figure 5 and Figure 6 shown, the main difference between this embodiment and the first embodiment is that a metal reinforcement member 100 is provided between the cathode metal member 50 and the N-type semiconductor layer 40 of this embodiment to achieve enhanced cathode connection and strengthen current conduction.

[0111] If the second wall layer 3022 of the pixel unit 30 is made of a conductive metal, the material of the metal reinforcement member 100 can be the same as that of the second wall layer 3022.

[0112] In one implementation, as Figure 6 shown, a cathode contact 80 corresponding to the cathode metal member 50 is further provided on the driving wafer 20. The cathode contact 80 and the anode contact 201 are insulated from each other by a second insulating dielectric layer 90. One end of the cathode metal member 50 is connected to the N-type semiconductor layer 40 through the metal reinforcement member 100, and the other end is connected to the corresponding cathode contact 80.

[0113] In one implementation, metal reinforcement members 100 are provided on both sides of each pixel unit 30. As Figure 9 shown, there is a gap between the outer edge wall 302 of the pixel unit 30 and the adjacent metal reinforcement member 100;

[0114] Or in an extreme case, as Figure 10 shown, the outer edge wall 302 of the pixel unit 30 can be in contact with the adjacent metal reinforcement member 100 to achieve a gapless situation.

[0115] In one implementation, when preparing the metal reinforcement member 100, the above-mentioned metal reinforcement member 100 is deposited on the N-type semiconductor layer 40, so that the N-type semiconductor layer 40 is electrically connected to the cathode metal member 50 through the metal reinforcement member 100. When the second wall layer 3022 is made of a metal member, the above-mentioned metal reinforcement member 100 can be prepared in the following manner:

[0116] When etching the second wall layer 3022 after the deposition of the second wall layer 3022 is completed, as Figure 9 shown, in addition to retaining the second wall layer 3022 located on the side wall of the pixel main body 301, the second wall layer 3022 located on the N-type semiconductor surface on both sides of the pixel unit 30 is also retained (it can be partially retained or completely retained), and the second wall layer 3022 on both sides is directly used as the metal reinforcement member 100. This method can make full use of the material of the second wall layer 3022.

[0117] All of the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present utility model, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of the present application, which will not be elaborated one by one here.

[0118] It should be noted that the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A high brightness optoelectronic device, characterized in that: include, A driving wafer, wherein the driving wafer includes an anode contact; A pixel unit, wherein the pixel unit is disposed on the driving wafer and corresponds to the anode contact, the pixel unit comprises a pixel body and an outer edge wall, the outer edge wall is disposed on a side wall of the pixel body, the outer edge wall comprises a first wall layer, the first wall layer is an insulator, and the first wall layer is in contact with the side wall of the pixel body; The pixel unit is located between the N-type semiconductor layer and the driving wafer, the pixel body includes a P-type semiconductor layer and an active layer, the active layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the P-type semiconductor layer is electrically connected to the corresponding anode contact on the driving wafer; the P-type semiconductor layer and the N-type semiconductor layer of each pixel unit are insulated by a first wall layer; The N-type semiconductor layer is electrically connected to a cathode metal piece, and the cathode metal piece is located on a side of the pixel unit to expose a light emitting region of the N-type semiconductor layer.

2. The high brightness optoelectronic device according to claim 1, characterized in that: The outside of each pixel unit is covered with a first insulating medium layer, an anode metal piece is arranged on the first insulating medium layer, and the P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal piece.

3. The high brightness optoelectronic device according to claim 2, characterized in that: The driver wafer is also provided with a cathode contact corresponding to the cathode metal piece. The cathode contact and the anode contact are insulated by a second insulating medium layer. One end of the cathode metal piece is connected to the N-type semiconductor layer, and the other end is connected to the corresponding cathode contact.

4. The high brightness optoelectronic device according to claim 1, characterized in that: A metal reinforcement is arranged between the cathode metal member and the N-type semiconductor layer.

5. The high brightness optoelectronic device according to claim 4, characterized in that: Metal reinforcements are arranged on both sides of each pixel unit, and there is a gap between the outer edge wall of the pixel unit and the adjacent metal reinforcement, or the outer edge wall of the pixel unit is in contact with the adjacent metal reinforcement.

6. The high brightness optoelectronic device according to claim 1, characterized in that: The N-type semiconductor layer has a first surface and a second surface arranged opposite to each other, the light emitting area of ​​the N-type semiconductor layer is located on the first surface, the pixel unit is located between the second surface and the driving wafer, and the contact surface between the cathode metal part and the N-type semiconductor layer is located on the second surface, or the contact surface between the cathode metal part and the N-type semiconductor layer covers a portion of the first surface and exposes the light emitting area of ​​the N-type semiconductor layer.

7. The high brightness optoelectronic device according to claim 1, characterized in that: There is a gap between the outer edge wall of the pixel unit and the adjacent cathode metal piece, or the outer edge wall of the pixel unit is in contact with the adjacent cathode metal piece.

8. The high brightness optoelectronic device according to claim 1, characterized in that: The outer edge wall body also includes a second wall body layer, and the second wall body layer is in contact with the outer wall of the first wall body layer.

9. The high brightness optoelectronic device according to claim 8, characterized in that: The second wall layer is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

10. The high brightness optoelectronic device according to claim 1, characterized in that: A plurality of protrusions are formed in the light emitting area of ​​the N-type semiconductor layer.

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