Novel multilayer heterogeneous bonding substrate structure

Abstract

The utility model provides a novel multilayer heterogeneous bonding substrate structure, which belongs to the field of piezoelectric composite materials, and comprises a functional substrate layer and a wafer structure layer, the functional substrate layer comprises a first substrate layer, and a functional element and a device layer which are manufactured on the surface of the first substrate layer; the wafer structure layer comprises a second substrate layer, an absorption layer, an isolation layer and a piezoelectric film layer which are sequentially arranged from bottom to top, a bonding layer is arranged between the functional substrate layer and the wafer structure layer, and the bottom surface of the wafer structure layer is aligned with the front surface of the functional substrate layer and is connected with the front surface of the functional substrate layer in various bonding modes at the bonding layer. The wafer structure layer is provided with a plated-through hole, two ends of the plated-through hole are respectively provided with a top metal panel and a bottom panel, the top metal panel is arranged at the top of the wafer structure layer, and the bottom panel is arranged at the bottom of the bonding layer. The method has the advantages of short connection distance, high Q value, good reliability and high space integration level, and is higher in batch production efficiency and more convenient to change wafer materials, functional elements and device manufacturing parameters.

Description

Technical Field

[0001] The utility model belongs to the technical field of piezoelectric composite materials, in particular to a novel multi-layer heterogeneous bonding substrate structure. Background Art

[0002] Spectrum resources are an indispensable foundation for modern communications and broadcasting technologies. Their effective management and rational use are crucial to ensuring the stability and quality of wireless communication services. Spectrum resources have extremely high economic value in modern society and are the basis for supporting key infrastructure such as mobile communications, Internet access, broadcast media and satellite communications.

[0003] With the development of communication technology, spectrum resources are becoming increasingly scarce. The new generation of communication technology increasingly requires high-performance filters with higher frequencies, larger bandwidths, lower losses and higher suppression. Conventional surface acoustic wave filters, as narrowband filters, cannot solve the above problems. Until the emergence of Murata's IHP-SAW technology, surface acoustic wave filters have ushered in new development opportunities. One of the core technologies of IHP-SAW technology is piezoelectric composite material technology, which suppresses the leakage of acoustic wave energy in the film through high and low acoustic impedance, thereby improving the device Q value.

[0004] At present, the industry generally adopts the method of embedding inductors in the substrate to solve the problem of matching the out-of-band indicators of the filter and the resonant unit. However, there are problems such as single components, single functions, and insufficient precision. Utility Model Content

[0005] In order to solve the above problems, the utility model provides a novel multi-layer heterogeneous bonding substrate structure. The wafer surface devices call the functional layer elements and the devices have the advantages of short connection distance, high Q value, good reliability and high spatial integration. The wafer structure layer and the functional substrate layer are divided into two parts for modular production, which has higher batch production efficiency and more convenient changes in wafer materials, functional elements and device manufacturing parameters.

[0006] The utility model adopts the following technical solutions to solve the above problems:

[0007] A novel multi-layer heterogeneous bonding substrate structure comprises a functional substrate layer and a wafer structure layer, wherein a bonding layer is arranged between the functional substrate layer and the wafer structure layer, the bottom surface of the wafer structure layer is aligned with the front surface of the functional substrate layer and connected at the bonding layer by a plurality of bonding methods, the wafer structure layer is provided with a metallized hole, and a top metal panel and a bottom panel are respectively arranged at both ends of the metallized hole, the top metal panel is placed on the top of the wafer structure layer, and the bottom panel is placed on the top of the functional substrate layer.

[0008] Further, the functional substrate layer includes a first substrate layer, and functional elements and device layers fabricated on the surface of the first substrate layer. When fabricating the functional elements and device layers, positions for metal panels are reserved, and the positions of the metal panels correspond to the bottom panels of the metallization holes.

[0009] Further, the functional elements and device layers include at least one type of functional element and device. The functional elements and devices can be two-dimensional or three-dimensional elements or devices, and the spaces between the functional elements and devices are filled with a dielectric.

[0010] Further, the wafer structure layer includes a second substrate layer, an absorption layer, an isolation layer, and a piezoelectric thin film layer, which are arranged in sequence from bottom to top.

[0011] Further, the surface of the piezoelectric thin film layer is the front side of the wafer structure layer, and a surface acoustic wave filter is fabricated on the surface of the piezoelectric thin film layer.

[0012] Further, the sidewalls of the metallization holes include an insulating layer, an adhesion layer, and a conduction layer, and the metallization holes are filled with copper metalization by electroplating in a solid state.

[0013] Further, the layout of the metallization holes is divided into multiple specifications, and the sizes and arrangement positions of the metallization holes are different under each specification.

[0014] Further, there are multiple bonding methods for the bonding layer. A bonding layer with an atomic-level thickness can be formed through plasma-activated low-temperature bonding, or a metal layer can be fabricated on the layer surface, and then a metal bonding layer can be formed through bonding under high temperature and high pressure.

[0015] Further, an inverted wafer structure layer is also connected to the functional substrate layer. The structure of each layer of the inverted wafer structure layer is centrosymmetric with respect to the functional substrate layer along the functional substrate layer, and the parameters of each layer of the inverted wafer structure layer are independent of the parameters of each layer of the wafer structure layer.

[0016] Further, the functional substrate layer includes functional elements and device layers, and the functional elements and device layers include independent functional elements and devices, functional elements and devices on the back side of the wafer, and positive and negative conduction type functional elements and devices.

[0017] The beneficial effects of the present utility model are as follows:

[0018] 1. The surface acoustic wave filter fabricated on the surface of the novel multi-layer heterogeneous bonding substrate invokes the buried functional elements and devices in the substrate, and has the advantages of short connection distance, high Q value, good reliability, and high spatial integration degree;

[0019] 2. The buried functional devices in the substrate, such as integrated passive filters, can be called in three-dimensional short distance, and a multiplexer or matching circuit can be formed by combining with surface acoustic wave filters on the substrate surface, which has better performance and spatial integration. At the same time, the preparation process of the new multi-layer heterogeneous bonding substrate can be divided into separate preparation of multiple parts of materials and finally bonded, with higher mass production efficiency;

[0020] 3. The surface acoustic wave filter fabricated on the multi-layer heterogeneous bonding substrate surface can call inductive elements in short distance, thus avoiding the use of substrates and directly performing die packaging or wafer-level packaging on the filter surface, reducing the filter usage space of the RF module;

[0021] 4. Functional devices added in the substrate, such as three-dimensional or two-dimensional integrated passive filters and surface acoustic wave filters on the wafer surface, are connected through a metal panel to construct a high-performance multiplexer. Description of the Drawings

[0022] In order to more clearly illustrate the specific embodiments of the present invention, the drawings required for use in the description of the specific embodiments will be briefly introduced below. The drawings in the following description are example diagrams of the above-mentioned new RF front-end receiving surface acoustic wave filter module. Obviously, the drawings described below are only exemplary. For those of ordinary skill in the art, without creative efforts, other embodiment drawings can be obtained according to the provided drawings.

[0023] Figure 1 . Structure diagram of the new multi-layer heterogeneous bonding substrate in Embodiment 1;

[0024] Figure 2 . Front top view of the new multi-layer heterogeneous bonding substrate in Embodiment 1;

[0025] Figure 3 . Simplified preparation process of the new multi-layer heterogeneous bonding substrate in Embodiment 1;

[0026] Figure 4 . Structure diagram of the double-sided functional wafer in the new multi-layer heterogeneous bonding substrate in Embodiment 2;

[0027] Figure 5 . Simplified preparation process of the double-sided functional wafer in the new multi-layer heterogeneous bonding substrate in Embodiment 2.

[0028] In the figure: 1 - First substrate layer; 2 - Functional element and device layer; 3 - Bonding layer; 4 - Second substrate layer; 5 - Absorbing layer; 6 - Isolation layer; 7 - Piezoelectric thin film layer; 8 - Top metal panel; 9 - Piezoelectric thin film surface; 10 - Metallized hole; 11 - Functional element and device; 12 - Metal panel; 13 - Reverse functional element and device; 14 - Reverse bonding layer; 15 - Third substrate layer; 16 - Reverse absorbing layer; 17 - Reverse isolation layer; 18 - Reverse thin film piezoelectric layer; 19 - Top panel of reverse metallized hole; 20 - Reverse metallized hole; 21 - Forward and reverse conduction type functional element and device; 22 - Filter panel; 23 - Left filter resonator region; 24 - Right filter resonator region. Detailed implementation mode

[0029] The exemplary embodiments of the present patent will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present patent are shown in the drawings, it should be understood that the present patent can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present patent and to fully convey the scope of the present patent to those skilled in the art. It should be noted that, without conflict, the embodiments in the present patent and the features in the embodiments can be combined with each other. The present patent will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0030] Embodiment 1

[0031] As Figure 1 、 Figure 2 shown, the present utility model provides a novel multi-layer heterogeneous bonding substrate structure, including a functional substrate layer and a wafer structure layer. In this embodiment, the wafer structure layer is a POI wafer. A bonding layer 3 is provided between the functional substrate layer and the wafer structure layer. The bottom surface of the wafer structure layer is aligned with the front surface of the functional substrate layer and is connected at the bonding layer 3 through various bonding methods. The wafer structure layer is provided with a metallized hole 10, and a top metal panel 8 and a bottom panel are respectively provided at both ends of the metallized hole 10. The top metal panel 8 is placed on the top of the wafer structure layer, and the bottom panel is placed on the top of the functional substrate layer.

[0032] The functional substrate layer includes a first substrate layer 1 and a functional element and device layer 2 fabricated on the surface of the first substrate layer 1. The first substrate layer 1 is an insulating layer made of a high acoustic velocity material, which is used to increase the barrier and suppress the longitudinal leakage of acoustic wave energy in the piezoelectric thin film layer, providing a supporting role for the fabrication of functional elements and devices. The material of the insulating layer is quartz, which can ensure insulation while having a relatively low dielectric loss, avoiding the influence at high frequencies of functional elements and devices. The front and back surfaces of the first substrate layer 1 are relatively flat, which can provide a better substrate for the interconnection of metal layers. In this embodiment, the functional element and device layer 2 is fabricated on the first substrate layer 1. The functional element and device layer 2 includes at least one metallized functional element and device 11, including integrated passive filters, capacitors, inductors, and interconnects. The metal patterns of the functional element and device 11 are fabricated on the substrate surface by semiconductor processing techniques using high conductivity metals, which include Ti, Cu, Al, Ni, Au. The dielectric is generally silicon oxide, polyimide, BCB, etc. The three-dimensional elements and devices are reflected in the multi-layer wiring. The multi-layer wiring requires copper filling using the damascene process to ensure the reliability of the connection. The spaces between the functional element and device 11 are filled with a dielectric. The dielectric material can be silicon dioxide, silicon nitride, polyimide, high-resistance silicon, glass, quartz, BCB (benzocyclobutene) material layer, PBO (poly(p-phenylene benzobisoxazole) fiber). The dielectric properties are low dielectric loss and high resistivity, with a resistance value above 2500 Ω·cm. The height of the dielectric filling is the same as the metal height of the functional element and device 11, and it is ensured that the interface of the functional element and device layer 2 reaches the bonding-level flatness after filling.

[0033] When fabricating the functional element and device layer 2, a position for the metal panel 12 is reserved. The position of the metal panel 12 corresponds to the bottom panel of the metallization hole 10. The functional element and device layer 2 leaves a metal panel 12 at the bottom of the through hole fabricated subsequently. The metal panel 12 is reserved when fabricating the functional element and device 11. After the subsequent metallization hole 10 opening wafer is aligned, it generally reaches the position of this metal panel 12, and signals are led out from this metal panel 12 to the top of the metallization hole 10. The functional element and device 11 are independently connected to the corresponding hole positions, and the interference between them is relatively small. Generally, all factors integrated in the layer, including the coupling interference between elements, etc., will be considered at the beginning of the design.

[0034] The wafer structure layer includes a second substrate layer 4, an absorption layer 5, an isolation layer 6, and a piezoelectric thin film layer 7 arranged in sequence from bottom to top. The material of the second substrate layer 4 is generally high-resistance silicon, and also includes silicon carbide, diamond, sapphire, and quartz, which have a relatively large resistance, generally in the range of 2500 Ω·cm to 3500 Ω·cm. Preferably, the resistivity of the high-resistance silicon material is 3000 Ω·cm. An absorption layer 5 needs to be fabricated above the second substrate layer 4. This layer is a polysilicon layer with a thickness of 0 - 2 μm, which is used to capture electrons and can improve the Q value of the device. The isolation layer 6 is made of the classic low-sound-speed material silicon dioxide above the absorption layer 5 and is used to form an acoustic reflection structure of low acoustic impedance / high acoustic impedance with the second substrate layer 4. The thickness of the isolation layer is 0 - 5 μm, and the isolation layer material contains silicon oxide, which is realized by thermal oxidation or PECVD. The upper surface of the piezoelectric thin film layer 7 is the piezoelectric thin film surface 9, which is the front surface of the wafer structure layer. The material of the piezoelectric thin film layer 7 is lithium niobate or lithium tantalate, and this layer of thin film is obtained by the smart-cut technology of He ion implantation, high-temperature annealing, and CMP polishing. After CMP, the surface roughness is reduced to within dozens of nanometers, and a surface acoustic wave filter is fabricated on the piezoelectric thin film surface 9. After the typical POI wafer preparation of the four layers of the second substrate layer 4, the absorption layer 5, the isolation layer 6, and the piezoelectric thin film layer 7 is completed, the POI wafer needs to be subjected to via etching at specified sites. The silicon TSV process is currently very mature. For the second substrate layer 4 with a maximum thickness of 500 μm, the TSV process is used to etch and open holes. The TSV process is also used to open holes in the absorption layer 5. For the isolation layer 6 and the piezoelectric thin film layer 7, due to their relatively thin thicknesses, metallization holes 10 can be prepared by physical bombardment etching.

[0035] The hole sidewall of the metallized hole 10 includes an insulating layer, an adhesion layer, and a conduction layer. Copper metallization electroplating solid filling is carried out in the through hole. After the electroplating solid filling is completed, high-temperature annealing and CMP polishing are required to remove the surface electroplated metal, leaving the hole surface metal and the piezoelectric thin film material. The layout of the metallized holes 10 is divided into multiple specifications. Under each specification, the size and arrangement position of the metallized holes are different. Under a certain specification, the size and arrangement of the metallized holes are fixed, which is convenient for the functional components and device layer to be redesigned before production according to the design requirements of the acoustic device on the surface of the piezoelectric thin film layer. After the production of the through hole is completed, a silicon dioxide insulating layer also needs to be deposited on the sidewall of the metallized hole 10 to protect the insulation between the metal in the through hole and the semiconductor silicon. Generally, CVD is used for deposition to ensure uniform deposition of the film layer in the hole. After the deposition of the silicon oxide thin film, an adhesion layer and an electroplating seed layer are deposited and prepared, and the metal copper in the through hole is thickened by electroplating to ensure that the metal in the hole can conduct the front and back sides of the POI wafer with low loss. Solid filling of metal copper is carried out by copper metallization electroplating in the metallized hole 10. After the bottom of the metallized hole 10 is aligned with the bottom panel 12 led out by the functional components and device 11, welding is performed, and a metal panel 8 for interconnection is fabricated at the top of the metallized hole 10. After the surface acoustic wave filter on the surface of the wafer structure layer is fabricated, only one pattern deposition is required to lead out the functional components and device 11 in the hole.

[0036] There are various bonding methods for the bonding layer 3. The surface of the functional component and device layer 2 is connected to the bottom surface of the wafer structure layer through various bonding methods, including bonding the upper surface of the functional component and device 2 and the bottom surface of the second bottom layer 4 at the bottom of the circular structure layer by means of low-temperature plasma activation. The bonding method can fabricate the bonding layer 3 on the surface of the functional component and device layer 2 and fabricate the bonding layer 3 on the bottom surface of the bottom layer 4, and realize flexible bonding through the bonding layer-bonding layer method. The materials of the bonding layer 3 include Au, Cu, Al, Ti, SiO 2 , SiN, Si, and bonding glue; an atomic-level thickness bonding layer can appear through plasma-activated low-temperature bonding, or a metal layer can be fabricated on the layer surface, and then a metal-bonded layer is formed through bonding under high temperature and high pressure.

[0037] As Figure 2 shown, the metallized through hole 10 leads to the surface 9 of the piezoelectric thin film layer. The size of the entire device is 2.5 mm in length and 2 mm in width. There are many metallized holes 10 distributed on the surface of the piezoelectric thin film layer. These metallized holes 10 respectively correspond to the connections of the functional components and device 11. Among them, the size of the filter resonator area 23 on the left is 1.6 mm in length and 1.1 mm in width, and the size of the filter resonator area 24 on the right is 1.6 mm in length and 0.9 mm in width. For the filter panel 22 on the filter, an interconnection pattern can be deposited on the surface to the calibrated metal holes, thereby realizing denser interconnection.

[0038] AsFigure 3 As shown, the general preparation process of this embodiment is as follows. The detailed manufacturing process can be referred to as follows:

[0039] 1) Provide a double-sided polished and flat piezoelectric single crystal material. The thickness of this piezoelectric single crystal material reaches 100 - 200 um and it belongs to bulk material. After subsequent ion implantation and annealing and stripping, it becomes the piezoelectric thin film layer 7. The piezoelectric single crystal material is in a certain tangential direction, and in this tangential direction, the comprehensive performance of the surface acoustic wave filter can be better. The comprehensive performance of the filter includes passband insertion loss, bandwidth, and quality factor. Preferably, the piezoelectric material in this embodiment is 15°YX - lithium niobate. The piezoelectric single crystal material includes opposite first surface and second surface, and the first surface is the surface for He + implantation.

[0040] 2) Inject He + into the lithium niobate wafer. The implantation ion energy is selected according to the required thin film thickness (i.e., implantation depth). In this embodiment, a 600 - nm lithium niobate thin film is required.

[0041] 3) Provide a high-resistance silicon substrate as the second substrate layer 4 of the novel multi-layer hetero-bonded substrate. The thickness of the high-resistance silicon substrate is 500 um. The high-resistance silicon substrate is divided into a first surface and a second surface. Sputter a polysilicon thin film on the first surface. This thin film serves as the absorption layer 5, which can capture the leaked electrons in the wafer and improve the Q value of the device. The thickness of the polysilicon thin film is generally less than that of the second substrate layer. Preferably, the thickness of the absorption layer in this embodiment is 1 um.

[0042] 4) Fabricate a silicon oxide thin film on the polysilicon surface of the absorption layer 5. The silicon oxide thin film constitutes the acoustic low-impedance layer, that is, the isolation layer 6. The silicon oxide thin film can be grown on the polysilicon surface by thermal oxidation. The required thickness of the polysilicon is approximately the sum of the thickness of the grown silicon oxide and the reserved thickness of the absorption layer. The interface between the silicon oxide and the polysilicon is perfectly bonded in this growth mode. The silicon oxide thin film can also be prepared by sputtering. By adjusting parameters such as the atmosphere pressure of magnetron sputtering O 2 and Ar and the ionization intensity of the electric field, the purity and density of the generated silicon dioxide are adjusted. Preferably, in this embodiment, the silicon target reacts with ionized O and under the action of the bias voltage, a dense silicon dioxide is generated on the wafer surface.

[0043] 5) The piezoelectric wafer and the silicon oxide wafer show a better activation effect than Ar under the activation of O 2 , N 2 plasma, forming strong hydrophilicity, which is conducive to hydrophilic bonding. Then, place the piezoelectric wafer and the silicon oxide wafer in O 2 and N 2Plasma activation under an atmosphere, which has physical and chemical effects, can remove impurities, break chemical bonds, and form hydroxyl groups and hydrogen bonds on the surface through reaction with water, enhancing hydrophilicity; in the bonding process, the surface roughness of the wafer affects the bonding effect. After plasma activation, megasonic cleaning is required. Megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through acoustic pressure and acoustic streaming effects, ensuring no pollutant residues and providing a high-quality basis for the bonding process. Preferably, in this embodiment, megasonic cleaning is performed at a power of 300W for 120s.

[0044] 6) Align and contact the first surface of the piezoelectric single-crystal material and the first surface of the silicon oxide wafer after activation and cleaning, with the activation surfaces facing each other. At this time, both the surfaces of lithium niobate and the silicon oxide wafer have appropriate hydroxyl densities. By applying pressure, the hydroxyl groups on the two wafer surfaces are close enough, and at room temperature, a dehydration condensation reaction occurs spontaneously through interfacial forces to achieve atomic-level wafer bonding.

[0045] 7) Annealing for reinforcement. The interfacial energy will increase after the pre-bonded wafers are stored at room temperature, mainly because H 2 O molecules gradually diffuse along the bonding interface into the air or the SiO 2 layer. High-temperature annealing can accelerate this process to form a stable connection, enhance the bonding strength, and reduce bubbles; however, conventional annealing easily causes wafer cracking due to the large difference in the thermal expansion coefficients of the lithium niobate crystal and silicon. The stepped heating and cooling annealing process can relieve stress. In this embodiment, the pre-bonded wafers are subjected to stepped annealing for reinforcement, rising from room temperature to 90°C at a rate of 1°C / min, holding at this temperature for 5h, then continuing to rise to 150°C at a rate of 1°C / min and maintaining for 10h, and subsequently cooling to room temperature at a rate of 1°C / min.

[0046] 8) Performance characterization. Bonding strength is one of the most important measured characteristics in the bonding process. Low strength may cause wafer cracking. In this embodiment, the double cantilever beam test method is used to evaluate the bonding strength by measuring the crack length. The measured bonding strength in the embodiment reaches 1.91J / cm 2 , which can withstand mechanical, thermal, and hydrostatic stress corrosion during subsequent processing, providing a solid foundation for wafer peeling and device fabrication.

[0047] 9) Preparation of the piezoelectric thin film layer. First, maintain at 165°C for 16h, then anneal at 190°C for 6h to further improve the bonding strength, and then raise the sample temperature to about 228°C to separate the He + implantation layer from the lithium niobate donor material.

[0048] 10) Double-sided grinding. Perform CMP grinding on both the front and back surfaces of the prepared POI wafer, namely the second surface (back surface) of the high-resistance silicon substrate and the piezoelectric thin film surface.

[0049] 11) Fabricate a soft mask material on the surface of the piezoelectric thin film layer. In this embodiment, photoresist HSQ is used, and holes to be etched are fabricated after photolithography and development.

[0050] 12) Use an Ar ion etcher to etch the thin film layer including the piezoelectric thin film layer and the isolation layer. Adjust the voltage of the Ar ions and the gas atmosphere, and control the sidewall angle of the hole etching to make the sidewall etching close to a vertical angle.

[0051] 13) Use a mature TSV process to etch the polysilicon layer and the high-resistivity silicon layer, and ultrasonically clean to remove impurities in the holes. 14) Sputter an insulating layer on the inner hole wall of the through hole. In this embodiment, a 300nm silicon oxide layer is sputtered, a 300nm metal Ti is sputtered and deposited, and a 3000nm electroplating seed layer Cu is electroplated. In this embodiment, a sputtering machine tool with an aspect ratio coverage ability greater than 5:1 is selected to achieve uniform coverage of the hole wall insulating layer, the adhesion layer, and the electroplating seed layer.

[0052] 15) Electroplate the metallized through hole. In this embodiment, the electroplating solution formula is adjusted to make the metal copper in the through hole solidify and fill.

[0053] 16) Double-sided grinding and polishing. Perform CMP grinding treatment on the front and back surfaces of the prepared POI wafer, that is, the second surface (back surface) of the high-resistivity silicon substrate and the piezoelectric thin film surface until the surface of the piezoelectric thin film layer is completely exposed, and polish to reduce the roughness to below 5 Å to achieve bonding-level flatness.

[0054] 17) Fabricate functional elements and devices on the insulating first substrate. In this embodiment, two-dimensional and three-dimensional inductive windings of metal Cu are fabricated on a quartz substrate to form inductors and integrated passive filters. Fill the gaps between the inductors with dielectric silicon dioxide, and after curing, grind the surface flat with CMP. Grind off the silicon dioxide covering the surface, and the grinding time is determined by completely exposing the metal signal panel of the functional element and device layer.

[0055] 18) The functional element and device wafer and the composite multi-layer heterogeneous wafer POI show better activation effect than Ar under O

[0056] 18) The functional element and device wafer and the composite multi-layer heterogeneous wafer POI show better activation effect than Ar under O 2 、N 2 plasma activation, forming strong hydrophilicity, which is beneficial to hydrophilic bonding. And place the wafer in O 2 and N 2Plasma activation in an atmosphere, which has physical and chemical effects, can remove impurities, break chemical bonds, and form hydroxyl groups and hydrogen bonds on the surface by reacting with water, enhancing hydrophilicity. In the bonding process, the surface roughness of the wafer affects the bonding effect. After plasma activation, megasonic cleaning is required. Megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through acoustic pressure and acoustic streaming effects, ensuring no pollutant residues and providing a high-quality basis for the bonding process. Preferably, in this embodiment, megasonic cleaning is performed at a power of 300W for 120s.

[0057] 19) Align and contact the first surface (front side) of the functional element and device wafer that has undergone activation and cleaning with the second surface (bottom side) of the composite multi-layer heterogeneous wafer POI. At this time, both the surfaces of the lithium niobate and silicon oxide wafers have appropriate hydroxyl densities. By applying pressure, the hydroxyl groups on the two wafer surfaces are close enough.

[0058] At room temperature, a dehydration condensation reaction is spontaneously formed by interfacial force bonding to achieve atomic-level wafer bonding.

[0059] 20) Annealing and strengthening. In this embodiment, stepwise annealing and strengthening are performed on the pre-bonded wafers. The temperature is raised from room temperature to 90°C at a rate of 1°C / min, held at this temperature for 5h, and then continued to be raised to 150°C at a rate of 1°C / min

[0060] and held for 10h, and then cooled to room temperature at a rate of 1°C / min. The bonding strength tested in the embodiment reaches 1.95J / cm 2 and can withstand mechanical, thermal, and water stress corrosion during subsequent processing.

[0061] 21) Fabricate a metal region for connection at the hole position on the surface of the thin-film lithium niobate to provide connection points for the connection of subsequent surface acoustic wave filters.

[0062] Embodiment 2:

[0063] As Figure 4 shown, the functional substrate layer is also connected to an inverted wafer structure layer, that is, an inverted POI wafer. The structure of the inverted wafer structure is centrosymmetric with respect to the wafer structure layer along the functional substrate layer. The inverted wafer structure and the wafer structure layer are independent of each other. The functional substrate layer includes a functional element and device layer 2. The functional element and device layer 2 includes independent functional elements and devices 11, reverse-side functional elements and devices 13, and forward and reverse conduction type functional elements and devices 21. Other technical features are the same as those in Embodiment 1.

[0064] In this embodiment, the wafer is divided into two sides, namely the POI wafer and the inverted POI wafer. The front side is the first surface, and the back side is the second surface. The wafer includes a thin film piezoelectric layer 7, an isolation layer 6, an absorption layer 5, a second substrate layer 4, a bonding layer 3, a functional element and device layer 2, a back bonding layer 14, a third substrate layer 15, a back absorption layer 16, a back isolation layer 17, and a back thin film piezoelectric layer 18. The POI wafer is provided with a metallization hole 10, and the metallization hole 10 is connected to the top metal panel 8. The inverted POI wafer is provided with a back metallization hole 20, and the back metallization hole 20 is connected to the top panel of the back metallization hole 19. The functional element and device layer 2 is located in the middle layer of the entire wafer, facilitating short-distance calls between the front and back sides of the wafer. The elements and devices of the functional element and device 2 are independent of each other, including the front functional element and device 11, the back functional element and device 13, and the forward and reverse conduction type functional element and device 21, and each points to a clear via position. The elements and devices are made of metal for their circuits, and the gap parts are filled with a dielectric. The dielectric material is generally materials such as silicon dioxide, polyimide, and BCB. The upper and lower surfaces of the functional element and device layer 2 are flat and are bonded to the second substrate layer 4 and the third substrate layer 15 respectively. There are various bonding methods, which can be low-temperature bonding by plasma activation, or bonding by using glue at the interface, or metal-metal bonding. The second substrate layer 4 and the third substrate layer 15 are high sound velocity substrates. In this embodiment, high-resistance silicon materials are used, with a thickness of 500 um. A polysilicon layer, namely the absorption layer 5 and the back absorption layer 16, is sputtered on the surfaces of the second substrate layer 4 and the third substrate layer 15 respectively to absorb electrons and improve the Q value of the device. The thickness of the polysilicon can be determined according to the subsequent process path. Considering that the materials of the isolation layer 6 and the back isolation layer 17 are silicon dioxide and are made by thermal oxidation, the thickness of the polysilicon should be larger. The isolation layer 6 and the back isolation layer 17 of silicon dioxide are made by PECVD, and the thickness of the polysilicon can be in the micron level. The piezoelectric thin film layer 7 and the back piezoelectric thin film layer 18 are respectively located above the isolation layer 6 and the back isolation layer 17.

[0065] After all the above layers are fabricated, the preparation of the metallization hole 10 and the back metallization hole 20 is carried out. In the embodiment, physical bombardment is used to bombard and etch the piezoelectric thin film layer 7, the back piezoelectric thin film layer 18, the isolation layer 6, and the silicon dioxide of the back isolation layer 17 to obtain holes with a thickness in the micron level, and the polysilicon and high-resistance silicon are etched away by the mature silicon TSV process until etching reaches the metal panel part of the functional element and device layer 2. An insulating layer of silicon dioxide with a thickness of several hundred nanometers is sputtered and deposited on the side walls of the holes, and the silicon dioxide layer at the bottom of the holes is removed by physical etching in a directional manner. After cleaning and spin-drying, an adhesion layer Ti and an electroplating seed layer of copper are deposited, and electroplating is used to fill the holes in the hole walls solidly. Compared with Embodiment 1, the biggest difference in this embodiment lies in the preparation of the double-sided functional layer, and there will be differences in the process.

[0066] As Figure 5 shown, the preparation process is as follows: First, an inverted POI wafer is fabricated according to the POI fabrication method of Embodiment 1. A temporary protective layer is fabricated on the surface of the thin-film piezoelectric layer 18 on the reverse side. Reverse-side functional elements and devices 13 are fabricated on the back surface of the third substrate layer 15. The functional element and device layer 2 is divided into a first surface connected to the inverted POI wafer and a second surface connected to the POI wafer. The area of the lead-out metal panel of the functional elements and devices 11 is larger than the opening area of the subsequent inverted POI wafer. An opening is made in the inverted POI wafer. First, the thin-film lithium niobate and silicon oxide layer are etched away by physical etching. Immediately afterwards, the polysilicon and high-resistance silicon are etched away by silicon TSV process, and a dielectric silicon oxide layer, a metal adhesion layer, and an electroplating seed layer are covered on the sidewalls. The via holes are filled with electroplated copper metal. After high-temperature annealing, grinding is carried out to remove the electroplated metal layers on both the front and back sides of the inverted POI wafer. Reverse-side functional elements and devices 13 are fabricated on the surface of the substrate layer of the inverted POI wafer, and a dielectric is filled between the reverse-side functional elements and devices 13. In this embodiment, the dielectric is silicon dioxide. After filling, CMP is used to polish it flat until the surface of the functional element and device layer is exposed until the dielectric and metal coexistence surface is exposed, and the surface roughness reaches the wafer bonding level. Immediately afterwards, the POI wafer is prepared. The material parameters of the POI wafer and the inverted POI wafer are independent of each other. Via holes are prepared in the POI wafer, and the via holes are covered with an insulating layer of silicon dioxide. The via hole metal adhesion layer and the electroplating seed layer are sputter-coated. Solid electroplated metal is filled. CMP grinding is used to remove the electroplated copper metal on the surface. The front and back sides of the POI wafer are polished to achieve the flatness of the bonding level. Then, the bottom surface of the POI wafer and the bottom surface of the inverted POI wafer (i.e., the surface of the functional element and device layer 2) are wafer-wafer bonded. The bonding method is the low-temperature bonding described in Embodiment 1. Then, the temporary protective layer on the surface of the reverse-side thin-film piezoelectric layer 18 of the inverted POI wafer is removed, and a metal interconnect area is fabricated in the double-sided metal holes.

[0067] It should be specifically noted that the content of this article and the exemplary embodiments are only used to illustrate the technical solutions of this patent, but the implementation manners of this patent are not limited by the above content. Any other changes, modifications, substitutions, combinations, etc. made without departing from the innovative essence and principle of this patent, such as the second substrate layer 4, the absorption layer 5, the isolation layer 6, and the thin-film piezoelectric layer 7 are fabricated layer by layer or fabricated in pairs first and then made into a POI wafer, are all included in the protection scope of this patent. For those skilled in the art, the specific meanings of the above terms in the patent can be understood according to the specific circumstances.

Claims

1. A novel multi-layer heterogeneous bonding substrate structure, characterized in that: The invention comprises a functional substrate layer and a wafer structure layer, wherein a bonding layer (3) is arranged between the functional substrate layer and the wafer structure layer, the bottom surface of the wafer structure layer is aligned with the front surface of the functional substrate layer and connected at the bonding layer (3) by a plurality of bonding methods, the wafer structure layer is provided with a metallized hole (10), and the two ends of the metallized hole (10) are respectively provided with a top metal panel (8) and a bottom panel, the top metal panel (8) is arranged on the top of the wafer structure layer, and the bottom panel is arranged on the top of the functional substrate layer.

2. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The functional substrate layer comprises a first substrate layer (1) and a functional element and device layer (2) manufactured on the surface of the first substrate layer (1); a position of a metal panel (12) is reserved when the functional element and device layer (2) are manufactured; the position of the metal panel (12) corresponds to the bottom panel of the metallized hole (10).

3. The novel multi-layer heterogeneous bonding substrate structure according to claim 2, characterized in that: The functional element and device layer (2) comprises at least one functional element and device (11), wherein the functional element and device (11) may be a two-dimensional or three-dimensional element or device, and the spaces between the functional elements and devices (11) are filled with a medium.

4. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The wafer structure layer comprises a second substrate layer (4), an absorption layer (5), an isolation layer (6) and a piezoelectric film layer (7) which are arranged in sequence from bottom to top.

5. The novel multi-layer heterogeneous bonding substrate structure according to claim 4, characterized in that: The surface of the piezoelectric film layer (7) is the front side of the wafer structure layer, and a surface acoustic wave filter is manufactured on the surface of the piezoelectric film layer (7).

6. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The hole sidewall of the metallized hole (10) comprises an insulating layer, an adhesive layer and a conductive layer, and the metallized hole (10) is solidly filled with copper metallization electroplating.

7. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The layout of the metallized holes (10) is divided into multiple specifications, and the size and arrangement position of the metallized holes are different in each specification.

8. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The bonding layer (3) has a variety of bonding methods. A bonding layer with atomic-level thickness can be formed by plasma activation and low-temperature bonding. A metal layer can also be made on the surface of the layer and then bonded under high temperature and high pressure to form a metal bonding layer.

9. The novel multi-layer heterogeneous bonding substrate structure according to claim 1, characterized in that: The functional substrate layer is also connected to an inverted wafer structure layer, each layer structure of the inverted wafer structure layer is centrally symmetrical with each layer structure of the wafer structure layer along the functional substrate layer, and each layer parameter of the inverted wafer structure layer is independent of each layer parameter of the wafer structure layer.

10. The novel multi-layer heterogeneous bonding substrate structure according to claim 9, characterized in that: The functional substrate layer comprises a functional element and device layer (2), wherein the functional element and device layer (2) comprises mutually independent functional elements and devices (11), wafer reverse side functional elements and devices (13), and forward and reverse conduction type functional elements and devices (21).

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