Silicon-based liquid crystal chip, silicon-based liquid crystal chip assembly and display device

Abstract

The utility model relates to a silicon-based liquid crystal chip, a silicon-based liquid crystal chip assembly and a display device. The silicon-based liquid crystal chip comprises a semiconductor substrate which is provided with a central area and a peripheral area which are adjacent to each other; the driving circuit is arranged in the central area of the semiconductor substrate; the peripheral circuit is arranged in the peripheral area of the semiconductor substrate and is electrically connected with the driving circuit; the shielding capacitor is arranged in the peripheral area and electrically connected with the peripheral circuit, and the shielding capacitor is used for shielding interference signals flowing through the peripheral circuit. The use performance and reliability of the silicon-based liquid crystal chip, the silicon-based liquid crystal chip assembly and the display device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of liquid crystal display, and particularly to a liquid crystal on silicon (LCOS) chip, an LCOS chip assembly, and a display device. Background Art

[0002] Liquid Crystal On Silicon (LCOS) is a new type of reflective micro liquid crystal display technology. Compared with LCD (Liquid Crystal Display), LCOS technology can increase the aperture ratio of the display interface, thereby achieving greater light output and higher resolution. Existing LCOS chips are vulnerable to signal interference during use, which has an adverse impact on the performance and reliability of LCOS chips. Summary of the Invention

[0003] Based on this, in view of the problem that LCOS chips are vulnerable to signal interference during use, it is necessary to provide an LCOS chip, an LCOS chip assembly, and a display device.

[0004] In a first aspect, the present application provides an LCOS chip, including:

[0005] A semiconductor substrate having an adjacent central region and peripheral region thereon;

[0006] A driving circuit disposed in the central region of the semiconductor substrate;

[0007] A peripheral circuit disposed in the peripheral region of the semiconductor substrate and electrically connected to the driving circuit; and

[0008] A shielding capacitor disposed in the peripheral region and electrically connected to the peripheral circuit, the shielding capacitor being used to shield interference signals flowing through the peripheral circuit.

[0009] In one embodiment, the peripheral circuit includes a first power supply signal line electrically connected to the driving circuit;

[0010] The shielding capacitor includes a first capacitor structure, one plate of the first capacitor structure being electrically connected to the first power supply signal line, the first capacitor structure being used to shield interference signals flowing through the first power supply signal line.

[0011] In one embodiment, the peripheral circuit further includes a first ground signal line electrically connected to the driving circuit;

[0012] The first capacitor structure includes a first plate and a second plate, the first plate being electrically connected to the first power supply signal line, and the second plate being electrically connected to the first ground signal line.

[0013] In one embodiment, the first power supply signal line includes a first metal trace and a first contact pad. One end of the first metal trace is electrically connected to the driving circuit, and the other end of the first metal trace is electrically connected to the first contact pad.

[0014] The first ground signal line includes a second metal trace and a second contact pad. One end of the second metal trace is electrically connected to the driving circuit, and the other end of the second metal trace is electrically connected to the second contact pad.

[0015] Wherein, the first electrode plate is disposed between the first contact pad and the driving circuit and is connected to the first metal trace; the second electrode plate is disposed between the second contact pad and the driving circuit and is connected to the second metal trace.

[0016] In one embodiment, the peripheral circuit further includes a second power supply signal line electrically connected to the driving circuit, and the voltage of the second power supply signal line is different from the voltage of the first power supply signal line.

[0017] The shielding capacitor includes a second capacitor structure. One electrode plate of the second capacitor structure is electrically connected to the second power supply signal line, and the second capacitor structure is used to shield interference signals flowing through the second power supply signal line.

[0018] In one embodiment, the peripheral circuit further includes a second ground signal line electrically connected to the driving circuit.

[0019] The second capacitor structure includes a third electrode plate and a fourth electrode plate. The third electrode plate is electrically connected to the second power supply signal line, and the fourth electrode plate is electrically connected to the second ground signal line.

[0020] In one embodiment, the second power supply signal line includes a third metal trace and a third contact pad. One end of the third metal trace is electrically connected to the driving circuit, and the other end of the third metal trace is electrically connected to the third contact pad.

[0021] The second ground signal line includes a fourth metal trace and a fourth contact pad. One end of the fourth metal trace is electrically connected to the driving circuit, and the other end of the fourth metal trace is electrically connected to the fourth contact pad.

[0022] Wherein, the third electrode plate is disposed between the third contact pad and the driving circuit and is connected to the third metal trace; the fourth electrode plate is disposed between the fourth contact pad and the driving circuit and is connected to the fourth metal trace.

[0023] In one embodiment, the liquid crystal on silicon (LCOS) chip further includes an antioxidant layer, which is disposed on the side of the driving circuit away from the semiconductor substrate and on the side of the peripheral circuit away from the semiconductor substrate; the shielding capacitor is disposed on the side of the antioxidant layer away from the semiconductor substrate;

[0024] Via holes are provided in the antioxidant layer, and conductive structures are provided in the via holes. The shielding capacitor is electrically connected to the peripheral circuit by means of the conductive structures.

[0025] In a second aspect, an embodiment of the present application provides a liquid crystal on silicon (LCOS) chip assembly, including:

[0026] A substrate;

[0027] A circuit board, which is disposed on the substrate;

[0028] The liquid crystal on silicon (LCOS) chip in the embodiment of the first aspect is disposed on the circuit board and is electrically connected to the circuit board;

[0029] A liquid crystal module, which is disposed on the liquid crystal on silicon (LCOS) chip and is electrically connected to the driving circuit of the liquid crystal on silicon (LCOS) chip.

[0030] In a third aspect, an embodiment of the present application provides a display device, including the liquid crystal on silicon (LCOS) chip assembly in the second aspect.

[0031] The liquid crystal on silicon (LCOS) chip, the liquid crystal on silicon (LCOS) chip assembly and the display device provided by the embodiments of the present application electrically connect the shielding capacitor to the peripheral circuit. On the one hand, it can shield the interference signals flowing through the peripheral circuit, reduce the possibility of the interference signals being conducted to the driving circuit, and thus reduce the influence of the interference signals on the driving circuit; on the other hand, by providing the shielding capacitor in the peripheral area and electrically connecting the shielding capacitor to the peripheral circuit, the routing path length between the shielding capacitor and the driving circuit can be minimized, and thus the influence of the interference signals on the line on the driving circuit can be minimized; in summary, the present application can improve the performance and reliability of the liquid crystal on silicon (LCOS) chip, the liquid crystal on silicon (LCOS) chip assembly and the display device. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 It is a schematic structural diagram of a liquid crystal on silicon (LCOS) chip provided by an embodiment of the present application.

[0034] Figure 2 is Figure 1 the top view of the silicon-based liquid crystal chip shown

[0035] Figure 3 is Figure 1 the structural schematic diagram of the shielding capacitor of the silicon-based liquid crystal chip shown

[0036] Figure 4 is the structural schematic diagram of a silicon-based liquid crystal chip component provided by an embodiment of the present application

[0037] Figure 5 is Figure 1 the top view of a partial structure of the silicon-based liquid crystal chip component shown

[0038] Figure 6 is the functional module schematic diagram of a display device provided by an embodiment of the present application

[0039] Description of reference numerals:

[0040] 1. Display device; 10. Silicon-based liquid crystal chip component; 11. Silicon-based liquid crystal chip; 111. Semiconductor substrate; 111a. Central region; 111b. Peripheral region; 112. Driving structure layer; 112a. Driving circuit; 112b. Peripheral circuit; 112b1. First power signal line; 112b11. First metal trace; 112b12. First contact pad; 112b2. First ground signal line; 112b21. Second metal trace; 112b22. Second contact pad; 112b3. Second power signal line; 112b31. Third metal trace; 112b32. Third contact pad; 112b4. Second ground signal line; 112b41. Fourth metal trace; 112b42. Fourth contact pad; 112c. Pixel electrode; 113. Shielding capacitor; 1131. First capacitor structure; 11311. First electrode plate; 11312. Second electrode plate; 1132. Second capacitor structure; 11321. Third electrode plate; 11322. Fourth electrode plate; 114. Anti-oxidation layer; 115. Conductive structure; 12. Substrate; 13. Circuit board; 131. First connection pad group; 132. Second connection pad group; 14. Liquid crystal component; 20. Light source; 30. Projection lens; 40. Housing Detailed implementation manners

[0041] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over" and the like are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also have other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0044] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" or the like specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0045] As described in the background art, existing LCOS chips are vulnerable to signal interference during use, which has an adverse impact on the performance and reliability of the LCOS chips.

[0046] The inventors have found through research that the main reasons for signal interference are as follows: one is the noise interference from the external power supply; the second is the noise interference between each circuit module; and the third is the signal interference between adjacent lines.

[0047] In view of the above problems, embodiments of the present application provide a liquid crystal on silicon (LCOS) chip, an LCOS chip assembly, and a display device. By providing a shielding capacitor and electrically connecting the shielding capacitor to the peripheral circuit, on the one hand, interference signals flowing through the peripheral circuit can be shielded, reducing the possibility of the interference signals being conducted to the driving circuit, thereby reducing the impact of the interference signals on the driving circuit. On the other hand, by providing the shielding capacitor in the peripheral area and electrically connecting the shielding capacitor to the peripheral circuit, the routing path length between the shielding capacitor and the driving circuit can be minimized, thereby minimizing the impact of the interference signals on the driving circuit. In summary, the present application can improve the performance and reliability of the LCOS chip, the LCOS chip assembly, and the display device.

[0048] In a first aspect, as shown in Figure 1 and Figure 2 , embodiments of the present application provide an LCOS chip 11. The LCOS chip 11 includes a semiconductor substrate 111, a driving circuit 112a, a peripheral circuit 112b, and a shielding capacitor 113. An adjacent central area 111a and a peripheral area 111b are provided on the semiconductor substrate 111. Exemplarily, the peripheral area 111b can surround the central area 111a. The driving circuit 112a is provided in the central area 111a of the semiconductor substrate 111. The peripheral circuit 112b is provided in the peripheral area 111b of the semiconductor substrate 111 and is electrically connected to the driving circuit 112a. The shielding capacitor 113 is provided in the peripheral area 111b and is electrically connected to the peripheral circuit 112b. The shielding capacitor 113 is used to shield interference signals flowing through the peripheral circuit 112b.

[0049] It should be noted that the semiconductor substrate 111 can be a silicon substrate, a silicon-germanium substrate, or a substrate made of other semiconductor materials. The LCOS chip 11 further includes a driving structure layer 112, and both the driving circuit 112a and the peripheral circuit 112b are provided on the driving structure layer 112. It can be understood that the driving structure layer 112 can include multiple metal layers and insulating layers located between adjacent two metal layers. Further, a plurality of pixel electrodes 112c are also provided on the driving structure layer 112. The driving circuit 112a in the embodiments of the present application can include multiple driving units, and each driving unit is electrically connected to a corresponding pixel electrode 112c.

[0050] The liquid crystal on silicon chip 11 provided by the embodiment of the present application, by providing a shielding capacitor 113 and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, on the one hand, can shield the interference signals flowing through the peripheral circuit 112b, reducing the possibility of the interference signals being conducted to the driving circuit 112a, thereby reducing the influence of the interference signals on the driving circuit 112a; on the other hand, by providing the shielding capacitor 113 in the peripheral area 111b and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, the routing path length between the shielding capacitor 113 and the driving circuit 112a can be minimized, that is: the circuit path between the shielding capacitor 113 and the driving circuit 112a is short, thereby minimizing the influence of the interference signals generated between adjacent lines on the driving circuit 112a; in summary, the present application can improve the performance and reliability of the liquid crystal on silicon chip 11.

[0051] In one embodiment, the peripheral circuit 112b includes a first power supply signal line 112b1 electrically connected to the driving circuit 112a. The shielding capacitor 113 includes a first capacitor structure 1131, and one plate of the first capacitor structure 1131 is electrically connected to the first power supply signal line 112b1. The first capacitor structure 1131 is used to shield the interference signals flowing through the first power supply signal line 112b1.

[0052] It should be noted that through the research of the inventor, it is found that power supply noise is one of the main factors causing signal interference. By electrically connecting one plate of the first capacitor structure 1131 to the first power supply signal line 112b1, the first capacitor structure 1131 can play a role in filtering power supply noise, thereby improving the performance and reliability of the liquid crystal on silicon chip 11.

[0053] It can be understood that the other plate of the first capacitor structure 1131 can be electrically connected to other signal lines. Exemplarily, the other plate can be electrically connected to a signal line for providing a fixed potential to the first capacitor structure 1131.

[0054] It should be noted that the number of the first capacitor structures 1131 can be multiple, and the multiple first capacitor structures 1131 are all electrically connected to the first power supply signal line 112b1. In this way, the shielding effect can be improved, and the performance and reliability of the liquid crystal on silicon chip 11 can be further improved.

[0055] In one embodiment, the peripheral circuit 112b further includes a first ground signal line 112b2 electrically connected to the driving circuit 112a. The first capacitor structure 1131 includes a first electrode plate 11311 and a second electrode plate 11312. The first electrode plate 11311 is electrically connected to the first power signal line 112b1, and the second electrode plate 11312 is electrically connected to the first ground signal line 112b2. Thus, by means of the first ground signal line 112b2, the second electrode plate 11312 is maintained at a stable potential, which is beneficial to reducing the routing density in the peripheral area 111b and at the same time reducing the manufacturing difficulty of the liquid crystal on silicon chip 11.

[0056] In one embodiment, the first power signal line 112b1 includes a first metal trace 112b11 and a first contact pad 112b12. One end of the first metal trace 112b11 is electrically connected to the driving circuit 112a, and the other end of the first metal trace 112b11 is electrically connected to the first contact pad 112b12. The first ground signal line 112b2 includes a second metal trace 112b21 and a second contact pad 112b22. One end of the second metal trace 112b21 is electrically connected to the driving circuit 112a, and the other end of the second metal trace 112b21 is electrically connected to the second contact pad 112b22. Among them, the first electrode plate 11311 is disposed between the first contact pad 112b12 and the driving circuit 112a and is connected to the first metal trace 112b11; the second electrode plate 11312 is disposed between the second contact pad 112b22 and the driving circuit 112a and is connected to the second metal trace 112b21.

[0057] It can be understood that both the first contact pad 112b12 and the second contact pad 112b22 are used to connect to the connection pads on the circuit board 13, so as to realize signal access. By disposing the first electrode plate 11311 between the first contact pad 112b12 and the driving circuit 112a and connecting it to the first metal trace 112b11, and disposing the second electrode plate 11312 between the second contact pad 112b22 and the driving circuit 112a and connecting it to the second metal trace 112b21, the circuit path length between the first capacitor structure 1131 and the driving circuit 112a can be maximally reduced, thereby maximally reducing the influence of the interference signals generated between adjacent lines on the driving circuit 112a.

[0058] In one embodiment, the peripheral circuit 112b further includes a second power signal line 112b3 electrically connected to the driving circuit 112a, and the voltage of the second power signal line 112b3 is different from the voltage of the first power signal line 112b1. The shielding capacitor 113 includes a second capacitor structure 1132. One electrode plate of the second capacitor structure 1132 is electrically connected to the second power signal line 112b3, and the second capacitor structure 1132 is used to shield the interference signals flowing through the second power signal line 112b3.

[0059] It can be understood that multiple power supply signal lines with different voltages are usually provided on the peripheral circuit 112b. By setting shielding capacitors 113 on different power supply signal lines, the power supply noise can be minimized, which is beneficial to further improving the performance and reliability of the liquid crystal on silicon chip 11.

[0060] In one example, the voltage of the first power supply signal is 5V, and the voltage of the second power supply signal is 1.8V.

[0061] It can be understood that the other plate of the second capacitor structure 1132 can be electrically connected to other signal lines. Exemplarily, the other plate can be electrically connected to a signal line for providing a fixed potential to the second capacitor structure 1132.

[0062] It should be noted that the number of the second capacitor structures 1132 can be multiple, and the multiple second capacitor structures 1132 are all electrically connected to the second power supply signal line 112b3. In this way, the shielding effect can be improved, and the performance and reliability of the liquid crystal on silicon chip 11 can be further improved.

[0063] In one of the embodiments, the peripheral circuit 112b further includes a second ground signal line 112b4 electrically connected to the driving circuit 112a. The second capacitor structure 1132 includes a third plate 11321 and a fourth plate 11322. The third plate 11321 is electrically connected to the second power supply signal line 112b3, and the fourth plate 11322 is electrically connected to the second ground signal line 112b4. In this way, by means of the second ground signal line 112b4, the fourth plate 11322 can maintain a stable potential, which is beneficial to reducing the routing density in the peripheral area 111b and at the same time reducing the manufacturing difficulty of the liquid crystal on silicon chip 11.

[0064] In one of the embodiments, the second power supply signal line 112b3 includes a third metal trace 112b31 and a third contact pad 112b32. One end of the third metal trace 112b31 is electrically connected to the driving circuit 112a, and the other end of the third metal trace 112b31 is electrically connected to the third contact pad 112b32. The second ground signal line 112b4 includes a fourth metal trace 112b41 and a fourth contact pad 112b42. One end of the fourth metal trace 112b41 is electrically connected to the driving circuit 112a, and the other end of the fourth metal trace 112b41 is electrically connected to the fourth contact pad 112b42. Among them, the third plate 11321 is disposed between the third contact pad 112b32 and the driving circuit 112a and is connected to the third metal trace 112b31; the fourth plate 11322 is disposed between the fourth contact pad 112b42 and the driving circuit 112a and is connected to the fourth metal trace 112b41.

[0065] It can be understood that both the third contact pad 112b32 and the fourth contact pad 112b42 are used to connect to the connection pads on the circuit board 13, thereby achieving signal access. By disposing the third electrode plate 11321 between the third contact pad 112b32 and the driving circuit 112a and connecting it to the third metal trace 112b31, and disposing the fourth electrode plate 11322 between the fourth contact pad 112b42 and the driving circuit 112a and connecting it to the fourth metal trace 112b41, the circuit path length between the second capacitor structure 1132 and the driving circuit 112a can be maximally reduced, thereby maximally reducing the influence of the interference signal generated between adjacent lines on the driving circuit 112a.

[0066] In one embodiment, referring to Figure 1 and Figure 3 as shown, the liquid crystal on silicon chip 11 further includes an antioxidant layer 114. The antioxidant layer 114 is disposed on the side of the driving circuit 112a away from the semiconductor substrate 111 and on the side of the peripheral circuit 112b away from the semiconductor substrate 111. The shielding capacitor 113 is disposed on the side of the antioxidant layer 114 away from the semiconductor substrate 111. Through holes are provided in the antioxidant layer 114, and a conductive structure 115 is provided in the through holes. The shielding capacitor 113 is electrically connected to the peripheral circuit 112b by means of the conductive structure 115. Exemplarily, the antioxidant layer 114 may be a PI (polyimide) film layer.

[0067] Specifically, the first electrode plate 11311 of the first capacitor structure 1131 is electrically connected to the first power signal line 112b1 by means of a conductive structure 115, and the second electrode plate 11312 of the first capacitor structure 1131 is electrically connected to the first ground signal line 112b2 by means of a conductive structure 115.

[0068] It can be understood that the first electrode plate 11311 can be electrically connected to the first power signal line 112b1 by means of multiple conductive structures 115, and the second electrode plate 11312 can be electrically connected to the first ground signal line 112b2 by means of multiple conductive structures 115.

[0069] It should be noted that in the process of manufacturing the shielding capacitor 113, the following method can be adopted:

[0070] First, drill holes in the antioxidant layer 114 to expose the metal traces, and then connect the electrode plates of the shielding capacitor 113 to the metal traces. It can be understood that the electrode plates can be directly welded to the metal traces, or a metal material can be provided in the through holes to connect the electrode plates to the metal traces. It can be understood that since the metal traces (aluminum material) are exposed to the air and are prone to oxidation reactions, therefore, before connecting the electrode plates to the metal traces, it is necessary to remove the oxide layer on the surface of the metal traces (pickling or mechanical removal).

[0071] It should be noted that the orthographic projection area of the first electrode plate 11311 (or the second electrode plate 11312) on the semiconductor substrate 111 is the first area, and the orthographic projection area of the first contact pad 112b12 (or the second contact pad 112b22) on the semiconductor substrate 111 is the second area. The first area may be greater than or less than the second area, or the first area may be equal to the second area. That is, the embodiments of the present application do not limit the sizes of the electrode plates and the contact pads of the shielding capacitor 113.

[0072] In a second aspect, as shown in Figure 4 and Figure 5 an embodiment of the present application provides a liquid crystal on silicon (LCOS) chip module 10, which includes a substrate 12, a circuit board 13, the liquid crystal on silicon chip 11 in the first aspect embodiment, and a liquid crystal module 14. The material of the substrate 12 may be aluminum. The circuit board 13 is disposed on the substrate 12, and the circuit board 13 may be a flexible printed circuit (FPC). The liquid crystal on silicon chip 11 is disposed on the circuit board 13 and is electrically connected to the circuit board 13. The liquid crystal module 14 is disposed on the liquid crystal on silicon chip 11 and is electrically connected to the driving circuit 112a of the liquid crystal on silicon chip 11.

[0073] In the liquid crystal on silicon chip module 10 provided by the embodiments of the present application, by providing the shielding capacitor 113 and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, on the one hand, interference signals flowing through the peripheral circuit 112b can be shielded, reducing the possibility of the interference signals being conducted to the driving circuit 112a, thereby reducing the influence of the interference signals on the driving circuit 112a. On the other hand, by providing the shielding capacitor 113 in the peripheral region 111b and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, the routing path length between the shielding capacitor 113 and the driving circuit 112a can be minimized, that is, the circuit path between the shielding capacitor 113 and the driving circuit 112a is short, thereby minimizing the influence of the interference signals generated between adjacent lines on the driving circuit 112a. In summary, the present application can improve the performance and reliability of the liquid crystal on silicon chip module 10.

[0074] It should be noted that a first connection pad group 131 and a second connection pad group 132 may be provided on the circuit board 13. The first connection is used for electrically connecting to the liquid crystal on silicon chip 11, and the second connection pad group 132 is used for external electrical connection.

[0075] In a third aspect, an embodiment of the present application provides a display device, which may be a projection device such as a projector or a projection system having a liquid crystal on silicon chip module. As shown in Figure 6 is a schematic diagram of the functional modules of the display device 1.

[0076] Specifically, the display device 1 includes the liquid crystal on silicon chip component 10 in the second aspect. It can be understood that the display device 1 further includes a light source 20, a projection lens 30, a housing 40, etc. The light source 20 and the liquid crystal on silicon chip component 10 are disposed in the housing 40, and the projection lens 30 is disposed on the housing 40. Among them, the light emitted by the light source 20 irradiates the liquid crystal on silicon chip component 10, and the projection lens 30 projects the optical image generated by the liquid crystal on silicon chip component 10 onto a screen or a wall.

[0077] For the display device 1 provided by the embodiment of the present application, by providing a shielding capacitor 113 and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, on the one hand, it is possible to shield the interference signal flowing through the peripheral circuit 112b and reduce the possibility of the interference signal being conducted to the driving circuit 112a, thereby reducing the influence of the interference signal on the driving circuit 112a; on the other hand, by providing the shielding capacitor 113 in the peripheral area 111b and electrically connecting the shielding capacitor 113 to the peripheral circuit 112b, the wiring path length between the shielding capacitor 113 and the driving circuit 112a can be maximally reduced, that is: the circuit path between the shielding capacitor 113 and the driving circuit 112a is short, thereby maximally reducing the influence of the interference signal generated between adjacent lines on the driving circuit 112a; in summary, the present application can improve the performance and reliability of the display device 1.

[0078] In the description of this specification, the descriptions referring to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0079] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0080] The above embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A liquid crystal on silicon chip, characterized in that: include: A semiconductor substrate having a central region and a peripheral region adjacent to each other; A driving circuit is disposed in the central area of ​​the semiconductor substrate; A peripheral circuit is disposed in the peripheral area of ​​the semiconductor substrate and is electrically connected to the driving circuit; as well as A shielding capacitor is disposed in the peripheral area and electrically connected to the peripheral circuit, and the shielding capacitor is used to shield interference signals flowing through the peripheral circuit.

2. The liquid crystal on silicon chip according to claim 1, characterized in that: The peripheral circuit includes a first power signal line electrically connected to the driving circuit; The shielding capacitor includes a first capacitor structure, one plate of the first capacitor structure is electrically connected to the first power signal line, and the first capacitor structure is used to shield interference signals flowing through the first power signal line.

3. The liquid crystal on silicon chip according to claim 2, characterized in that: The peripheral circuit further comprises a first ground signal line electrically connected to the driving circuit; The first capacitor structure includes a first plate and a second plate, the first plate is electrically connected to the first power signal line, and the second plate is electrically connected to the first ground signal line.

4. The liquid crystal on silicon chip according to claim 3, characterized in that: The first power signal line includes a first metal wiring and a first contact pad, one end of the first metal wiring is electrically connected to the driving circuit, and the other end of the first metal wiring is electrically connected to the first contact pad; The first ground signal line includes a second metal line and a second contact pad, one end of the second metal line is electrically connected to the driving circuit, and the other end of the second metal line is electrically connected to the second contact pad; The first electrode plate is disposed between the first contact pad and the driving circuit and connected to the first metal wiring; the second electrode plate is disposed between the second contact pad and the driving circuit and connected to the second metal wiring.

5. The liquid crystal on silicon chip according to claim 2, characterized in that: The peripheral circuit further comprises a second power signal line electrically connected to the driving circuit, and a voltage of the second power signal line is different from a voltage of the first power signal line; The shielding capacitor includes a second capacitor structure, one plate of the second capacitor structure is electrically connected to the second power signal line, and the second capacitor structure is used to shield interference signals flowing through the second power signal line.

6. The liquid crystal on silicon chip according to claim 5, characterized in that: The peripheral circuit further includes a second ground signal line electrically connected to the drive circuit; The second capacitor structure includes a third plate and a fourth plate, the third plate is electrically connected to the second power signal line, and the fourth plate is electrically connected to the second ground signal line.

7. The liquid crystal on silicon chip according to claim 6, characterized in that: The second power signal line includes a third metal wiring and a third contact pad, one end of the third metal wiring is electrically connected to the driving circuit, and the other end of the third metal wiring is electrically connected to the third contact pad; The second ground signal line includes a fourth metal line and a fourth contact pad, one end of the fourth metal line is electrically connected to the driving circuit, and the other end of the fourth metal line is electrically connected to the fourth contact pad; The third electrode plate is disposed between the third contact pad and the driving circuit, and is connected to the third metal wiring; the fourth electrode plate is disposed between the fourth contact pad and the driving circuit, and is connected to the fourth metal wiring.

8. The liquid crystal on silicon chip according to any one of claims 1 to 7, characterized in that: The silicon-based liquid crystal chip further includes an anti-oxidation layer, which is arranged on a side of the driving circuit away from the semiconductor substrate and a side of the peripheral circuit away from the semiconductor substrate; the shielding capacitor is arranged on a side of the anti-oxidation layer away from the semiconductor substrate; The anti-oxidation layer is provided with a via hole, a conductive structure is provided in the via hole, and the shielding capacitor is electrically connected to the peripheral circuit by means of the conductive structure.

9. A liquid crystal on silicon chip assembly, characterized in that: include: substrate; A circuit board is arranged on the substrate; The liquid crystal on silicon chip according to any one of claims 1 to 8, arranged on the circuit board and electrically connected to the circuit board; The liquid crystal component is arranged on the silicon-based liquid crystal chip and is electrically connected to the driving circuit of the silicon-based liquid crystal chip.

10. A display device, characterized in that: It comprises the liquid crystal on silicon chip assembly as claimed in claim 9.

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