Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the array substrate comprises pixel areas arranged in an array and a non-pixel area located between two adjacent rows of pixel areas, the array substrate comprises a substrate, a scanning line, a first insulating layer and a transparent electrode, the scanning line is located in the non-pixel area, the scanning line extends in the row direction, and the scanning line comprises a first sub-segment; the first insulating layer is arranged on the side, away from the substrate, of the scanning line; the transparent electrode is arranged on the side, away from the scanning line, of the first insulating layer and extends in the row direction, and an avoiding opening is formed in the edge of the side, extending in the row direction, of the transparent electrode; in a plane view of the array substrate, the scanning lines and the transparent electrodes are partially overlapped, and in the column direction, the avoiding openings completely expose the first sub-segments of the scanning lines. The yield of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] In the array substrate of a conventional liquid crystal display (LCD), since crosstalk may occur between data lines and pixels, a transparent electrode layer is usually provided in the array substrate as a shielding layer to reduce the influence of data lines on pixels. In the plan view of the conventional array substrate, a part of the transparent electrode overlaps with the scanning line.

[0003] However, during the manufacturing process of the array substrate, an abnormal problem of short circuit between the scanning line and other signal lines may occur. At this time, it is necessary to repair by cutting the scanning line with a laser. However, the molten material will be formed at the part of the scanning line cut by the laser, and the solidified molten material will be short-circuited with the overlapping part of the transparent electrode, affecting the yield of the display panel.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0005] The purpose of this application is to provide an array substrate and a display panel to improve the yield of the display panel.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, this application provides an array substrate, including a pixel region arranged in an array and a non-pixel region located between two adjacent rows of the pixel regions. The array substrate includes:

[0008] A substrate;

[0009] A scanning line located in the non-pixel region, extending along the row direction, and the scanning line includes a first sub-segment;

[0010] A first insulating layer provided on the side of the scanning line away from the substrate; and

[0011] A transparent electrode provided on the side of the first insulating layer away from the scanning line, extending along the row direction, and an avoidance opening is provided at one side edge of the transparent electrode extending along the row direction;

[0012] In the plan view of the array substrate, the scanning line and the transparent electrode partially overlap, and in the column direction, the avoidance opening completely exposes the first sub-segment of the scanning line.

[0013] In an embodiment of this application, the transparent electrode includes:

[0014] A first sub - part, located in the pixel region and extending along the row direction;

[0015] A plurality of second sub - parts, located in the non - pixel region. The plurality of second sub - parts are connected to the same side of the first sub - part extending along the row direction. The plurality of second sub - parts are arranged at intervals, and a relief opening is formed between two adjacent second sub - parts;

[0016] In a plan view of the array substrate, the second sub - part overlaps with the scanning line.

[0017] In an embodiment of the present application, the width of the relief opening in the column direction is greater than or equal to 3 microns.

[0018] In an embodiment of the present application, the width of the relief opening in the row direction is greater than or equal to 4 microns.

[0019] In an embodiment of the present application, in a plan view of the array substrate, the shape of the positive projection of the inner wall of the relief opening on the substrate is one of a broken line and an arc.

[0020] In an embodiment of the present application, the array substrate further includes a connection electrode. The connection electrode and the transparent electrode are located in the same film layer. The connection electrode extends along the column direction and is located between two adjacent transparent electrodes. One end of the connection electrode is connected to the first sub - part of an adjacent transparent electrode, and the other end of the connection electrode is connected to the second sub - part of an adjacent transparent electrode;

[0021] In a plan view of the array substrate, the positive projection of the connection electrode on the substrate is located outside the positive projection of the relief opening on the substrate.

[0022] In an embodiment of the present application, the array substrate further includes:

[0023] Data lines, disposed between the first insulating layer and the transparent electrode. The data lines extend along the column direction, and a plurality of data lines intersect with a plurality of scanning lines to form a plurality of pixel regions;

[0024] A second insulating layer, disposed between the data lines and the transparent electrode;

[0025] A color resist layer, disposed between the second insulating layer and the transparent electrode;

[0026] A third insulating layer, disposed on a side of the transparent electrode away from the color resist layer; and

[0027] Pixel electrodes, disposed on a side of the third insulating layer away from the transparent electrode and located in the pixel regions;

[0028] In a plan view of the array substrate, the pixel electrode overlaps with the first sub - portion, a positive projection of the second sub - portion on the substrate is located outside a positive projection of the pixel electrode on the substrate, and a positive projection of the avoidance opening on the substrate is located outside a positive projection of the pixel electrode on the substrate.

[0029] In an embodiment of the present application, the color resist layer includes a plurality of color resist blocks arranged along the row direction, edges of two adjacent color resist blocks overlap to form a color resist stack, the color resist stack includes a first sub - stack, the first sub - stack is located in the non - pixel area, and the first sub - stack extends along the column direction;

[0030] The connection electrode is located in the non - pixel area, a hollow portion is formed between two adjacent connection electrodes, and the hollow portion communicates with the avoidance opening;

[0031] In a plan view of the array substrate, one connection electrode overlaps with one data line, and a positive projection of a part of the first sub - stack on the substrate is located within a positive projection of the hollow portion on the substrate.

[0032] In an embodiment of the present application, in a plan view of the array substrate, a width of the connection electrode is less than a width of the data line.

[0033] In an embodiment of the present application, the color resist layer includes a plurality of color resist blocks arranged along the row direction, edges of two adjacent color resist blocks overlap to form a color resist stack, the color resist stack includes a first sub - stack, the first sub - stack is located in the non - pixel area, and the first sub - stack extends along the column direction;

[0034] In a plan view of the array substrate, the data line overlaps with the color resist stack, and a positive projection of the connection electrode on the substrate is located outside a positive projection of the color resist stack on the substrate.

[0035] In a second aspect, the present application provides a display panel, including an array substrate, the array substrate includes a pixel area arranged in an array and a non - pixel area located between two adjacent rows of the pixel areas, the array substrate includes a substrate, a scanning line, a first insulating layer, and a transparent electrode, the scanning line is located in the non - pixel area, the scanning line extends along the row direction, the scanning line includes a first sub - segment; the first insulating layer is disposed on a side of the scanning line away from the substrate; the transparent electrode is disposed on a side of the first insulating layer away from the scanning line, the transparent electrode extends along the row direction, and an avoidance opening is provided at a side edge of the transparent electrode extending along the row direction; in a plan view of the array substrate, the scanning line partially overlaps with the transparent electrode, and in the column direction, the avoidance opening completely exposes the first sub - segment of the scanning line.

[0036] In the present application, the scan line includes a first sub-segment. During the manufacturing process of the array substrate, when an abnormal problem of short circuit occurs between the scan line and other signal lines, the first sub-segment can be cut off by laser ablation to repair the array substrate. Since an avoidance opening that completely exposes the first sub-segment is provided on one side edge in the extending direction of the transparent electrode, when the first sub-segment is cut off by laser ablation, the solidified melt will not be short-circuited with the transparent electrode, thereby improving the yield of the display panel. Description of the Drawings

[0037] Figure 1 is a plan view of an embodiment of the array substrate of the present application;

[0038] Figure 2 is a plan view of an embodiment of the scan line and the transparent electrode of the present application;

[0039] Figure 3 is Figure 2 a cross-sectional view taken along the section line A-A' in

[0040] Figure 4 is a plan view of an embodiment of the scan line of the present application;

[0041] Figure 5 is a plan view of an embodiment of the data line of the present application;

[0042] Figure 6 is a plan view of an embodiment of the transparent electrode and the connection electrode of the present application;

[0043] Figure 7 is a plan view of an embodiment of the pixel electrode of the present application;

[0044] Figure 8 is a plan view of another embodiment of the transparent electrode of the present application;

[0045] Figure 9 is a schematic diagram of the data line, the first sub-stack, and the connection electrode of the present application. Detailed Description of the Invention

[0046] The meanings of the terms used in this specification and the claims correspond to the meanings commonly understood by those of ordinary skill in the art to which the present application pertains. The terms used in this specification and the claims are only for the purpose of facilitating the description and understanding of the present application, and are not intended to limit the present application to the narrow interpretation of the specific terms used in this specification and the claims.

[0047] The present application provides a display panel, which can be used in mobile phones, tablet computers, e - readers, electronic display screens, laptop computers, mobile phones, augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, vehicle navigation devices, etc.

[0048] The display panel can be a Liquid Crystal Display (LCD).

[0049] An embodiment of the present application will be described by taking a liquid crystal display panel as an example. The display panel includes an array substrate 100.

[0050] Please refer to Figure 1 , the present application provides an array substrate 100, which includes a pixel area PA arranged in an array and a non - pixel area NA located between adjacent rows of the pixel area PA. The array substrate 100 includes a substrate 90, scan lines 11, a first insulating layer 50, and a transparent electrode 20.

[0051] Please refer to Figure 2 , the scan lines 11 are located in the non - pixel area NA and extend along the row direction X. The scan line 11 includes a first sub - segment 111. The first insulating layer 50 is disposed on a side of the scan line 11 away from the substrate 90. The transparent electrode 20 is disposed on a side of the first insulating layer 50 away from the scan line 11 and extends along the row direction X. An avoidance opening 21 is provided at a side edge of the transparent electrode 20 extending along the row direction X.

[0052] In a plan view of the array substrate 100, the scan line 11 and the transparent electrode 20 partially overlap. In the column direction Y, the avoidance opening 21 completely exposes the first sub - segment 111 of the scan line 11.

[0053] Please refer to Figure 3 , in this embodiment, the scan line 11 includes a first sub - segment 111. During the manufacturing process of the array substrate 100, when an abnormal problem of short - circuit between the scan line 11 and other signal lines occurs, the first sub - segment 111 can be cut off by laser ablation to repair the array substrate 100. Since the avoidance opening 21 that completely exposes the first sub - segment 111 is provided at a side edge of the transparent electrode 20 in the extending direction, when the first sub - segment 111 is cut off by laser ablation, the solidified melt will not be short - circuited with the transparent electrode 20, thereby improving the yield of the display panel.

[0054] Optionally, the substrate 90 is a rigid substrate 90, and the material of the rigid substrate 90 includes glass.

[0055] Optionally, the substrate 90 is a flexible substrate 90, and the material of the flexible substrate 90 includes polyimide (PI).

[0056] Optionally, refer to Figure 4 , the array substrate 100 further includes a first metal layer 10. The first metal layer 10 is disposed on the substrate 90. The first metal layer 10 includes scan lines 11 and gates 12. Among them, the scan lines 11 are electrically connected to the gates 12.

[0057] Optionally, a first insulating layer 50 is disposed on a side of the first metal layer 10 away from the substrate 90. The first insulating layer 50 is configured as a gate insulating layer.

[0058] Optionally, the material of the first insulating layer 50 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0059] Optionally, the array substrate 100 further includes a semiconductor layer. The semiconductor layer is disposed on a side of the first insulating layer 50 away from the substrate 90 and is disposed corresponding to the gates 12.

[0060] Optionally, refer to Figure 5 , the array substrate 100 further includes a second metal layer 30. The second metal layer 30 includes data lines 31, source electrodes 32, and drain electrodes 33. Among them, the data lines 31 are disposed on the first insulating layer 50, the source electrodes 32 are electrically connected to the data lines 31, the source electrodes 32 are electrically connected to the semiconductor layer, and the drain electrodes 33 are electrically connected to the semiconductor layer. The gates 12, the semiconductor layer, the source electrodes 32, and the drain electrodes 33 form thin film transistors of sub-pixels.

[0061] Optionally, the data lines 31 extend along the column direction Y, and a plurality of data lines 31 intersect with a plurality of scan lines 11 to form a plurality of pixel regions PA. Among them, the plurality of pixel regions PA are arranged in an array. A non-pixel region NA is formed between adjacent two rows of pixel regions PA.

[0062] Optionally, the array substrate 100 further includes a second insulating layer 60. The second insulating layer 60 is disposed on a side of the second metal layer 30 away from the substrate 90. The second insulating layer 60 is configured as a passivation layer.

[0063] Optionally, the material of the second insulating layer 60 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0064] Optionally, the array substrate 100 further includes a color resist layer 70. The color resist layer 70 is disposed on the second insulating layer 60. The color resist layer 70 includes a plurality of color resist blocks 71, and the plurality of color resist blocks 71 are arranged along the row direction X.

[0065] Optionally, the color resist blocks 71 include red color resist blocks 71, green color resist blocks 71, and blue color resist blocks 71.

[0066] Optionally, refer to Figure 6 , a transparent electrode 20 is disposed on a side of the color resist layer 70 away from the substrate 90.

[0067] Optionally, the material of the transparent electrode 20 includes indium tin oxide (ITO).

[0068] Optionally, the array substrate 100 further includes a third insulating layer 80 disposed on a side of the transparent electrode 20 away from the substrate 90.

[0069] Optionally, the material of the third insulating layer 80 includes an organic insulating material. The material of the third insulating layer 80 may be a photoresist. Compared with an inorganic insulating material, the organic insulating material can improve the flatness above its film layer, thereby improving the device performance of the array substrate 100.

[0070] Optionally, refer to Figure 7 , the array substrate 100 further includes a pixel electrode 40 disposed on a side of the third insulating layer 80 away from the substrate 90. In the present application, the transparent electrode 20 serves as a shielding layer to shield the crosstalk of the first metal layer 10 and the second metal layer 30 to the pixel electrode 40, thereby improving the display effect of the display panel.

[0071] Optionally, the pixel electrode 40 is located within the pixel region PA. The material of the pixel electrode 40 includes indium tin oxide.

[0072] Optionally, in a plan view of the array substrate 100, the orthographic projection of the avoidance opening 21 on the substrate 90 is located outside the orthographic projection of the pixel electrode 40 on the substrate 90. In this embodiment, after the first sub-segment 111 is cut off by laser ablation, it is possible to prevent the melt formed by the first sub-segment 111 from short-circuiting with the pixel electrode 40 after solidification, thereby improving the yield of the display panel.

[0073] Optionally, refer to Figure 6 , the transparent electrode 20 includes a first sub-part 22 and a plurality of second sub-parts 23. The first sub-part 22 is located within the pixel region PA and extends along the row direction X. The second sub-parts 23 are located within the non-pixel region NA, and the plurality of second sub-parts 23 are connected to the same side of the first sub-part 22 extending along the row direction X. The plurality of second sub-parts 23 are spaced apart, and an avoidance opening 21 is formed between adjacent two second sub-parts 23.

[0074] Optionally, refer to Figure 2 , in a plan view of the array substrate 100, the second sub-part 23 overlaps with the scan line 11.

[0075] In this embodiment, the second sub-part 23 located within the non-pixel region NA overlaps with the scan line 11 to shield the electric field generated by the scan line 11, so as to prevent the electric field generated by the scan line 11 from changing the phase of the liquid crystal.

[0076] Optionally, refer toFigure 1 In the plan view of the array substrate 100, the pixel electrode 40 overlaps with the first sub - part 22. The orthographic projection of the second sub - part 23 on the substrate 90 is located outside the orthographic projection of the pixel electrode 40 on the substrate 90. The orthographic projection of the avoidance opening 21 on the substrate 90 is located outside the orthographic projection of the pixel electrode 40 on the substrate 90.

[0077] In this embodiment, when the first sub - segment 111 is cut off by laser ablation, the solidified melt will not be short - circuited with the pixel electrode 40, thereby improving the yield of the display panel.

[0078] Optionally, please refer to Figure 6 In the plan view of the array substrate 100, the shape of the orthographic projection of the inner wall of the avoidance opening 21 on the substrate 90 is a broken line.

[0079] In this embodiment, the shape of the orthographic projection of the avoidance opening 21 on the substrate 90 is a semi - rectangle. Therefore, the shape of the orthographic projection of the inner wall of the avoidance opening 21 on the substrate 90 is a broken line.

[0080] Optionally, please refer to Figure 8 In the plan view of the array substrate 100, the shape of the orthographic projection of the inner wall of the avoidance opening 21 on the substrate 90 is an arc.

[0081] In this embodiment, the shape of the orthographic projection of the avoidance opening 21 on the substrate 90 is a semi - circle or an ellipse. Therefore, the shape of the orthographic projection of the inner wall of the avoidance opening 21 on the substrate 90 is an arc.

[0082] Optionally, please refer to Figure 6 The width L2 of the avoidance opening 21 in the column direction Y is greater than or equal to 3 microns. In this embodiment, the width L2 of the avoidance opening 21 in the column direction Y refers to the maximum width of the avoidance opening 21 in the column direction Y.

[0083] In this embodiment, the value of the width L2 of the avoidance opening 21 in the column direction Y is one of the values 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5 microns, 5.5 microns, 6 microns, 6.5 microns, 7 microns, 7.5 microns, 8 microns, 8.5 microns, 9 microns, 9.5 microns, 10 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, 50 microns. Among them, the value of the width L2 of the avoidance opening 21 in the column direction Y mainly depends on the specific size and application scenario of the array substrate 100. When applied to small - sized mobile phone devices, the value of the width L2 of the avoidance opening 21 in the column direction Y is relatively small. When applied to large - sized TVs and laptop computers, the value of the width L2 of the avoidance opening 21 in the column direction Y is relatively large.

[0084] Optionally, the width L1 of the avoidance opening 21 in the row direction X is greater than or equal to 4 microns. In this embodiment, the width L1 of the avoidance opening 21 in the row direction X refers to the maximum width of the avoidance opening 21 in the row direction X.

[0085] In this embodiment, the value of the width L1 of the avoidance opening 21 in the row direction X is one of the values of 4 microns, 4.5 microns, 5 microns, 5.5 microns, 6 microns, 6.5 microns, 7 microns, 7.5 microns, 8 microns, 8.5 microns, 9 microns, 9.5 microns, 10 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, 50 microns. Among them, the value of the width L1 of the avoidance opening 21 in the row direction X mainly depends on the specific size and application scenario of the array substrate 100. When applied to small-sized mobile phone devices, the value of the width L1 of the avoidance opening 21 in the row direction X is small. When applied to large-sized TVs and laptop computers, the value of the width L1 of the avoidance opening 21 in the row direction X is large.

[0086] Optionally, please refer to Figure 6 , the array substrate 100 further includes a connection electrode 24. The connection electrode 24 and the transparent electrode 20 are located in the same film layer. The connection electrode 24 extends along the column direction Y and is located between two adjacent transparent electrodes 20. One end of the connection electrode 24 is connected to the first sub-part 22 of an adjacent transparent electrode 20, and the other end of the connection electrode 24 is connected to the second sub-part 23 of another adjacent transparent electrode 20.

[0087] Optionally, in the plan view of the array substrate 100, the orthographic projection of the connection electrode 24 on the substrate 90 is located outside the orthographic projection of the avoidance opening 21 on the substrate 90.

[0088] In this embodiment, the connection electrode 24 is used to connect two adjacent transparent electrodes 20 to reduce the impedance of the transparent electrode 20.

[0089] Optionally, the connection electrode 24 is located in the non-pixel area NA. In the plan view of the array substrate 100, one connection electrode 24 overlaps with one data line 31. It is used to shield the electric field generated by the data line 31 to prevent the electric field generated by the data line 31 from changing the phase of the liquid crystal.

[0090] Optionally, the edges of two adjacent color resist blocks 71 overlap to form a color resist stack. In the plan view of the array substrate 100, the color resist stack overlaps with the data line 31. Among them, the color resist stack includes a first sub-stack 72, and the first sub-stack 72 is located in the non-pixel area NA. The first sub-stack 72 extends along the column direction Y and overlaps with the part of the data line 31 located in the non-pixel area NA.

[0091] In this embodiment, the connection of the color stack is unstable. The color resist stack may peel off during the manufacturing process of the array substrate 100. After the color resist stack peels off, on the one hand, the edge of part of the color resist block 71 is lifted up, causing the connection electrode 24 located above the color resist block 71 to be lifted up and short-circuited with the pixel electrode 40. On the other hand, after the color stack peels off, there is only a thin second insulating layer 60 between the connection electrode 24 and the data line 31 below. When there are foreign matter or dust particles, the connection electrode 24 is easily short-circuited with the data line 31 below.

[0092] Optional, see Figure 9 A hollow portion 25 is formed between two adjacent connection electrodes 24, and the hollow portion 25 is connected to the avoidance opening 21. In the plan view of the array substrate 100, the orthographic projection of a portion of the first sub-stack 72 on the substrate 90 is located within the range of the orthographic projection of the hollow portion 25 on the substrate 90, and the orthographic projection of another portion of the first sub-stack 72 on the substrate 90 overlaps with the orthographic projection of the connection electrode 24 on the substrate 90.

[0093] In this embodiment, the first sub-stack 72 may be peeled off during the manufacturing process of the array substrate 100. In order to reduce the impact of the first sub-stack 72 peeling off on the array substrate 100, this embodiment reduces the number of first connection electrodes 24, forms a hollow portion 25 between two adjacent first electrodes, and makes the orthographic projection of a part of the first sub-stack 72 on the substrate 90 located within the range of the hollow portion 25. When the first sub-stack 72 of this part is peeled off, since there is no connection electrode 24 above the first sub-stack 72 of this part, the yield of the display panel can be improved.

[0094] Optionally, in a plan view of the array substrate 100 , a width L3 of the connecting electrode 24 in the row direction X is smaller than a width L4 of the data line 31 in the row direction X.

[0095] Since the connection electrode 24 plays a role in reducing the impedance of the transparent electrode 20, the orthographic projection of another part of the connection electrode 24 on the substrate 90 still overlaps with the orthographic projection of part of the first sub-stack 72 on the substrate 90. In this embodiment, by reducing the width L3 of the connection electrode 24 in the row direction X, the width L3 of the connection electrode 24 in the row direction X is made smaller than the width L4 of the data line 31 in the row direction X. After the first sub-stack 72 is peeled off, the risk of short circuit between the connection electrode 24 and the data line 31 is reduced, thereby improving the yield of the display panel.

[0096] Optionally, the orthographic projection of the connecting electrode 24 on the substrate 90 is located outside the orthographic projection of the color-resist stack on the substrate 90 .

[0097] In this embodiment, some of the connection electrodes 24 may not overlap with the data lines 31. When the first sub-stack 72 is peeled off, the connection electrodes 24 that do not overlap with the data lines 31 will not be short-circuited with the data lines 31 or the pixel electrodes 40, improving the yield of the display panel.

[0098] The specific embodiments of the present application have been described in detail above. The above-described embodiments disclosed in the present application are only the preferred embodiments of the present application. For those of ordinary skill in the art, many variations and improvements can be made without departing from the concept of the present application. These variations and improvements all fall within the protection scope defined by the claims of the present application.

Claims

1. An array substrate, comprising pixel areas arranged in an array, and a non-pixel area located between two adjacent rows of the pixel areas, characterized in that: include: substrate; A scan line, located in the non-pixel area, the scan line extends along a row direction, and the scan line includes a first sub-segment; A first insulating layer, disposed on a side of the scanning line away from the substrate; as well as A transparent electrode is provided on a side of the first insulating layer away from the scanning line, the transparent electrode extends along the row direction, and a side edge of the transparent electrode extending along the row direction is provided with a avoidance opening; In a plan view of the array substrate, the scan line partially overlaps with the transparent electrode, and in a column direction, the avoidance opening completely exposes a first subsegment of the scan line.

2. The array substrate according to claim 1, characterized in that: The transparent electrode comprises: A first sub-portion, located in the pixel area and extending along the row direction; A plurality of second sub-sections, located in the non-pixel area, the plurality of second sub-sections are connected to the same side of the first sub-section extending along the row direction, the plurality of second sub-sections are arranged at intervals, and the avoidance opening is formed between two adjacent second sub-sections; In a plan view of the array substrate, the second sub-portion overlaps the scan line.

3. The array substrate according to claim 2, characterized in that: The width of the avoidance opening in the column direction is greater than or equal to 3 micrometers.

4. The array substrate according to claim 2, characterized in that: The width of the avoidance opening in the row direction is greater than or equal to 4 micrometers.

5. The array substrate according to claim 2, characterized in that: In the plan view of the array substrate, the shape of the orthographic projection of the inner wall of the avoidance opening on the substrate is one of a broken line and an arc line.

6. The array substrate according to claim 2, characterized in that: The array substrate further comprises a connecting electrode, wherein the connecting electrode and the transparent electrode are located in the same film layer, the connecting electrode extends along the column direction and is located between two adjacent transparent electrodes, one end of the connecting electrode is connected to a first sub-portion of an adjacent transparent electrode, and the other end of the connecting electrode is connected to a second sub-portion of another adjacent transparent electrode; In a plan view of the array substrate, an orthographic projection of the connection electrode on the substrate is located outside an orthographic projection of the avoidance opening on the substrate.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes: A data line is provided between the first insulating layer and the transparent electrode, the data line extends along the column direction, and a plurality of the data lines intersect with a plurality of the scanning lines to form a plurality of the pixel areas; A second insulating layer is provided between the data line and the transparent electrode; A color resist layer, disposed between the second insulating layer and the transparent electrode; A third insulating layer is provided on a side of the transparent electrode away from the color resist layer; and A pixel electrode, disposed on a side of the third insulating layer away from the transparent electrode and located in the pixel area; In the plan view of the array substrate, the pixel electrode overlaps with the first sub-portion, the orthographic projection of the second sub-portion on the substrate is located outside the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the avoidance on the substrate is located outside the orthographic projection of the pixel electrode on the substrate.

8. The array substrate according to claim 7, characterized in that: The color resist layer includes a plurality of color resist blocks arranged along the row direction, the edges of two adjacent color resist blocks overlap to form a color resist stack, the color resist stack includes a first sub-stack, the first sub-stack is located in the non-pixel area, and the first sub-stack extends along the column direction; The connecting electrode is located in the non-pixel area, a hollow portion is formed between two adjacent connecting electrodes, and the hollow portion is connected to the avoidance opening; In a plan view of the array substrate, one of the connecting electrodes overlaps with one of the data lines, and an orthographic projection of a portion of the first sub-layer on the substrate is located within the range of an orthographic projection of the hollow portion on the substrate.

9. The array substrate according to claim 7, characterized in that: In a plan view of the array substrate, a width of the connection electrode in the row direction is smaller than a width of the data line in the row direction.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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