Module for bonding fan-out wafer level packaging unit on electronic component through wire bonding

Abstract

The utility model discloses a module for bonding a fan-out type wafer level packaging unit on an electronic component through wire bonding. The module comprises a carrier plate, a first bare chip, a first dielectric layer, a plurality of first conducting circuits, a second dielectric layer, a plurality of second conducting circuits, a second bare chip, an electronic component, at least one first bonding wire, at least two second bonding wires and at least one third bonding wire, wherein each second conducting circuit is formed by grinding metal paste filled in each second groove of the second dielectric layer, and each second conducting circuit forms a welding pad in each second groove; wherein the first bare crystal can be electrically connected with the outside through the welding pads around the chip area on the second surface of the first bare crystal, so that the problems that the fan-out packaging technology in the existing module is easy to generate higher manufacturing cost and is not beneficial to environmental protection when manufacturing the conducting circuits are effectively solved.

Description

Technical Field

[0001] The utility model relates to a module, in particular to a module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component. Background Art

[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced packaging FOWLP, the redistribution layer (RDL) is the most critical. Because each conductive connection line in the RDL can cause the XY-plane electrical extension and interconnection of multiple pads on the bare die, so that a relatively dispersed plurality of solder pads can be formed around the bare die, thereby effectively improving the design space and reliability of each conductive connection line. However, how to make each conductive connection line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating the XY-plane electrical extension and interconnection effect is the most critical for the production of each conductive connection line in the RDL.

[0004] However, the forming method of each conductive connection line in the RDL technology applied in the existing FOWLP packaging technology is to use electroless plating forming technology or electroplating forming technology for production. In this way, in addition to the relatively high material cost and production cost, the existing technology process also does not meet or is not conducive to environmental protection requirements.

[0005] In addition, when the FOWLP packaging unit needs to increase performance or computing power, it is necessary to additionally increase the number of bare dies. How to perform the external or internal electrical connection between the bare dies inside and outside the packaging unit is also an important problem to be solved. Summary of the Utility Model

[0006] The main purpose of the utility model is to provide a module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component, including a carrier board, a first bare die, a first dielectric layer, a plurality of first conductive connection lines, a second dielectric layer, a plurality of second conductive connection lines, a second bare die, an electronic component, at least one first wire bond, at least two second wire bonds, and at least one third wire bond; wherein each second conductive connection line is formed by grinding the metal paste filled in each second groove of the second dielectric layer, and each second conductive connection line forms a solder pad in each second groove; wherein the first bare die can be externally electrically connected through the pads around the chip area on the second surface of the first bare die, effectively solving the problem that the fan-out packaging technology in the existing module is prone to high manufacturing costs and is not conducive to environmental protection when manufacturing each conductive connection line.

[0007] To achieve the above object, the present utility model provides a module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component. The module includes a carrier plate, a first die, a first dielectric layer, a plurality of first conductive lines, a second dielectric layer, a plurality of second conductive lines, a second die, an electronic component, at least one first bonding wire, at least two second bonding wires, and at least one third bonding wire. The carrier plate has a first surface and a second surface opposite thereto. The first die is separated from a wafer. The first die has a first surface and a second surface opposite thereto. The first surface of the first die is fixedly disposed on the second surface of the carrier plate. The second surface of the first die has a plurality of pads, and the vertical chip region of the second surface is defined as a chip region. The first dielectric layer is disposed on the second surface of the carrier plate and the second surface of the first die. The first dielectric layer has a plurality of first grooves formed by extending horizontally. Each pad of the first die is exposed through each first groove. Each first conductive line is formed by filling a metal paste in each first groove. Each first conductive line is electrically connected to each pad of the first die. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a plurality of second grooves formed by extending horizontally. Each second groove communicates with each first groove. Each second conductive line is formed by filling a metal paste in each second groove. Each second conductive line is electrically connected to each first conductive line. At least one of the second grooves is located around the chip region on the second surface of the first die. Each second conductive line forms a bonding pad in each second groove by being exposed through each second groove. The first die can be electrically connected externally in sequence through each pad of the first die, each first conductive line, each second conductive line, and each bonding pad located around the chip region on the second surface of the first die. The second die is separated from a wafer. The second die has a first surface and a second surface opposite thereto. The first surface of the second die is fixedly disposed on the second dielectric layer to form the fan-out wafer-level packaging unit. The second surface of the second die has a plurality of pads. The electronic component has a first surface on which the first surface of the carrier plate is disposed. Each first bonding wire is subjected to a wire bonding operation to form a first solder joint on each bonding pad and a second solder joint on each pad of the second die, so that the first die and the second die of the fan-out wafer-level packaging unit can form an electrical connection.Each of the second bonding wires is subjected to a wire bonding operation to form a third solder joint on each of the pads around the chip region and a fourth solder joint on the first surface of the electronic component, so that the first die and the second die of the fan-out wafer-level packaging unit can be electrically connected to the electronic component; each of the third bonding wires is subjected to a wire bonding operation to form a fifth solder joint on each of the pads of the second die and a sixth solder joint on the first surface of the electronic component, so that the second die of the fan-out wafer-level packaging unit can be electrically connected to the electronic component.

[0008] In a preferred embodiment of the present invention, the electronic component is a printed circuit board (PCB, Printed circuitboard).

[0009] In a preferred embodiment of the present invention, the surface of each of the pads is flush with the surface of the second dielectric layer.

[0010] In a preferred embodiment of the present invention, the first die and the second die are formed by dividing the same wafer or different wafers.

[0011] In a preferred embodiment of the present invention, the carrier plate includes a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate.

[0012] In a preferred embodiment of the present invention, each of the first conductive lines is composed of silver paste, nano silver paste, copper paste or nano copper paste.

[0013] In a preferred embodiment of the present invention, each of the second conductive lines is composed of silver paste, nano silver paste, copper paste or nano copper paste.

[0014] In a preferred embodiment of the present invention, the first surface of the first die is further disposed on the carrier plate by using a die attach film (DAF, Die Attach Film).

[0015] In a preferred embodiment of the present invention, the first surface of the second die is further disposed on the carrier plate by using a die attach film. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic plan view of a side cross-section of the module of the present invention.

[0017] Figure 2 is a schematic plan view of a side cross-section of the first die of the present invention disposed on the carrier plate.

[0018] Figure 3 is at Figure 2A schematic plan view of a side cross-section of a first dielectric layer laid on a first die.

[0019] Figure 4 It is Figure 3 A schematic plan view of a side cross-section of a metal paste filled in a first groove in

[0020] Figure 5 It is Figure 4 A schematic plan view of a side cross-section of the metal paste ground to form a first conductive line in

[0021] Figure 6 It is Figure 5 A schematic plan view of a side cross-section of a second dielectric layer laid on a first dielectric layer in

[0022] Figure 7 It is Figure 6 A schematic plan view of a side cross-section of a metal paste filled in a second groove in

[0023] Figure 8 It is Figure 7 A schematic plan view of a side cross-section of the metal paste ground to form a second conductive line in

[0024] Figure 9 It is Figure 8 A schematic plan view of a side cross-section of a second die arranged on a second dielectric layer in

[0025] Explanation of reference numerals: 1 - module; 1a - chip area; 1b - fan-out wafer-level packaging unit; 10 - carrier board; 11 - first surface; 12 - second surface; 20 - first die; 21 - first surface; 22 - second surface; 23 - crystal pad; 30 - first dielectric layer; 31 - first groove; 40 - first conductive line; 40a - metal paste; 50 - second dielectric layer; 51 - second groove; 60 - second conductive line; 60a - metal paste; 70 - second die; 71 - first surface; 72 - second surface; 73 - crystal pad; 80 - electronic component; 81 - first surface; 90 - first bonding wire; 91 - first solder joint; 92 - second solder joint; 100 - second bonding wire; 101 - third solder joint; 102 - fourth solder joint; 110 - third bonding wire; 111 - fifth solder joint; 112 - sixth solder joint; 120 - chip bonding film. Detailed implementation manners

[0026] In conjunction with the drawings, the structure and technical features of the present utility model will be described in detail as follows. Each drawing is only used to illustrate the structural relationship and related functions of the present utility model. Therefore, the dimensions of each component in each drawing are not drawn according to the actual ratio and are not used to limit the present utility model.

[0027] Refer to Figure 1, the present utility model provides a module 1 in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component. The module 1 includes a carrier 10, a first die 20, a first dielectric layer 30, a plurality of first conductive lines 40, a second dielectric layer 50, a plurality of second conductive lines 60, a second die 70, an electronic component 80, at least one first bonding wire 90, at least two second bonding wires 100, and at least one third bonding wire 110.

[0028] The carrier 10 has a first surface 11 and an opposite second surface 12, as Figure 2 shown.

[0029] The first die 20 is separated from a wafer. The first die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of the first die 20 is fixedly disposed on the second surface 12 of the carrier 10. A plurality of pads 23 are provided on the second surface 22 of the first die 20, and a vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 2 shown. In Figure 2 , two pads 23 are taken as an example for each pad 23 of the first die 20, but it is not used to limit the present utility model.

[0030] The first dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and the second surface 22 of the first die 20. The first dielectric layer 30 has a plurality of first grooves 31 formed by extending horizontally, as Figure 3 shown; each pad 23 of the first die 20 is exposed to the outside by each first groove 31, as Figure 3 shown.

[0031] Each first conductive line 40 is composed of a metal paste 40a filled in each first groove 31. Each first conductive line 40 is electrically connected to each pad 23 of the first die 20, as Figure 5 shown.

[0032] The second dielectric layer 50 is disposed on the first dielectric layer 30. The second dielectric layer 50 has a plurality of second grooves 51 formed by extending horizontally. Each second groove 51 communicates with each first groove 31, as Figure 6 shown.

[0033] Each second conductive line 60 is composed of a metal paste 60a filled in each second groove 51. Each second conductive line 60 is electrically connected to each first conductive line 40, as Figure 8 shown; at least one of the second grooves 51 is located around the chip area 1a on the second surface 22 of the first die 20, as Figure 9As shown; wherein each second conductive line 60 is exposed to the outside through each second groove 51, and a solder pad 61 is formed in each second groove 51, as Figure 9 shown; wherein the first die 20 can be electrically connected to the outside in sequence through the pads 23 of the first die 20, the first conductive lines 40, the second conductive lines 60, and the solder pads 61 around the chip region 1a on the second surface 22 of the first die 20, as Figure 9 shown.

[0034] The second die 70 is separated from a wafer. The second die 70 has a first surface 71 and a second surface 72 opposite thereto. The first surface 71 of the second die 70 is fixedly disposed on the second dielectric layer 50 to form the fan-out wafer-level packaging unit 1b, as Figure 9 shown; wherein there are a plurality of pads 73 on the second surface 72 of the second die 70, as Figure 9 shown. In Figure 9 the description, two pads 73 are taken as an example for the pads 73 of the second die 70, but it is not intended to limit the present invention.

[0035] The electronic component 80 has a first surface 81 for the first surface 11 of the carrier 10 to be disposed thereon, as Figure 1 shown; wherein the electronic component 80 is a printed circuit board (PCB), but it is not limited.

[0036] Each first bonding wire 90 is subjected to a wire bonding operation to form a first solder joint 91 on each solder pad 61 and a second solder joint 92 on each pad 73 of the second die 70, so that the first die 20 and the second die 70 of the fan-out wafer-level packaging unit 1b can be electrically connected, as Figure 1 shown.

[0037] Each second bonding wire 100 is subjected to a wire bonding operation to form a third solder joint 101 on each solder pad 61 around the chip region 1a and a fourth solder joint 102 on the first surface 81 of the electronic component 80, so that the first die 20 and the second die 70 of the fan-out wafer-level packaging unit 1b can be electrically connected to the electronic component 80, as Figure 1 shown.

[0038] Each third bonding wire 110 is subjected to a wire bonding operation to form a fifth solder joint 111 on each pad 73 of the second die 70 and a sixth solder joint 112 on the first surface 81 of the electronic component 80, so that the second die 70 of the fan-out wafer-level packaging unit 1b can be electrically connected to the electronic component 80, as Figure 1as shown

[0039] The wire bonding operation described above is a common existing technique and will not be elaborated here.

[0040] Refer to Figure 1 , each pad 61 further bears the positive pressure generated during the wire bonding operation or the formation of solder joints, so that the internal circuit will not be damaged by the positive pressure, and the internal circuit (such as each first conductive line 40) can be allowed to pass through or be arranged below each pad 61.

[0041] The method of manufacturing the module 1 may include the following steps, but is not limited thereto:

[0042] Step S1: Provide a carrier 10, as Figure 2 shown; wherein the carrier 10 has a first surface 11 and a second surface 12 opposite thereto, as Figure 2 shown.

[0043] Step S2: Dispose a plurality of first bare dies 20 separated from at least one wafer (Wafer) on the carrier 10, as Figure 2 shown; wherein each first bare die 20 has a first surface 21 and a second surface 22 opposite thereto, the first surface 21 of each first bare die 20 is disposed on the carrier 10, and a plurality of pads 23 are provided on the second surface 22 of each first bare die 20, and the vertical chip area of the second surface 20 is defined as a chip area 1a, as Figure 2 shown.

[0044] Step S3: First, lay a first dielectric layer 30 on the carrier 10 and the second surface 22 of each first bare die 20, and form a plurality of first grooves 31 in a horizontal direction on the first dielectric layer 30, so that each pad 23 of each first bare die 20 can be exposed to the outside through each first groove 31, as Figure 3 shown. Then, fill the metal paste 40a into each first groove 31 and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 4 shown, and grind the metal paste 40a higher than the surface of the first dielectric layer 30, so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30 to form a plurality of first conductive lines 40, as Figure 5 shown. After that, lay a second dielectric layer 50 on the first dielectric layer 30, and form a plurality of second grooves 51 in a horizontal direction on the second dielectric layer 50, so that each second groove 51 can communicate with each first groove 31, as Figure 6 shown, and at least one of the second grooves 51 is formed around the chip area 1a on the second surface 22 of the first bare die 20, as Figure 9As shown, finally, metal paste 60a is filled into each of the second grooves 51 and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as Figure 7 shown, and the metal paste 60a higher than the surface of the second dielectric layer 50 is ground so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50 to form a plurality of second conductive lines 60, as Figure 8 shown, and each of the second conductive lines 60 can be exposed to the outside through each of the second grooves 51 to form a solder pad 61 in each of the second grooves 51, as Figure 9 shown.

[0045] Step S4: A second die 70 is disposed on the second dielectric layer 50, as Figure 9 shown: wherein the second die 70 has a first surface 71 and a second surface 72 opposite thereto, the first surface 71 of the second die 70 is fixedly disposed on the second dielectric layer 50, and a plurality of die pads 73 are provided on the second surface 72 of the second die 70, as Figure 9 shown.

[0046] Step S5: A dicing operation is performed to form a plurality of fan-out wafer-level packaging units 1b by dicing, as Figure 9 shown; wherein each of the fan-out wafer-level packaging units 1b has the first die 20 and the second die 70, as Figure 9 shown, and each of the fan-out wafer-level packaging units 1b shown in Figure 9 is taken as an example of one fan-out wafer-level packaging unit 1b for illustration, but not to limit the present invention.

[0047] Step S6: An electronic component 80 is provided and the electronic component 80 has a first surface 81, and the first surface 11 of the carrier 10 of one of the fan-out wafer-level packaging units 1b is disposed on the first surface 81 of the electronic component 80, as Figure 1 shown.

[0048] Step S7: A wire bonding operation is performed to form at least one first bonding wire 90, at least two second bonding wires 100 and at least one third bonding wire 110 on the fan-out wafer-level packaging unit 1b or the electronic component 80, as Figure 1 shown; wherein each of the first bonding wires 90 forms a first solder joint 91 on each of the die pads 61 of the first die 20 of the fan-out wafer-level packaging unit 1b and a second solder joint 92 on each of the die pads 72 of the second die 70, as Figure 1 shown; wherein each of the second bonding wires 100 forms a third solder joint 101 on each of the die pads 61 around the chip area 1a of the fan-out wafer-level packaging unit 1b and a fourth solder joint 102 on the electronic component 80, as Figure 1As shown; wherein each third bonding wire 110 forms a fifth solder joint 111 and a sixth solder joint 112 on each pad 73 of the second die 70 and on the first surface 81 of the electronic component 80, respectively, as Figure 1 shown; wherein the first die 20 and the second die 70 in the fan-out wafer-level packaging unit 1b on the electronic component 80 are electrically connected through the respective first bonding wires 90, as Figure 1 shown; wherein the first die 20 and the second die 70 of the fan-out wafer-level packaging unit 1b on the electronic component 80 and the electronic component 80 can be electrically connected through the respective second bonding wires 100, as Figure 1 shown; wherein the second die 70 of the fan-out wafer-level packaging unit 1b and the electronic component 80 can be electrically connected through the respective third bonding wires 110, thereby forming a module 1, as Figure 1 shown.

[0049] The process of step S3 in the method for manufacturing the fan-out wafer-level packaging unit 1b of the above-mentioned embodiment can be regarded as a key step in fabricating the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1b. First, a first dielectric layer 30 can be laid on the carrier 10 and the second surface 22 of each first die 20, and a plurality of first grooves 31 can be formed horizontally on the first dielectric layer 30, so that each pad 23 of each first die 20 can be exposed to the outside through each first groove 31, as Figure 3 shown. Then, a metal paste 40a is filled into each first groove 31 and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 4 shown, and the metal paste 40a higher than the surface of the first dielectric layer 30 is ground, so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30 to form a plurality of first conductive lines 40, as Figure 5 shown. After that, a second dielectric layer 50 is laid on the first dielectric layer 30, and a plurality of second grooves 51 are formed horizontally on the second dielectric layer 50, so that each second groove 51 can communicate with each first groove 31, as Figure 6 shown, and at least one of the second grooves 51 is formed around the chip area 1a on the second surface 22 of the first die 20, as Figure 9 shown. Finally, a metal paste 60a is filled into each second groove 51 and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as Figure 7 shown, and the metal paste 60a higher than the surface of the second dielectric layer 50 is ground, so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50 to form a plurality of second conductive lines 60, as Figure 8As shown, and each second conductive line 60 can be exposed to the outside through each second groove 51 to form a solder pad 61 in each second groove 51, as Figure 9 shown. Since step S3 of the above preferred embodiment is a process that can be easily and precisely implemented, the process can be simplified. It is sufficient to enable each first conductive line 40 and each second conductive line 60 in the redistribution layer (RDL) to generate XY-plane electrical extension and interconnection effects, and at the same time, the fabricated fan-out wafer-level packaging unit 1b can still maintain or achieve a certain degree of thinness, lightness, shortness, and small size.

[0050] Refer to Figure 9 , the surface of each solder pad 61 is flush with the surface of the second dielectric layer 50, but it is not limited, so that the structure maintains better structural flatness and is easy to perform wire bonding operations to increase the reliability of the product.

[0051] Refer to Figure 1 , the first die 20 and the second die 70 are formed by dividing from the same wafer or different wafers, but it is not limited, which is beneficial to diversified product development applications.

[0052] Refer to Figure 1 , the carrier board 10 includes a silicon (Si) carrier board, a glass carrier board, or a ceramic carrier board, but it is not limited, which is beneficial to diversified product development applications.

[0053] Refer to Figure 1 , the metal paste 40a constituting each first conductive line 40 further uses silver paste, nano silver paste, copper paste, or nano copper paste, but it is not limited, which is beneficial to diversified product development applications.

[0054] Refer to Figure 1 , the metal paste 60a constituting each second conductive line 60 further uses silver paste, nano silver paste, copper paste, or nano copper paste, but it is not limited, which is beneficial to diversified product development applications.

[0055] The above-mentioned nano silver paste material has characteristics such as low cost, high conductivity, and the ability to sinter at low temperature. However, since the nano silver paste material is a common existing material, it will not be elaborated here.

[0056] Refer to Figure 2 , the first surface 21 of the first die 20 is further disposed on the carrier board 10 by using a die attach film (DAF) 120, but it is not limited.

[0057] Refer to Figure 9 , the first surface 71 of the second die 70 is further disposed on the carrier board 10 by using a die attach film 120, but it is not limited.

[0058] Compared with the existing module technology with fan-out wafer-level packaging units, the module 1 of the present utility model has the following advantages:

[0059] (1) The fan-out wafer-level packaging unit 1b of the module 1 of the present utility model can be manufactured through step S3 in the preferred manufacturing method. Compared with the related manufacturing technologies of the fan-out wafer-level packaging units in the existing modules, when manufacturing the fan-out wafer-level packaging unit 1b of the present utility model, through the production of each conductive connection line in the RDL, each conductive connection line in the RDL can have XY-plane electrical extension and interconnection effects, and at the same time, it can also maintain or achieve a certain degree of thin, light, short, and small effects. These are all simplified and easily precisely implemented steps, especially beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present utility model is not only more simplified and cost-saving, but also can effectively improve the usage efficiency and reliability of the module 1.

[0060] (2) In the forming process of the conductive connection lines of the module 1 of the present utility model, the first dielectric layer 30 can be first laid on the second surface 22 of the carrier board 10 and each first bare die 20, and each first groove 31 is formed horizontally on the first dielectric layer 30, so that each pad 23 of each first bare die 20 can be exposed to the outside through each first groove 31, as Figure 3 shown. Then, the metal paste 40a is filled into each first groove 31 and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 4 shown, and the metal paste 40a higher than the surface of the first dielectric layer 30 is ground so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30 to form each first conductive connection line 40, as Figure 5 shown. After that, the second dielectric layer 50 is laid on the first dielectric layer 30, and each second groove 51 is formed horizontally on the second dielectric layer 50 so that each second groove 51 can communicate with each first groove 31, as Figure 6 shown, and at least one of the second grooves 51 is formed around the chip area 1a on the second surface 22 of the first bare die 20, as Figure 9 shown. Finally, the metal paste 60a is filled into each second groove 51 and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as Figure 7 shown, and the metal paste 60a higher than the surface of the second dielectric layer 50 is ground so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50 to form each second conductive connection line 60, as Figure 8 shown, and each second conductive connection line 60 can be exposed to the outside through each second groove 51 to form each solder pad 61 in each second groove 51, as Figure 9As shown, the module 1 of the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness in the production of each conductive line in the existing fan-out packaging technology.

[0061] (3) The module 1 of the present utility model forms each first bonding wire 90, each second bonding wire 100, and each third bonding wire 110 on the fan-out wafer-level packaging unit 1b or the electronic component 80 through wire bonding operation techniques, as Figure 1 shown; each first bonding wire 90 forms the first solder joint 91 on each pad 61 of the first die 20 of the fan-out wafer-level packaging unit 1b and forms the second solder joint 92 on each pad 72 of the second die 70, as Figure 1 shown; each second bonding wire 100 forms the third solder joint 101 on each pad 61 around the chip area 1a of the fan-out wafer-level packaging unit 1b and forms the fourth solder joint 102 on the electronic component 80, as Figure 1 shown; each third bonding wire 110 forms the fifth solder joint 111 and the sixth solder joint 112 on each pad 73 of the second die 70 and the first surface 81 of the electronic component 80, respectively, as Figure 1 shown; the first die 20 and the second die 70 in the fan-out wafer-level packaging unit 1b on the electronic component 80 are electrically connected through each first bonding wire 90, as Figure 1 shown; the first die 20 and the second die 70 of the fan-out wafer-level packaging unit 1b on the electronic component 80 and the electronic component 80 can be electrically connected through each second bonding wire 100, as Figure 1 shown; the second die 70 of the fan-out wafer-level packaging unit 1b and the electronic component 80 can be electrically connected through each third bonding wire 110. Thus, when the FOWLP packaging unit needs to increase its performance or computing power, the wire bonding operation technique is used to achieve the external or internal electrical connection between the die inside the packaging unit and the external die, and the number of dies can be additionally increased to provide a product with higher performance or more functions, thereby increasing the market competitiveness of the product.

[0062] The above is only the preferred embodiment of the present utility model, which is illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.

Claims

1. A module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component, characterized in that: Include: A carrier having a first surface and an opposite second surface; A first bare die is cut from a wafer, the first bare die has a first surface and an opposite second surface, the first surface of the first bare die is fixed on the second surface of the carrier, the second surface of the first bare die has a plurality of pads, and a vertical chip area of ​​the second surface is defined as a chip area; A first dielectric layer is disposed on the second surface of the carrier and the second surface of the first bare crystal, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of the first bare crystal is exposed to the outside through each of the first grooves; A plurality of first conducting circuits, each of which is formed by metal paste filled in each of the first grooves, and each of the first conducting circuits is electrically connected to each of the die pads of the first bare die; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; A plurality of second conducting circuits, each of which is formed by metal paste filled in each of the second grooves, and each of the second conducting circuits is electrically connected to each of the first conducting circuits; wherein at least one of the second grooves is located around the chip region on the second surface of the first die; wherein each of the second conducting circuits is exposed to the outside by each of the second grooves and a bonding pad is formed in each of the second grooves; wherein the first die can be electrically connected to the outside via each of the die pads of the first die, each of the first conducting circuits, each of the second conducting circuits, and each of the bonding pads located around the chip region on the second surface of the first die in sequence; A second bare die is formed by dividing a wafer, the second bare die has a first surface and an opposite second surface, the first surface of the second bare die is fixed on the second dielectric layer to form the fan-out wafer-level packaging unit; wherein the second surface of the second bare die has a plurality of pads; an electronic component having a first surface on which the first surface of the carrier is disposed; At least one first bonding wire, each of the first bonding wires is subjected to a wire bonding operation to form a first solder joint on each bonding pad and a second solder joint on each die pad of the second die, so that the first die and the second die of the fan-out wafer-level packaging unit can be electrically connected; At least two second bonding wires, each of which is wire bonded to form a third bonding point on each bonding pad around the chip area and a fourth bonding point on the first surface of the electronic component, so that the first die and the second die of the fan-out wafer-level packaging unit can be electrically connected to the electronic component; and At least one third welding wire, each of which is subjected to wire bonding operations to form a fifth welding point on each of the die pads of the second bare die and a sixth welding point on the first surface of the electronic component, so that the second bare die of the fan-out wafer-level packaging unit can form an electrical connection with the electronic component.

2. The module according to claim 1, characterized in that The electronic component is a printed circuit board.

3. The module according to claim 1, characterized in that The surface of each of the bonding pads is flush with the surface of the second dielectric layer.

4. The module according to claim 1, characterized in that The first die and the second die are separated from the same wafer or different wafers.

5. The module according to claim 1, characterized in that The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

6. The module according to claim 1, characterized in that Each of the first conducting circuits is made of silver paste, nano silver paste, copper paste or nano copper paste.

7. The module according to claim 1, characterized in that Each of the second conducting circuits is made of silver paste, nano silver paste, copper paste or nano copper paste.

8. The module according to claim 1, characterized in that The first surface of the first bare die is disposed on the carrier by using a chip bonding film.

9. The module according to claim 1, characterized in that The first surface of the second bare die is disposed on the carrier by using a chip bonding film.

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