Memory

Abstract

The utility model relates to a memory. The memory is based on a three-dimensional flash memory and is provided with a plurality of stacked layers, and signal cross-layer interaction is supported in a multi-stacked layer structure of the three-dimensional flash memory. The memory comprises a first memory unit located on any stack layer, a second memory unit located on a different stack layer, and a silicon controlled device connected between an input port of the second memory unit and a reference ground of the second memory unit. When the voltage difference between the first power line and the second power line exceeds a standard value due to different working states of the first storage unit and the second storage unit, the silicon controlled device is guided to be switched on, so that voltage or current impact of an output signal of the first storage unit on an input port of the second storage unit during cross-layer interaction is inhibited. Otherwise, when the voltage difference between the first power line and the second power line is lower than the standard value, the silicon controlled device is forbidden, and the output signal is interacted to the input port of the second storage unit.

Description

Technical Field

[0001] The utility model mainly relates to the technical field of memory, and more specifically, to a memory based on three-dimensional flash memory and realizing signal cross-layer interaction in the semiconductor memory of the three-dimensional flash memory. Background Art

[0002] In the field of data storage, in order to overcome the limitations of two-dimensional storage devices, the industry has begun to develop memory components with three-dimensional structural features. The main design idea is to increase the integration density by arranging many memory cells three-dimensionally on the semiconductor substrate. Three-dimensional memory, such as 3D-NAND, is a flash memory device in which storage cells are constructed in a three-dimensional stacked manner. In the 3D-NAND memory structure, it usually includes a stacking structure with storage function and an external circuit structure with interconnection function and other auxiliary circuits. In a three-dimensional storage device such as 3D-NAND flash memory, the flash memory is usually physically divided into multiple blocks, each block includes a certain number of storage cells. The erase operation of flash memory is usually based on the block as the basic unit, that is, the smallest unit.

[0003] As the name implies, the three-dimensional flash memory stacking structure based on the three-dimensional memory will generate different levels of storage areas or storage units on different stacking layers, and the storage areas or storage units at different levels are usually in different working states, such as write operation, read operation or erase operation. Three-dimensional memories from different manufacturers or three-dimensional memories from the same manufacturer but customized for different customers may have different block or unit division standards. There are some doubts about the interaction between any two storage areas or storage units at different levels, because the working states of the two storage areas or storage units are usually different. For example, if one in the normal data transmission and reception state sends data information to another in the standby silent state at a different level, their interaction may not only fail to complete normally, but even the latter may cause various abnormalities such as disordered working timing, false triggering of local circuits, and generation of unexpected leakage current or dark current due to the ineffective voltage and current impact from other layers. How to realize cross-layer signal interaction in three-dimensional flash memory is a difficult problem that needs to be solved urgently. Utility Model Content

[0004] The present application relates to a memory, which is based on a three-dimensional flash memory and has a plurality of stacked layers, and supports signal cross-layer interaction in a multi-stacked layer structure of the three-dimensional flash memory of the memory. The memory also includes:

[0005] A first storage unit located in any stacking layer is provided with a first power line;

[0006] A second storage unit located in a different stacking layer than any of the stacking layers, and configured with a second power line;

[0007] A load disposed between a first power supply line and a second power supply line;

[0008] A thyristor device connected between the input port of a second storage unit and the reference ground of the second storage unit;

[0009] A driving signal is generated by comparing the voltage sensed across the load and the output signal of the output port of the first storage unit, which is used to drive a thyristor device triggered by a transistor, and the driving signal is used to turn on or off the transistor that mates with the thyristor device;

[0010] When the voltage difference between the first and second power supply lines exceeds the specified value due to different operating states of both the first and second storage units, the thyristor device is guided to conduct, thereby suppressing the voltage or current impact on the input port of the second storage unit by the output signal of the first storage unit during cross-layer interaction; conversely, when the voltage difference between the first and second power supply lines is lower than the specified value, the thyristor device is disabled, allowing the output signal to interact with the input port of the second storage unit.

[0011] The above-mentioned memory: An operational amplifier and a comparator are configured in each stacked layer. The operational amplifier is used to calculate the voltage sensed across the load, and a coupling capacitor is used to couple the output signal to the inverting terminal of the comparator and couple the output terminal of the operational amplifier to the non-inverting terminal of the comparator; the comparison result of the comparator is regarded as the driving signal for controlling the on or off of the transistor.

[0012] The above-mentioned memory: A sampling circuit is configured in each stacked layer. The sampling circuit includes a NOR gate, a delay unit, and an inverter; the sampling circuit samples the sudden change voltage at the input port of the second storage unit. The voltage at the input port of the second storage unit is directly input to the first input terminal of the NOR gate, and the voltage at the input port of the second storage unit is input to the second input terminal of the NOR gate after passing through the delay unit and the inverter; the output of the NOR gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. When the electrostatic protection transistor is reversely broken down and turned on due to the sudden change voltage, the electrostatic protection transistor is turned off again; alternatively, the sampling circuit samples the sudden change voltage at the input port of the second storage unit. The voltage at the input port of the second storage unit is input to the first input terminal of the NOR gate, and the voltage at the input port of the second storage unit is input to the second input terminal of the NOR gate after passing through the delay unit and the inverter; the output of the NOR gate and the driving signal are input to an AND gate for performing a logical AND operation, and the output of the AND gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. When the electrostatic protection transistor is reversely broken down and turned on due to the sudden change voltage, the electrostatic protection transistor is turned off again.

[0013] The above-mentioned memory: If the voltage difference between the first and second power supply lines exceeds the specified value, the logic high level of the output signal disables the drive signal and the logic low level of the output signal enables the drive signal, keeping the drive signal continuously and dynamically switching between the disabled and enabled states; if the voltage difference between the first and second power supply lines is lower than the specified value, both the logic high level and the logic low level of the output signal disable the drive signal.

[0014] The above-mentioned memory: An operational amplifier is used to calculate the voltage sensing value of the load, a coupling capacitor is used to couple the output signal to the inverting terminal of a comparator, and the output terminal of the operational amplifier is coupled to the non-inverting terminal of the comparator; the comparison result of the comparator is regarded as the drive signal for controlling the on / off of the transistor.

[0015] The above-mentioned memory: Based on the condition that the voltage difference between the first and second power supply lines exceeds the specified value and the thyristor device enters the on state: the electrostatic protection transistor configured between the input port of the second storage unit and the second power supply line is clamped in the off state to cut off the dark current flowing from the first power supply line through the second power supply line, the electrostatic protection transistor, the thyristor device and flowing to the reference ground.

[0016] The above-mentioned memory: At the moment when a voltage drop is generated between the first power supply line and the reference ground and the electrostatic protection transistor is reversely broken down due to the on state of the thyristor device, the electrostatic protection transistor is at least forced to turn off once to form a break point of the dark current at the electrostatic protection transistor, but does not affect the original function of the thyristor device for suppressing the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit.

[0017] The above-mentioned memory: A sampling circuit samples the mutated voltage at the input port of the second storage unit. The sampling circuit directly inputs the voltage at the input port of the second storage unit to the first input terminal of the NOR gate, and inputs the voltage at the input port of the second storage unit to the second input terminal of the NOR gate after passing through the delay unit and the inverter for delay and inversion respectively; the output of the NOR gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor, so that at the moment when the electrostatic protection transistor itself is reversely broken down and turned on due to the mutated voltage, the electrostatic protection transistor is at least turned off again.

[0018] The above-mentioned memory: A sampling circuit samples the mutated voltage at the input port of the second memory cell. The sampling circuit inputs the voltage at the input port of the second memory cell to the first input terminal of an OR-NOT gate, and inputs the voltage at the input port of the second memory cell to the second input terminal of the OR-NOT gate after being delayed and inverted by a delay unit and an inverter respectively. The driving signal and the output of the OR-NOT gate are input to an AND gate to perform a logical AND operation. The output of the AND gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. Thus, at the moment when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage, the electrostatic protection transistor is at least turned off again.

[0019] The above-mentioned memory: The prerequisite for the sampling circuit to effectively sample the mutated voltage is that the voltage difference between the first and second power supply lines exceeds the specification value. Among them, the voltage impact on the input port of the second memory cell by the output signal of the first memory cell during the cross-layer interaction is an invalid sampling for the sampling circuit.

[0020] This application relates to a method for cross-layer interaction of signals in a 3D flash memory, which is characterized by including:

[0021] A load is provided between the first power supply line of the first memory cell in any stack layer of the 3D flash memory and the second power supply line of the second memory cell in other different stack layers of the 3D flash memory;

[0022] The voltage sensed value across the load is compared with the output signal at the output port of the first memory cell to generate a driving signal for driving a thyristor device triggered by a transistor;

[0023] The thyristor device is connected between the input port of the second memory cell and the reference ground of the second memory cell, and the driving signal is used to operate the on / off of the supporting transistor for triggering the thyristor device;

[0024] When the voltage difference between the first and second power supply lines exceeds the specification value due to different working states of the first and second memory cells, the thyristor device is guided to conduct to suppress the voltage or current impact on the input port of the second memory cell by the output signal of the first memory cell during the cross-layer interaction; conversely, when the voltage difference between the first and second power supply lines is lower than the specification value, the thyristor device is prohibited from conducting.

[0025] The above method: If the voltage difference between the first and second power supply lines exceeds the specified value, the logic high level of the output signal disables the drive signal and the logic low level of the output signal enables the drive signal, keeping the drive signal continuously and dynamically switching between the disabled and enabled states; if the voltage difference between the first and second power supply lines is lower than the specified value, both the logic high level and the logic low level of the output signal disable the drive signal.

[0026] The above method: Use an operational amplifier to calculate the voltage sensing value of the load, use a coupling capacitor to couple the output signal to the inverting terminal of a comparator, and couple the output terminal of the operational amplifier to the non-inverting terminal of the comparator; the comparison result of the comparator is regarded as the drive signal for controlling the on / off of the transistor.

[0027] The above method: Based on the condition that the voltage difference between the first and second power supply lines exceeds the specified value and the thyristor device enters the on state: clamp the electrostatic protection transistor configured between the input port of the second storage unit and the second power supply line in the off state to cut off the dark current flowing from the first power supply line through the second power supply line, the electrostatic protection transistor, the thyristor device and flowing to the reference ground.

[0028] The above method: At the moment when the voltage drop is generated between the first power supply line and the reference ground and the electrostatic protection transistor is reversely broken down due to the on state of the thyristor device, at least turn off the electrostatic protection transistor once to form a break point of the dark current at the electrostatic protection transistor, but does not affect the original function of the thyristor device for suppressing the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit.

[0029] The above method: Use a sampling circuit to sample the mutated voltage of the input port of the second storage unit. The sampling circuit directly inputs the voltage of the input port of the second storage unit to the first input terminal of the NOR gate, and inputs the voltage of the input port of the second storage unit to the second input terminal of the NOR gate after passing through the delay and inversion of the delay unit and the inverter respectively; the output of the NOR gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor, so that at the moment when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage, at least turn off the electrostatic protection transistor again.

[0030] The above method: The sampling circuit samples the mutated voltage at the input port of the second storage unit. The sampling circuit inputs the voltage at the input port of the second storage unit to the first input terminal of an OR-NOT gate. The voltage at the input port of the second storage unit is respectively input to the second input terminal of the OR-NOT gate after passing through the delay and inversion of a delay unit and an inverter. The driving signal and the output of the OR-NOT gate are input to an AND gate to perform a logical AND operation. The output of the AND gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. Thus, at the moment when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage, the electrostatic protection transistor is at least turned off again.

[0031] The above method: The prerequisite for the sampling circuit to effectively sample the mutated voltage is that the voltage difference between the first and second power supply lines exceeds the specification value. Among them, the output signal of the first storage unit during the cross-layer interaction has an impact on the voltage at the input port of the second storage unit, which is an invalid sampling for the sampling circuit.

[0032] The aforementioned memory is compatible with existing 3D-Flash memories, such as vertical three-dimensional flash memories. Therefore, it is basically equivalent to the power consumption of current memories, and the increase in the circuit is very small. For example, for millions, tens of millions, or even hundreds of millions of transistors in the storage layer or stack layer, only a limited number of transistors are added, without adding too many auxiliary circuits, and it has extremely low static power consumption during non-signal cross-layer interaction. During the stage of signal cross-layer interaction between the storage layer or stack layer, it adapts to the different working states of any two storage regions or storage units in different storage layers or stack layers, and enables the signal interaction between any two storage regions or storage units to be successfully completed on the premise of not interfering with or damaging each other. Note that there are often differences in aspects such as the supply voltage, supply current, operating power consumption, and transistor operating range between the different working states of any two storage regions or storage units located in different layers. Typically, the working voltages or currents required for different operating ranges of transistors, such as cut-off, linear, or saturation amplification, are often quite different. The different power supply conditions between two storage regions or storage units in different working states will impact each other due to data interaction. This article can efficiently respond to and suppress this impact, meeting the signal interaction requirements of different storage layers under the three-dimensional architecture. It avoids various anomalies such as timing disorders, circuit mis-triggering, leakage current, or dark current in the impacted party during signal interaction. It solves the problem of mutual interference between two storage units located in different stack layers and participating in the interaction caused by signal cross-layer interaction actions in three-dimensional flash memories. Description of the Drawings

[0033] To make the above objectives, features, and advantages more understandable, the following will combine the drawings to elaborate on the specific implementation manners in detail. After reading the following description and referring to the following drawings, the features and advantages of this application will be obvious.

[0034] Figure 1 It is a schematic diagram of the three-dimensional distribution of memory cells in a three-dimensional flash memory type.

[0035] Figure 2 They are stacked layers sharing the same common semiconductor substrate but separated by dielectric layers.

[0036] Figure 3 It is for data interaction or signal interaction between memory cells in different stacked layers.

[0037] Figure 4 A thyristor device is connected between the input port of the memory cell and the reference ground.

[0038] Figure 5 It is to compare the load voltage sensed value with the output signal to generate a drive signal.

[0039] Figure 6 A sampling circuit samples the mutant voltage at the input port of the memory cell.

[0040] Figure 7 The drive signal and the output of the NOR gate are input to the AND gate to perform a logical AND operation. Detailed implementation manners

[0041] Next, in combination with specific embodiments, the technical solutions disclosed in this application will be clearly and completely described. However, the described embodiments are only the embodiments used for narrative illustration in this application rather than all the embodiments. Based on these embodiments, those skilled in the art should recognize that any solution obtained without creative labor falls within the protection scope of this application.

[0042] See Figure 1, the memory is based on 3D flash memory (3D-NAND) and has numerous stacked layers L0 - L2. Note that the stacked layers L0 - L2 shown in the figure are only partial storage layers for example, not all storage layers. The main idea of this article is to support cross-layer signal interaction. The three dimensions of the 3D, namely the X-axis (axis-X), Y-axis (axis-Y), and Z-axis (axis-Z), expand the number of memory cells from different dimensions: see that the stacked layer L0 has memory cells L0-B1, L0-B2. The stacked layer can also be referred to by terms such as storage layer or stack layer, etc. For example, the stacked layer L1 has memory cells L1-B1, L1-B1. The memory cell can also be referred to as a storage area or storage body. Again, for example, the stacked layer L2 has memory cells L2-B1, L2-B2. Based on the 3D flash memory stacked structure of the 3D memory, different levels of storage areas or memory cells are generated on different stacked layers, and different levels of storage areas or memory cells usually operate in different states. For example, conventional write operations, read operations, erase operations, data transmission, or data reception, etc. operate in a high-power consumption active state, while conventional low supply voltage or low supply current, etc. operate in a low-power consumption sleep state. Again, for example, some transistors or the vast majority of transistors in the memory cell operate in a standby state at the static operating point, and so on. All in all, the operating states of any two memory cells located at different levels are usually not the same, or in other words, their respective operating states cannot be determined in advance. This uncertainty will bring unpredictable negative drawbacks to the two memory cells participating in data interaction, as described below.

[0043] See Figure 1, there are some hidden doubts about the data interaction or signal communication between any two memory cells located in different levels, such as L0-B1 and L2-B2. The working states of memory cells such as L0-B1 and L2-B2 are usually different. Based on the explanation, assume that L0-B1 is operating in the data transceiver working state while L2-B2 is operating in the low-power sleep working state or in the standby state of receiving a small voltage and current. If L0-B1 sends data to L2-B2 to meet the interaction requirements of the memory, L2-B2 located in L2 will have greater drawbacks due to the sudden voltage and current impact from L0-B1 in other layers such as L0. Abnormalities such as working timing disorders, circuit mis-triggering, generation of unexpected leakage current or dark current will occur in L2-B2 located in L2. For example, many static functional modules sense a sudden influx of a large current or large voltage much larger than the working voltage or working current required for static, then it will respond to this mutation and rise from the low-frequency clock to the high-frequency clock in a timely manner. However, the functional module should still operate at the low-frequency clock according to the specification, which causes some modules including the storage function to have timing disorder abnormalities. In addition, the sudden influx of a large current or large voltage brought in during data interaction will also cause components such as the clamping circuit to be abnormally opened, the electrostatic protection circuit to be abnormally opened, and transistors or diodes that are prone to latch-up or avalanche parasitically in the substrate to be enabled, etc. These are all typical examples of some circuits of the memory cell being mis-triggered. The consequences of hidden problems such as leakage current or dark current are more serious.

[0044] See Figure 2 , taking a small number of memory cells in two layers such as L2 and L3 as an example, they are separated by a dielectric layer L23 such as silicon dioxide or silicon nitride between the two layers on the semiconductor substrate. The stacked layer L2 and the stacked layer below it are separated by the dielectric layer L12. By the same token, the stacked layer L3 and the stacked layer above it are separated by the dielectric layer L34. In 3D-NAND, it is required that memory cells in different levels perform data transceiver, power interconnection, or communication, etc. At this time, a conductive material such as tungsten material, doped silicon, copper material, or copper-aluminum alloy is prepared in the dielectric layer L23. Usually, the TSV (through silicon via) technology is used to fabricate this conductive material between memory cells in different levels. The through-silicon via technology typically opens a through-hole between two semiconductor silicon layers and fills the through-hole with the aforementioned conductive material to form a vertical electrical interconnection. If necessary, an insulating layer such as silicon dioxide or silicon nitride can be prepared on the sidewall of the through-hole by chemical vapor deposition, physical vapor deposition, or sputtering.

[0045] See Figure 2, taking a small number of memory cells in two levels L2 and L3 as an example. Although this example is based on two adjacent levels above and below, it should be noted that two levels separated by a short distance or a long distance non-adjacently also satisfy the features described below. Refer to the vias Via1 - Via6 or more vias fabricated at the position of the dielectric layer L23.

[0046] Refer to Figure 2 , taking a small number of memory cells in two adjacent levels L2 and L3 as an example: For example, if the power lines are connected in parallel on the same layer, the power lines V21 and V22 of the memory cells L2 - B1 and L2 - B2 are at the same potential. Again, if the power lines are connected in parallel on the same layer, the power lines V31 and V32 of the memory cells L3 - B1 and L3 - B2 are at the same potential. If the power lines are connected in parallel between different layers, the power lines V21 - V22 and the power lines V31 - V32 are at the same potential. For example, the interconnect line at via Via1 can be used to connect the power line V21 to V31, and the interconnect line at via Via4 can be used to connect the power line V22 to V32.

[0047] Refer to Figure 2 , taking a small number of memory cells in two adjacent levels L2 and L3 as an example: For example, if the reference ground is connected in parallel on the same layer, the reference grounds E21 and E22 of the memory cells L2 - B1 and L2 - B2 are at the same potential. If the reference ground is connected in parallel on the same layer, the reference grounds E31 and E32 of the memory cells L3 - B1 and L3 - B2 are at the same potential. If the reference ground is connected in parallel between different layers, the reference grounds E21 - E22 and the reference grounds E31 - E32 are at the same potential. For example, the interconnect line at via Via3 can be used to connect the power line E21 to E31, and the interconnect line at via Via6 can be used to connect the power line E22 to E32.

[0048] Refer to Figure 3, in this example, it is assumed that the storage unit L2-B1 in the normal data transceiver state sends data information to another storage unit L3-B2 at different levels and in the standby silent state. The so-called data information usually includes at least the most direct binary symbol sequence or other information contents of various current memory-related categories similar to read or write or instruction or command or address, etc. The problem is that the interaction of such data information between L2-B1 and L3-B2 may not only fail to be completed normally, but even the latter L3-B2 may generate the abnormality described in this application due to the high-frequency data sending action from the former L2-B1: the I / O port (input / output) of L3-B2 will be impacted by the voltage and current that appear in vain, resulting in disorder of the working time-sequence, mis-triggering of some local circuits such as the electrostatic clamping circuit, and unexpected leakage current or dark current. For example, the inducing factors of the leakage current or dark current flowing to E32 are largely the direct consequences of information interaction.

[0049] See Figure 3 , the storage unit L2-B1 sends the data stream D_FL1 to L3-B2. In the figure, SO21 is the data output port (I / O) of the storage unit L2-B1 in the lower layer of the stacked layer structure of the 3D flash memory, and SI32 is the data input port (I / O) of the storage unit L3-B2 in the upper layer of the stacked layer structure of the 3D flash memory. The output port SO21 can be connected to the input port SI32 using the interconnection line at the via Via2. The data bit width of the data stream D_FL1 can be either a single bit width or a multi-bit width that better meets the actual requirements. The more the bit width, the more the number of interconnection lines required.

[0050] See Figure 3 , note that L2-L3, etc. all share the same common substrate or wafer. The stacked layers of the 3D flash memory are basically fabricated in the same wafer, but only the storage areas are designed in layers. The leakage current or dark current flowing to E32 will also flow to the common substrate. Such current will not only have a negative impact on the local area of the storage unit L3-B2, but also backfire on the data sender L2-B1 itself. For example, it may secretly change the magnitude of V21 / E21, and it may also perform unexpected programming on the transistors of each storage unit in all layers (for example, signals such as voltage and current applied to the semiconductor substrate can easily erase or write data in units of physical blocks). Obviously, the stacked structure of the 3D flash memory will multiply or even exponentially amplify the drawbacks and consequences of such leakage current or dark current compared with other types of memories. Therefore, how to achieve signal cross-layer interaction in the 3D flash memory is an urgent problem to be solved.

[0051] See Figure 3, the storage unit L3-B2 sends the data stream D_FL2 to L2-B2. In the figure, SO32 is the data output port (I / O) of the storage unit L3-B2 in the upper layer of the stacked layer structure of the 3D flash memory. In the figure, SI22 is the data input port (I / O) of the storage unit L2-B2 in the lower layer of the stacked layer structure of the 3D flash memory. The interconnection line at the via Via5 can be used to connect the output port SO32 to the input port SI22. The data bit width of the data stream D_FL2 can be either a single bit width or a multi-bit width that is more in line with the actual requirements. Note that the generation of the data stream D_FL2 is very likely to be abnormally sent to the storage unit L2-B2. This is because, for example, when a large current or large voltage much larger than the working voltage or working current required for static state suddenly surges into the originally static storage unit L3-B2, it will respond to this mutation and be awakened in a timely manner. Under the awakening condition, the storage unit L3-B2 sends data to L2-B2. This chain reaction can also extend from the storage unit L2-B2 to more storage units not shown in the figure. In other words, the storage units originally in the established working state in the flash memory are involved in a large number of unnecessary or even wrong operating states under the influence of a small number of storage units with signal cross-layer interaction. This is also the problem faced by signal cross-layer interaction.

[0052] See Figure 3 , in an alternative embodiment, as shown in the storage unit L2-B1 in the next stacked layer and the storage unit L3-B2 in the upper stacked layer. Denote L2-B1 as the first storage unit and L3-B2 as the second storage unit. As shown in the figure, the relevant storage circuits Cir each equipped with these storage units (memory cell) usually include or represent components such as a storage unit control module (control circuit), a storage unit driver module (driver circuit), or a similar storage unit logic control module (logic circuit), and even a transistor array that can store symbol information. It should be noted that the storage units L2-B1 and L3-B2 are distributed in two adjacent upper and lower layers, and they can also be distributed in two non-adjacent stacked layers. That is to say, the first storage unit in any stacked layer of the 3D flash memory and the second storage unit in other different stacked layers of the 3D flash memory, including, for example, L2-B1, L3-B2, and L0-B1, L3-B1, etc., if they are distributed in two non-adjacent upper and lower layers, can still achieve information interaction through vias and their interconnection lines.

[0053] See Figure 3, in an alternative embodiment, TLC-NAND storage products with more than 200 layers have become the largest market for 3D flash memory, such as 236-layer NAND, 238-layer NAND, 232-layer NAND, etc. The so-called "layer" mentioned in the industry refers to the stacked layer shown in the figure. Therefore, the first storage unit in any stacked layer and the second storage unit in a different stacked layer can come from any two of the hundreds of storage layers.

[0054] See Figure 3 , some industry consensus regarding stacked layers or laminated layers: The so-called multi-layerization refers to an increase in the number of stacked word lines (such as the gate lines of unit transistors), aiming to improve the storage density of 3D NAND flash memory, such as the storage capacity per unit area. If the number of word line layers is doubled, according to simple calculations, the storage density will also double. The number of stacked or laminated word lines is expected to exceed 1000 layers, as announced at the international academic conference IEDM 2023.

[0055] See Figure 1 , the gradual scaling of 3D-NAND flash memory is the mainstream, but at the same time, it exacerbates the negative impact of dark current or leakage current associated with signal cross-layer interaction. This is because the tolerable value of dark current or leakage current in a semiconductor substrate with a smaller density is much lower than that in a semiconductor substrate with a larger density. Scaling usually increases the number of transistors in the plane area where the X-axis (axis-X) and Y (axis-Y) are located, that is, increases the density per unit area of the plane. At this time, the index can increase the amount of data that can be stored per unit area, such as per square millimeter. Scaling also increases the number of layers in the direction of the Z-axis (axis-Z), and the more layers there are, the greater the storage density and the larger the amount of data that can be stored. Any attempt to increase the storage density in the two-dimensional plane or the three-dimensional height direction will reduce the tolerance of dark current or leakage current faced by 3D flash memory, because scaling is equivalent to allowing dark current or leakage current to freely move uncontrollably inside a semiconductor substrate with a higher transistor density, which allows dark current or leakage current to more easily perform unexpected programming on the transistors of each storage unit in all layers. With the development trend of 3D flash memory with high density and large number of layers, dark current or leakage current is more severe for signal cross-layer interaction.

[0056] See Figure 4, in an alternative embodiment, a first memory cell such as L2-B1 in any stack layer of the 3D flash memory, for example L2, is equipped with a first power supply line V21, and a second memory cell such as L3-B2 in other different stack layers of the 3D flash memory, such as L3, is equipped with a second power supply line V32. A load is provided between the first power supply line V21 and the second power supply line V32, and the load ld provided at the second memory cell L3-B2 is taken as an example. The illustrated load ld can generally use an active load or a passive load. Common electronic components of an active load are N-type or P-type transistors, amplifiers, bipolar transistors, or combinations thereof, and common electronic components of a passive load are resistors, capacitors, inductors, or combinations thereof. More details about active loads or passive loads will not be elaborated one by one. The load ld can be connected between the power supply line V21 and the power supply line V32 through an interconnection line deployed in a via hole. In a suitable solution, it is preferably to use a combination of an active load and a passive load, for example, they are combined in series or in parallel.

[0057] See Figure 4 , in an alternative embodiment, a first memory cell such as L2-B1 in any stack layer of the 3D flash memory, for example L2, is equipped with a first reference ground E21, and a second memory cell such as L3-B2 in other different stack layers of the 3D flash memory, such as L3, is equipped with a second reference ground E32. The so-called reference ground (GND) or virtual ground is a concept of grounding and it has a relatively low potential. As shown in the figure, it is allowed that the reference ground E21 and the reference ground E32 are equipotential or non-equipotential.

[0058] See Figure 4 , in an alternative embodiment, a first memory cell such as L2-B1 in any stack layer of the 3D flash memory, for example L2, is regarded as a signal sender, and a second memory cell such as L3-B2 in other different stack layers of the 3D flash memory, such as L3, is regarded as a signal receiver. The transceiver of signals or data is a type of cross-layer interaction.

[0059] See Figure 4, in an alternative embodiment, the interconnecting wire at the via Via2 used previously can connect the output port SO21 of the first memory cell, such as L2-B1, to the input port SI32 of the second memory cell, such as L3-B2. The connection or coupling of ports is a basic condition for signal cross-layer interaction. Both the port SO21 and the port SI32 belong to I / O ports, which are common ports of memory cells and are part of the prior art. The I / O ports (pads) of 3D flash memory will not be elaborated again, but it is worth noting that in a multi-layer architecture, the interior of the flash memory is filled with a large number of cross-layer interconnecting wires that connect different I / O ports to each other. Its advantage is that interactions between memory cells can be performed conveniently and quickly, but its disadvantage is that this interaction mode can easily generate unnecessary crosstalk and various side effects between memory cells.

[0060] See Figure 4 , in an alternative embodiment, the voltage sensed value across the load ld can be compared with the output signal of the output port SO21 of the first memory cell, such as L2-B1. For example, the data stream D_FL1 or data sequence of SO21 is compared with the voltage sensed value, thereby generating a drive signal sg. The drive signal sg can drive the transistor-triggered thyristor device shown in the figure. The thyristor device is characterized by the semiconductor device PNPN. Regarding the transistor-triggered thyristor device: it means that the conduction or non-conduction (ON / OFF) of the thyristor device is triggered by a transistor. The transistor used to trigger the conduction of the thyristor device is represented by tri-mos in the figure. The transistor tri-mos can be an NMOS transistor or a PMOS transistor of the opposite type. The transistor tri-mos can be integrated with the semiconductor device PNPN on the same silicon wafer as an integral component (such as LVTSCR), or both the transistor tri-mos and the semiconductor device PNPN are discrete devices.

[0061] See Figure 4, in an alternative embodiment, the thyristor device is connected between the input port of a second memory cell such as L3-B2, e.g., SI32, and the reference ground E32 of the second memory cell such as L3-B2 in a different stacked layer L3. For the convenience of illustration, it is assumed in the figure that the node N0 is connected to the input port I / O of L3-B2, i.e., SI32. Therefore, the thyristor device is actually also connected between the node N0 and the reference ground E32 of the second memory cell such as L3-B2. The on / off state of the complementary transistor tri-mos of the thyristor device is controlled by the drive signal sg. For example, if the drive signal sg is used to trigger the complementary transistor tri-mos of the thyristor device to turn on, the thyristor conducts. If the drive signal sg is used to trigger the complementary transistor tri-mos of the thyristor device to turn off, the thyristor's characteristic is that it will not be cut off or turned off accordingly. Its characteristic is that even if the trigger voltage of the transistor tri-mos used to trigger the thyristor is removed, the thyristor still remains conducting.

[0062] See Figure 4, in an alternative embodiment, overall, the drive signal sg can drive a transistor-triggered thyristor device. Specifically, the drive signal sg is used to operate the on / off state of the companion transistor tri-mos for triggering the thyristor device. Thus, it can be seen that whether a current path is generated between node N0 or port SI32 and the reference ground E32 depends on the drive signal sg. When a current path is required between node N0 or port SI32 and E32 is related to the operating state of the second storage unit such as L3-B2: if it is in a low-power state, its power supply usually has a very low voltage level. For example, memory transistors that do not need to have a low data refresh rate for a long time usually operate in a low-power sleep or standby state compared to memory transistors with a high data refresh rate. Suppose an interaction occurs during this period, such as a sudden voltage or current impact at node N0 or port SI32. The jump signal accompanying the impact will radiate and be transmitted to the relevant circuit Cir of the memory cell. If the impact energy is sufficient to break the original operating state of the transistors in the memory cell, abnormalities such as timing disorders, local circuit mis-triggering, unexpected leakage current or dark current will occur. Typically, when several transistors of the second storage unit are in a static operating state, they usually enter appropriate states such as the cut-off region, linear region, or saturation region. The jump signal caused by the impact coupled to the gates, sources, or drains of these transistors will break the original appropriate operating range of the transistors. Then, the single transistor affected by the impact will naturally enter an uncontrollable state, and the combined circuit of several single transistors will be even more uncontrollable. Note the data stream D_FL1, data sequence, command, or instruction sent by the first storage unit such as L2-B1. These interaction quantities will produce the aforementioned impact or equivalent effect at node N0 or port SI32 of the second storage unit. It can be seen that the different operating states of the first storage unit and the second storage unit lead to the occurrence of abnormal situations, and the most intuitive manifestation of this difference in operating states is the voltage difference between the first power supply line V21 and the second power supply line V32. It should be noted that not all voltage differences will produce severe impacts. Those weaker voltage differences are not sufficient to generate enough impact power.

[0063] See Figure 4, in an alternative embodiment, conventional memory cells are each provided with an electrostatic protection transistor ESD-MOS, or an output stage transistor, etc. for I / O terminals such as input ports or output ports. For example, a single memory cell is provided with a PMOS type electrostatic protection transistor P1 connected between the input port and the power supply line, and a single memory cell is provided with an NMOS type electrostatic protection transistor N1 connected between the input port and the reference ground. Further, a single memory cell is provided with a PMOS type output stage transistor P2 connected between the output port and the power supply line, and a single memory cell is provided with an NMOS type output stage transistor N2 connected between the output port and the reference ground. This belongs to the prior art.

[0064] See Figure 4 , in an alternative embodiment, conventional memory cells are each provided with pulse protection or electrostatic protection ESD diodes D1-D4, etc. for I / O terminals such as input ports or output ports. For example, a single memory cell is provided with a pulse protection or electrostatic protection diode D1 connected between the input port and the power supply line, and a single memory cell is provided with a pulse protection or electrostatic protection diode D2 connected between the input port and the reference ground. Further, a single memory cell is provided with a pulse protection or electrostatic protection diode D3 connected between the output port and the power supply line, and a single memory cell is provided with a pulse protection or electrostatic protection diode D4 connected between the output port and the reference ground. This belongs to the prior art.

[0065] See Figure 4In an optional embodiment, as mentioned above, when the voltage difference between the first power line V21 and the second power line V32 of the first storage unit such as L2-B1 and the second storage unit such as L3-B2 exceeds the pre-designed or predetermined standard value (specified value) due to different working states, the thyristor device needs to be guided to conduct so as to suppress the current or voltage impact of the output signal such as D_FL1 at SO21 of the first storage unit such as L2-B1 on the input port SI32 of the second storage unit such as L3-B2 during the cross-layer interaction. Cross-layer means, for example, that the signal D_FL1 crosses the levels of two different stacking layers, so-called any stacking layer such as L2 and a different stacking layer such as L3. There are many design schemes for the predetermined standard value or specified value: assuming that a suitable turn-on threshold is configured for the transistor tri-mos, the transistor tri-mos can be turned on only when the voltage difference reaches the standard value or specified value under the threshold condition. For example, the threshold is designed according to a defined standard value or specified value. For example, the power supply of the comparator related to the driving signal sg or the operational amplifier related to the voltage sensing value can come from the first power line V21 or the second power line V32 coupled to the first power line V21. The high and low potential levels of the comparison result of the comparator or the driving signal are related to V21 and the difference between V21 and V32. The high potential level of the comparison result or the driving signal is designed to be below the reasonable standard value to drive the transistor tri-mos to turn on. On the contrary, when the voltage difference between the first power line V21 and the second power line V32 is lower than the standard value, the thyristor device is prohibited from turning on and at this time, the output signal of the first storage unit L2-B1, such as D_FL1 at SO21, can be smoothly transmitted to the input port of the second storage unit L3-B2, such as SI32, during the cross-layer interaction. For example, as mentioned above, if the voltage difference does not reach the standard value or the specified value, the transistor tri-mos cannot be turned on under its threshold condition. In addition, the load resistance or load impedance and other parameters are changed to adjust the standard value. For example, in an optional embodiment, a larger load resistance or load impedance can produce a large voltage difference and corresponds to a high design standard value, and a smaller load resistance or load impedance can produce a small voltage difference and corresponds to a low design standard value. If the voltage difference between V21 and V32 is exactly equal to the standard value, the thyristor device is actually allowed to be turned on, but there is no serious consequence if the thyristor device is not turned on at this time, because the destructive power of the impact power under critical conditions is small and belongs to the tolerable range, and there is no restriction on it. The selection of the standard value is diverse, for example, directly taking the power supply voltage on the first power line, or the standard value is selected to take a voltage value slightly lower than the power supply voltage on the first power line, or the standard value is selected to take half of the difference between V21 and E21, that is, the middle value, and the standard value can also be selected to select a voltage value within the difference range of the difference between V21 and E21, and so on.

[0066] See alsoFigure 4 In an alternative embodiment, when the voltage difference between the first power supply line and the second power supply line exceeds the specification value due to different operating states of both the first storage unit and the second storage unit, the thyristor device is guided to conduct, thereby suppressing the voltage or current impact on the input port of the second storage unit by the output signal of the first storage unit during cross-layer interaction (cross-layer includes spanning adjacent or non-adjacent layers); conversely, when the voltage difference between the first power supply line and the second power supply line is lower than the specification value, the thyristor device is prohibited from conducting.

[0067] See Figure 4 In an alternative embodiment, the voltage difference between the first power supply line and the second power supply lines V21 and V32 respectively exceeds the specification value. The output signal of the output port SO21 of the first storage unit, such as the logic high level of the data stream D_FL1 or the symbol one, causes the drive signal sg to be disabled, and the output signal such as the logic low level of the data stream D_FL1 or the symbol zero causes the drive signal sg to be enabled. Based on this design, the purpose is to maintain the continuous dynamic switching of the drive signal between the disabled (i.e., invalid) and enabled (i.e., valid) states. That is, to make the drive signal sg exhibit the characteristics of a pulsating signal or an alternating current signal. This is because the triggering conditions for the thyristor device and the trigger transistor to turn on or off are related to the degree of difference in the voltage difference between the first power supply line and the second power supply line, related to the voltage level of the high and low levels of the output signal data stream D_FL1, and related to factors such as the clutter noise mixed in the output signal such as the data stream D_FL1. And noise is inevitably present. Figure 3The multi-bit wide data stream D_FL1 uses side-by-side interconnect lines, and there is signal coupling between any two of the interconnect lines from SO21 to SI32. Especially in three-dimensional storage with high-density data storage, denser interconnect lines are used and data transmission occurs more frequently. Signal coupling is a typical type of parasitic noise between any two interconnect lines relative to each other. Generally, the closer the vias such as Via1 - Via6 are, the more severe the noise between adjacent vias. For example, when the power supply fluctuates in Via1, which is a power supply path, glitches will be generated on the interconnect lines inside Via1 and transmitted to the interconnect lines inside Via2 through spatial coupling or parasitic capacitance, etc. Such glitches coupled to the output signal are equivalent to the clutter of the data stream D_FL1 mixing frequencies. If the drive signal sg exhibits a static signal with a continuously high level or a static signal with a continuously low level, the thyristor device is likely not to be triggered due to the influence of the aforementioned factors. For example, the voltage difference that was originally sufficient to turn on the tri-mos is pulled down by a negative glitch. Another example is that the original data stream of the output signal is mixed with noise that pushes it up, making the comparison result of the comparator inaccurate. In the case of a static signal, the thyristor device can almost only rely on the initial state change of the drive signal sg. The initial state of the drive signal sg is a single comparison result of the comparator at a certain moment that is vulnerable to external influences and prone to errors. Similar to factors such as glitch pull-down or mixing noise, if an incorrect initial state of the drive signal sg is established, the drive signal sg will give an incorrect operation to the thyristor device, and the voltage impact or current impact on the input port SI32 of the second storage unit still cannot be overcome during signal cross-layer interaction.

[0068] See Figure 4 , in an alternative embodiment, considering the drawback that the thyristor device only depends on the switching change of the initial state of the drive signal, and in the static state, the switching change of the initial state of the drive signal is almost only once, so this application proposes to make the switching change of the drive signal occur multiple times dynamically. The logic high level of the output signal such as the data stream D_FL1 disables the drive signal, and the logic low level of the output signal enables the drive signal, keeping the drive signal sg continuously and dynamically switching between the disabled and enabled states. The drive signal sg exhibits a continuously changing dynamic signal, which is equivalent to the drive signal sg showing the characteristics of a pulsating signal or an alternating current signal at this time. The previous drawback that in the case of a static signal, the thyristor device can almost only rely on the initial state change of the drive signal sg (which is prone to errors) can thus be solved.

[0069] See Figure 4, in an alternative embodiment, the voltage differences of the first power supply line and the second power supply lines V21 and V32 are each lower than the specification value. At this time, the output signals such as the logic high level and the logic low level of the data stream D_FL1 both disable the drive signal sg. Considering that the thyristor device does not need to be triggered to conduct, it is necessary to keep the drive signal sg continuously disabled. Note that in this example, different from the previous requirement that the drive signal dynamically switches between being disabled (invalid) and enabled (valid), the static continuous disabling of the drive signal can extremely effectively avoid the mis-triggering of the thyristor device.

[0070] See Figure 4 , in an alternative embodiment, the operational amplifier am is used to calculate the voltage sensed value across the load ld. For example, the two input terminals of the operational amplifier am are respectively coupled to both ends of the load ld. If there is a voltage difference between V21 and V32, such a voltage difference will be reflected at the output terminal of the operational amplifier am. The greater the voltage difference, the greater the output value of the operational amplifier, or the smaller the voltage difference, the lower the output value of the operational amplifier. The role of the operational amplifier am in the figure is to calculate the voltage sensed value of the load ld: if the voltage difference between V21 and V32 is greater, this difference is mapped to the operational amplifier and makes the output value of am greater; if the voltage difference between V21 and V32 is smaller, this difference is mapped to the operational amplifier and makes the output value of am lower. One of the functions of the operational amplifier am is to amplify and operate on the target value, and the target value in the example in the figure is the voltage difference between V21 and V32. There are various types of operational amplifiers am. For example, it can output a positive voltage for the received and sensed positive voltage, or convert the received and sensed negative voltage into a positive voltage. These types are all optional solutions that can be adopted in this application. The voltage value of the load ld is allowed to have positive and negative voltages.

[0071] See Figure 4, an output signal such as a data stream D_FL1 is coupled to the inverting terminal of a comparator cm using a coupling capacitor tc, and the output terminal of an operational amplifier am is coupled to the non-inverting terminal of the comparator cm. The coupling capacitor tc can use a conventional capacitor or a MOS transistor capacitor as shown in the figure. As shown in the figure, for the MOS capacitor, the drain and source of the transistor are shorted as one electrode of the capacitor, and the gate is used as the other electrode of the capacitor. A large number of memory transistors or other types of transistors are deployed in any memory stack layer of the 3D flash memory. For example, backup transistors for defective pixels. Selecting a part of these transistors to fabricate MOS capacitors is a cost-saving solution. Fabricating a capacitor with capacitor plates in an integrated circuit usually requires a trade-off in terms of whether semiconductor area is wasted. The comparison result of the comparator cm can be regarded as a drive signal sg. Regarding the drive signal sg: it is mainly used to control the on / off of a complementary trigger transistor tri-mos of a thyristor device such as a PNPN type, and then drive and operate the thyristor device.

[0072] See Figure 4 , in an alternative embodiment, when the voltage difference between the first power supply line V21 and the second power supply line V32 exceeds the specified value, and when the thyristor device enters the on state, an electrostatic protection transistor configured between the input port of the second memory cell, such as the input port SI32 of LE-B2, and the second power supply line V32 is clamped in the off state. Here, the electrostatic protection transistor P1 configured between the input port SI32 or the node N0 and the second power supply line V32 is a PMOS transistor and belongs to the ESD protection circuit, and its gate is allowed to be connected to the source. At this time, the purpose of clamping the electrostatic protection transistor P1 in the off state is mainly to cut off the dark current or leakage current flowing from the first power supply line V21, through the second power supply line V32, the electrostatic protection transistor P1, the thyristor device, and to the reference ground E32 of the second memory cell. The clamping scheme will be continued to be introduced below.

[0073] See Figure 4, in an alternative embodiment, the dark current mechanism is as follows. When the thyristor device enters the on state and the voltage difference between both V21 and V32 exceeds the specification value, note that the thyristor device characteristic is that once triggered on, it cannot be turned off by the tri-mos. The sudden turn-on of the thyristor device will produce an effect similar to a negative pulse due to the sudden pull-down of the potential at node N0. A higher voltage of the first power supply line V21 compared to the second power supply line V32 is applied between the source and drain of the electrostatic protection transistor P1. Since the thyristor device is turned on, there is a high voltage between the source and drain of P1. The PN junction between the substrate (N-WELL) or body region (N-body) of the transistor P1 and its drain doping region such as the P-type heavily doped region is reverse broken down, and then a current conduction path allowing current to flow between the source and drain of the transistor P1 is generated. At this time, the dark current flows from the first power supply line V21 through the second power supply line V32, through the electrostatic protection transistor P1, and through the thyristor device to the reference ground E32 of the second storage unit. This dark current or leakage current is hidden and imperceptible, and is generated during the cross-layer interaction of the output signal such as D_FL1.

[0074] See Figure 4 , in an alternative embodiment, hereby it can be known that the advantage of the electrostatic protection transistor P1 is to prevent accidental pulses that occur at the input port or output port from damaging each circuit including the port of the storage unit. However, during the cross-layer interaction of the signal, the disadvantage of the electrostatic protection transistor P1 is that it induces dark current or leakage current. All stacked layers of the 3D flash memory share the same common semiconductor substrate. The dark current or leakage current injected into the semiconductor substrate is equivalent to the programming signal applied to the substrate region or body region of each transistor of each storage unit, thereby rewriting the default data of the storage transistors of each storage unit. The current branch where the dark current or leakage current is located will change the voltage drop of V21 / E21. Therefore, it is necessary to suppress, at the moment when the thyristor device is turned on (transient), the reverse breakdown of the PN junction (P++ / N-WELL) of the pull-up transistor such as the ESD electrostatic protection transistor P1 at the input port of the second storage unit such as SI32, which results in a current conduction branch in the pull-up transistor, forming a through current (i.e., dark current, leakage current) from the first power supply line V21 to the second power supply line V32, then flowing through the thyristor device based on the conduction branch of P1 to the reference ground E32. The ESD transistor often connects its source to the semiconductor substrate or body region of the transistor.

[0075] See Figure 5, in an alternative embodiment, based on the condition that the voltage difference between the first and second power supply lines exceeds the specified value and the thyristor device enters the on state: the electrostatic protection transistor configured between the input port of the second storage unit and the second power supply line is clamped in the off state to cut off the dark current flowing from the first power supply line through the second power supply line, the electrostatic protection transistor, the thyristor device and to the reference ground. This prevents the dark current (or leakage current) from unexpectedly programming the storage transistors of each storage unit (such as the first storage unit and the second storage unit) in each stacked layer.

[0076] See Figure 5 , in an alternative embodiment, as shown, the dark current or leakage current flowing from the first power supply line V21 of any stacked layer L2 through the second power supply line V32 of a different stacked layer L3, then through the electrostatic protection transistor P1, and through the thyristor device and flowing to the reference ground E32 of the different stacked layer L3 flows from L3 to L2 at the via Via6 in L3 and continues to flow from L2 to L1 at the via Via6 in the lower layer L2 until the dark current leaks to different stacked layers.

[0077] See Figure 5 , in an alternative embodiment, how to select the appropriate timing and select the appropriate mechanism to clamp the electrostatic protection transistor in the off state to cut off the dark current flowing from the first power supply line V21 through the second power supply line V32, the electrostatic protection transistor P1, and the thyristor device and flowing to the reference ground E32 is one of the problems. Because the premise is that it is not allowed to affect the original function of the thyristor device for suppressing the voltage or current impact of the output signal of the first storage unit L2-B1 on the input port of the second storage unit. It should be noted that the so-called non-influence on the original function of the thyristor device actually includes many aspects. For example, it is necessary to maintain the established protection effects of both ESD-P1 and ESD-N1 for electrostatic protection. At least, they cannot be manipulated additionally without limit, otherwise the function of the thyristor device connected in series or parallel with them will be indirectly affected due to this series-parallel relationship. For example, the unreasonable conduction or long-term conduction of the electrostatic protection transistor establishes a direct connection channel between V21 and V32 to E32. This will not only damage the electronic components on this direct connection channel but also be difficult to close this direct connection channel due to the intrinsic characteristics of the thyristor device. Furthermore, the control conditions of the electrostatic protection transistor are preferably coupled or decoupled with the output signal of the output port SO21 of the first storage unit and the voltage difference between the first power supply line and the second power supply line, so that the inappropriate activation time points of ESD-P1 or ESD-N1 can be greatly reduced. These measures are also effective ways to avoid the failure of the thyristor device in suppressing the "voltage impact or current impact caused by the output signal".

[0078] See Figure 6, in an alternative embodiment, the above-mentioned problem is solved as follows: a voltage drop may be generated between the first power supply line V21 and the reference ground E32 of the second storage unit, and at the moment when the static protection transistor, such as the pull-up transistor ESD static protection transistor P1, is reversely broken down due to the turn-on of the thyristor device, the static protection transistor P1 is at least forced to turn off once. A voltage drop is generated between V21 and the reference ground E32 of L3-B2, which means that the voltage difference based on the first power supply line and the second power supply line exceeds the specified value, and the thyristor device enters the on state. At this time, the sudden turn-on of the thyristor device will generate a negative pulse action due to the sudden drop of the potential at node N0, and the voltage drop generated by this so-called voltage difference will also be applied between the source and drain of the static protection transistor. There is a high voltage between the source and drain of P1, and the PN junction between the substrate (N-WELL) or body region (N-body) of the transistor P1 and its drain doping region, such as the P-type heavily doped region, is reversely broken down. If P1 is at least forced to turn off once at the moment of reverse breakdown, even if the transistor P1 is subjected to a negative pulse and a high voltage drop, the dark current flowing through the transistor P1 can be interrupted during the reverse breakdown period without affecting the normal operation of the thyristor device. Thus, a break point of the so-called dark current can be generated at the static protection transistor P1 without affecting the original function of the thyristor for suppressing the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit. It should be noted that when the ESD-PMOS, that is, P1, and the ESD-NMOS, that is, N1, are manipulated here, it is easy to affect the voltage or current impact of the output signal on the input port. For example, the manipulated ESD transistors P1 / N1 lose the possibility of discharging under voltage impact or current impact, that is, they lose the initial protection function, while this article can well avoid this point.

[0079] See Figure 6, one solution of the present application is: when a voltage drop is generated between the first power supply line V21 and the reference ground E32 and the static protection transistor such as P1 is reversely broken down instantaneously due to the turn-on of the thyristor device, the static protection transistor such as P1 is forced to turn off at least once. The transistor such as P1 can also be forced to turn off multiple times, but the number of times of forced turn-off depends on the number of times the transistor P1 itself is reversely broken down. As long as it is broken down and a path for dark current or leakage current is generated, it needs to be forced to turn off. The transistor such as P1 is turned off once or several times based on the fact that the process of its reverse breakdown and then turn-off may repeat: the potential of node N0 will oscillate during this process, and the degree of oscillation determines the situation of repeated reverse breakdown of the transistor. When the transistor such as P1 is reversely broken down, turning it off at least once can form a break point of the dark current at the static protection transistor such as P1, but does not affect the original function of the thyristor device for suppressing the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit. This break point effectively prevents the direct connection channel established between V21 and V32 to E32 due to the unreasonable conduction or long-term conduction of the static protection transistor. The electronic components of this direct connection channel include P1, N1, D1-D2, and the thyristor device, etc. If there is no break point, not only will the electronic components on this direct connection channel be damaged, but it will also be difficult to cut off this direct connection channel due to the intrinsic characteristic of the thyristor device that it is easy to conduct but difficult to turn off, providing an uncontrollable channel for the dark current.

[0080] See Figure 6 , in an alternative embodiment, a sampling circuit samples the mutated voltage of the input port of the second storage unit such as L3-B2, for example SI32. The sampling circuit directly inputs the voltage of the input port of the second storage unit such as L3-B2 to the first input terminal IN1 of the NOR gate NR of the sampling circuit, and inputs the voltage of the input port of the second storage unit such as L3-B2 to the other relative second input terminal IN2 of the NOR gate NR after being delayed by the delay unit DL and inverted by the inverter INV1. That is, the mutated voltage of node N0 or the input port such as SI32 is sampled by the sampling circuit and the sampling result is bifurcated: the mutated voltage or the sampling result of the voltage is input to the first input terminal of the NOR gate NR, and the sampling result is input to the second input terminal of the NOR gate NR after being delayed by the delay unit DL and inverted by the inverter INV1.

[0081] See Figure 6, the output of the NOR gate NR is coupled to the gate of the electrostatic protection transistor P1 through another inverter IV2 and a capacitor C in sequence. Thereby, at the moment when the electrostatic protection transistor P1 itself is reversely broken down and turned on due to the mutated voltage of the node N0, the electrostatic protection transistor P1 is at least turned off again. The principle of the circuit operation during this period is that if the voltage of the node N0 mutates, or the voltage jumps, etc., the sampling circuit is sensitive to this mutation of the voltage and generates a single pulse. For example, when the thyristor is suddenly turned on at the node N0 or the input port SI32, the potential at the node N0 suddenly drops, causing the NOR gate NR to generate a single pulse. The generated single pulse is inverted by the shown inverter IV2, and then the coupling capacitor C that isolates direct current couples the inverted signal to the gate of the electrostatic protection transistor P1. The single pulse will control the transistor P1 to be instantaneously turned off once. This is an alternative example of at least forcibly turning off the electrostatic protection transistor P1 once at the moment when a voltage drop occurs between the first power supply line and the reference ground E32, and the electrostatic protection transistor is reversely broken down due to the turn-on of the thyristor device. To form a break point of the dark current at the electrostatic protection transistor, so as to cut off the dark current flowing from the first power supply line through the second power supply line, the electrostatic protection transistor and the thyristor device to the reference ground E32. It can be seen that the electrostatic protection transistor is turned off because of the voltage drop between the first power supply line and the reference ground E32, and the electrostatic protection transistor is reversely broken down due to the sudden turn-on of the thyristor device. The electrostatic protection transistor is reversely broken down and immediately turned off, and the reverse breakdown and re-turn-off of the electrostatic protection transistor are almost instantaneously completed. Thereby, it can be known that at the moment when the electrostatic protection transistor, such as P1 itself, is reversely broken down and turned on due to the mutated voltage (this is one of the characteristics of the ESD transistor), at least subsequently or immediately afterwards, the electrostatic protection transistor, such as P1, is turned off again. The turn-on of the ESD transistor is before and the re-turn-off is after, but the process of turn-on and re-turn-off is actually almost transiently or instantaneously completed, with almost no time delay, and this is a characteristic of the transistor-level circuit. If the electrostatic protection transistor can be forcibly turned off once, then a break point of the dark current will be formed at the electrostatic protection transistor, but the thyristor device is still effective: this is because while the direct-through channel of the dark current is cut off, the thyristor device maintains conduction and allows the output signal of the first storage unit SO21 to flow from the conducting thyristor device to the reference ground E32 during the cross-layer interaction, thereby suppressing the voltage impact or current impact on the input port of the second storage unit SI32. This is an alternative embodiment of clamping the electrostatic protection transistor configured between the input port of the second storage unit and the second power supply line in the off state.

[0082] See Figure 6, in an alternative embodiment, the sampling circuit samples the mutated voltage at the input port of the second memory cell. The sampling circuit inputs the voltage at the input port of the second memory cell to the first input terminal of the NOR gate, and inputs the voltage at the input port of the second memory cell to the second input terminal of the NOR gate after being delayed and inverted by a delay unit and an inverter respectively. The output of the NOR gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. At the moment when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage, the electrostatic protection transistor is turned off again. This prevents the dark current (or leakage current) from unexpectedly programming the memory transistors of each memory cell (such as the first memory cell and the second memory cell) in each stacked layer.

[0083] See Figure 6 , in an alternative embodiment, the premise for the sampling circuit to effectively sample the mutated voltage at node N0 or input port SI32 is that the voltage difference between the first power supply line V21 and the second power supply line V32 exceeds a pre-designed or pre-determined specification value (prescribed value). However, it is required that the voltage impact of the output signal of SO21 of the first memory cell such as L2-B1 on the input port SI32 of the second memory cell such as L3-B2 during the cross-layer interaction is an invalid sampling for the sampling circuit. For this design, see Figure 7 the solution in. If the voltage impact of the output signal of the first memory cell such as L2-B1 on the input port SI32 of the second memory cell such as L3-B2 during the cross-layer interaction is not classified as an invalid sampling, the output signal is very likely to be considered as part of the mutated voltage, which is obviously illogical. Or the output signal is superimposed on the mutated voltage according to the principle of Fourier transform and generates mixing, which will undoubtedly change the mutated voltage. If the mutated voltage is inadvertently hidden and strengthened, it will cause abnormalities such as easier breakdown of P1 under high impact energy. It is necessary to prevent the output signal from being superimposed on the mutated voltage and causing the sampling circuit to sample the wrong mutated voltage.

[0084] See Figure 7, in an alternative embodiment, a sampling circuit samples the mutated voltage at the input port of the second storage unit, such as SI32 of L3-B2. The sampling circuit directly inputs the voltage at the input port of the second storage unit, such as L3-B2, to the first input terminal IN1 of the NOR gate NR of the sampling circuit, and inputs the voltage at the input port of the second storage unit, such as L3-B2, to the other relative second input terminal IN2 of the NOR gate NR after being delayed and inverted by the delay unit DL and the inverter INV1 respectively. That is, the mutated voltage at the node N0 or the input port, such as SI32, is sampled by the sampling circuit and the sampling result is branched: the mutated voltage or the sampling result of the voltage is input to the first input terminal of the NOR gate NR, and the sampling result is input to the second input terminal of the NOR gate NR after being delayed by the delay unit DL and inverted by the inverter INV1. In an alternative embodiment, the comparison result of the comparator cm is regarded as the drive signal sg for controlling whether the thyristor device-matching transistor tri-mos is turned on or off. The drive signal sg and the output of the NOR gate NR are input to an AND gate AN to perform a logical AND operation. For example, as shown in the figure, the drive signal sg and the output of the NOR gate NR are respectively input to the two input terminals of the AND gate AN, and the AND gate AN performs a logical AND operation on both the drive signal and the output of the NOR gate.

[0085] See Figure 7, the output of the AND gate AN is coupled to the gate of the electrostatic protection transistor P1 through another inverter IV2 and another capacitor C, whereby at the moment when the electrostatic protection transistor P1 itself is reversely broken down and turned on due to the mutated voltage at the node N0, the electrostatic protection transistor P1 is at least turned off again. The principle of the circuit operation during this period is that if the voltage at the node N0 changes suddenly, or if the voltage jumps, etc., the sampling circuit is sensitive to this sudden change in voltage and generates a single pulse. For example, when the thyristor is suddenly turned on at the node N0 or the input port SI32, the NOR gate NR generates a single pulse due to the sudden drop in the potential at the node N0. The generated single pulse is inverted by the shown inverter IV2, and then the inverted signal is coupled to the gate of the electrostatic protection transistor P1 by the coupling capacitor C that isolates direct current. The single pulse will control the transistor P1 to be instantaneously turned off once. This is an alternative example of at least forcibly turning off the electrostatic protection transistor P1 once at the moment when a voltage drop occurs between the first power supply line and the reference ground E32 and the electrostatic protection transistor is reversely broken down due to the turn-on of the thyristor device. To form a break point of the dark current at the electrostatic protection transistor, so as to cut off the dark current flowing from the first power supply line through the second power supply line, the electrostatic protection transistor and the thyristor device and flowing to the reference ground E32. It can be seen that the electrostatic protection transistor is turned off because of the voltage drop between the first power supply line and the reference ground E32 and the reverse breakdown of the electrostatic protection transistor caused by the sudden turn-on of the thyristor device. The electrostatic protection transistor is reversely broken down and immediately turned off, and the reverse breakdown and re-turn-off of the electrostatic protection transistor are almost instantaneous. If the electrostatic protection transistor can be forcibly turned off once, then a break point of the dark current will be formed at the electrostatic protection transistor, but the thyristor device is still effective: this is because while the direct-through channel of the dark current is cut off, the thyristor device remains conductive and allows the output signal of the first storage unit SO21 to flow from the conductive thyristor device to the reference ground E32 during the cross-layer interaction, thereby suppressing the voltage impact or current impact on the input port of the second storage unit SI32. This is an alternative embodiment of clamping the electrostatic protection transistor configured between the input port of the second storage unit and the second power supply line in the off state.

[0086] See Figure 7 , compared with Figure 6The differences can be reflected in that the driving signal sg and the output of the NOR gate NR are input to the AND gate AN to perform a logical and operation. For example, as shown in the figure, the driving signal sg and the output of the NOR gate NR are respectively input to the two input terminals of the AND gate AN. Based on this, it is required that the AND gate AN perform a logical and operation on both the driving signal and the output of the NOR gate. The AND gate AN will participate in the timing of turning off the single-pulse controlled transistor P1 generated by the NOR gate NR and at least achieve one of the purposes: making the output signal of the first storage unit, such as SO21 of L2-B1, have an ineffective sampling on the voltage impact of the input port SI32 of the second storage unit, such as L3-B2, during the cross-layer interaction for the sampling circuit. Avoid the output signal being mixed and superimposed on the mutated voltage and being sampled as the wrong mutated voltage by the sampling circuit.

[0087] See Figure 7 , in an optional embodiment, the sampling circuit samples the mutated voltage of the input port of the second storage unit. The sampling circuit inputs the voltage of the input port of the second storage unit to the first input terminal of the NOR gate, and inputs the voltage of the input port of the second storage unit to the second input terminal of the NOR gate after delay and inversion through a delay unit and an inverter respectively. The driving signal and the output of the NOR gate are input to the AND gate to perform a logical and operation. The output of the AND gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. At the moment when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage itself, the electrostatic protection transistor is at least turned off again. The logical and operation is used to make the output signal of the first storage unit have an ineffective sampling on the voltage impact of the input port of the second storage unit during the cross-layer interaction for the sampling circuit. It is possible to avoid the output signal of the first storage unit being mixed and superimposed in the mutated voltage and being sampled as the wrong mutated voltage by the sampling circuit. Or prevent dark current (or leakage current) from unexpectedly programming the storage transistors of each storage unit (such as the first storage unit and the second storage unit) in each stacked layer.

[0088] See Figure 7, regarding the logical AND operation, it is used to make the voltage impact of the output signal of the first storage unit on the input port of the second storage unit during cross-layer interaction ineffective for the sampling circuit. For example, if the voltage difference between the first power supply line and the second power supply line exceeds the specification value, the logical high level of the output signal (such as from SO21) will disable the drive signal sg, and the logical low level of the output signal will enable the drive signal sg. Thus, the drive signal is kept continuously and dynamically switched between the disabled and enabled states. Thereby: making the voltage impact of the output signal of the first storage unit on the input port of the second storage unit during cross-layer interaction ineffective for the sampling circuit. For example, when the output signal sends a logical zero value or symbol, the drive signal sg is enabled and the sampling circuit is activated. The voltage of node N0 or SI32 mixed and superimposed with the output signal at this time is ignored or regarded as invalid because it is in the logical zero value (or symbol). Another example is that when the output signal sends a logical one value or symbol, the drive signal sg is disabled and the sampling circuit is latched. The voltage of node N0 or SI32 will not be sampled by the sampling circuit at this time because the sampling circuit is latched and disabled at this time. Even though the voltage of node N0 or SI32 is mixed and superimposed with the logical one value (or symbol) of the output signal at this time, no sampling action will occur. Therefore, it is designed that the logical high level of the output signal disables the drive signal and the logical low level enables the drive signal, keeping the drive signal continuously and dynamically switched between the disabled and enabled states. Furthermore, according to the foregoing scheme, the control limiting conditions of the electrostatic protection transistor P1 are coupled or decoupled with the output signal of the output port SO21 of the first storage unit and the voltage difference between the first power supply line and the second power supply line, so that the inappropriate activation time point of the ESD-P1, that is, the electrostatic protection transistor P1, can be greatly reduced, and the disordered sampling timing is also avoided. These measures are effective ways to avoid the failure of thyristor devices in aspects such as "suppressing voltage impact or current impact caused by output signals".

[0089] See Figure 6 , the illustrated memory is based on 3D flash memory and has a large number of stacked layers, supporting signal cross-layer interaction in the multi-stacked layer structure of the 3D flash memory of the memory. The memory further includes: a first storage unit such as L2-B1 located in any stacked layer such as the L2 layer, and the first storage unit is configured with a first power supply line V21; a second storage unit such as L3-B2 located in a different stacked layer from any stacked layer such as the L3 layer, and the second storage unit such as L3-B2 is also configured with a second power supply line V32 at the same time; a load ld provided between the first power supply line V21 and the second power supply line V32, and a thyristor device such as the illustrated PNPN type thyristor or other types of thyristors used in the industry connected between the input port SI32 of the second storage unit such as L3-B2 and the reference ground E32 of the second storage unit such as L3-B2.

[0090] SeeFigure 6 In the illustrated memory, the voltage sensing value across the load ld and the output signal of the output port of the first memory cell are compared to generate a drive signal sg. The drive signal sg is used to drive a thyristor device triggered by a transistor tri-mos, and the drive signal sg is used to operate the on / off state of the transistor tri-mos associated with the thyristor device.

[0091] See Figure 6 In the illustrated memory, when the voltage difference between the first power supply line and the second power supply lines V21 and V32 exceeds the specification value due to different operating states of the first and second memory cells, the thyristor device is guided to conduct, thereby suppressing the voltage impact or current impact on the input port of the second memory cell such as L3-B2 during cross-layer interaction of the output signal of the first memory cell L2-B1; conversely, when the voltage difference between the first power supply line and the second power supply lines V21 and V32 is lower than the specification value, the thyristor device needs to be disabled, allowing the output signal of SO21 of the first memory cell such as L2-B1 to be interacted to the input port (I / O) of SI32 of the second memory cell L3-B2.

[0092] See Figure 6 In each stack layer, an operational amplifier am and a comparator cm are configured. The operational amplifier is used to calculate the voltage sensing value across the load ld. The output signal of SO21 is coupled to the inverting terminal of the comparator cm using a coupling capacitor such as a MOS capacitor tc, and the output terminal of the operational amplifier am is coupled to the non-inverting terminal of the comparator cm. The comparison result of the comparator cm obtained can be regarded as the drive signal sg for controlling the on / off state of the transistor tri-mos associated with the thyristor device. In addition to using the MOS capacitor tc, a conventional capacitor can also be used as the coupling capacitor. The advantage of using a transistor capacitor here is that the memory originally uses a large number of redundant transistors as substitutes for memory bad points. Therefore, the transistor capacitor can be fabricated using the original redundant transistors of the memory. For example, the transistor gate serves as one pole of the capacitor, and the source-drain substrate of the transistor is connected together as the other pole of the capacitor. As shown in the figure, for example, when the output signal of SO21 of L2-B1 is transmitted to the adjacent upper layer, the signal is led out through a via Via2 to the input port of SI32 of L3-B2. Then, when the output signal is transmitted to the adjacent upper layer, the output signal can be transmitted to the comparator cm configured in the upper layer: the output signal is coupled to the inverting terminal of the comparator cm using a coupling capacitor. Note that the characteristic of the output signal is that it continuously switches between high and low levels. Therefore, the coupling capacitor can couple the output signal with pulsating or AC characteristics to the inverting terminal of the comparator cm.

[0093] See Figure 6, a sampling circuit is configured in each stacked layer. As shown in the figure, the sampling circuit at least includes a NOR gate NR, a delay unit DL, and an inverter IV1. The sampling circuit samples the mutated voltage at the input port of the second storage unit L3-B2. The voltage at the SI32 input port of the second storage unit L3-B2 is directly input to the first input terminal IN1 of the NOR gate NR of the sampling circuit. At the same time, the voltage at the input port of the second storage unit L3-B2 is input to the second input terminal IN2 of the NOR gate NR after passing through the delay unit DL and the inverter IV1. The output of the NOR gate is coupled to the gate of the electrostatic protection transistor P1 through another inverter IV2 and another capacitor C, and can re-shutdown the electrostatic protection transistor P1 again when the electrostatic protection transistor is reversely broken down and turned on due to a mutated voltage (such as at SI32 or node N0). In this example, the sampling circuit and the driving signal are separated from each other.

[0094] See Figure 7 , a sampling circuit is configured in each stacked layer. As shown in the figure, the sampling circuit at least includes a NOR gate NR, a delay unit DL, and an inverter IV1. The sampling circuit samples the mutated voltage at the input port of the second storage unit L3-B2. The voltage at the SI32 input port of the second storage unit L3-B2 is directly input to the first input terminal IN1 of the NOR gate NR of the sampling circuit. At the same time, the voltage at the input port of the second storage unit L3-B2 is input to the second input terminal IN2 of the NOR gate NR after passing through the delay unit DL and the inverter IV1. The output of the NOR gate and the driving signal sg are input to an AND gate AN to perform a Logic AND operation. The output of the AND gate AN is coupled to the gate of the electrostatic protection transistor P1 through another inverter IV2 and a capacitor C, and immediately re-shuts down the electrostatic protection transistor again when the electrostatic protection transistor is reversely broken down and turned on due to the mutated voltage (such as at SI32 or node N0). In this example, the sampling circuit and the driving signal are coupled.

[0095] Through the above description and drawings, typical embodiments of specific structures of specific implementation manners are given. The above application proposes existing preferred embodiments, but these contents are not restrictive. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the appended claims should be regarded as covering all changes and modifications of the true intention and scope of this application. Any and all equivalent scopes and contents within the scope of the claims should be considered to still fall within the intention and scope of this application.

Claims

1. A memory, characterized in that: The memory is based on a three-dimensional flash memory and has a plurality of stacked layers, and supports signal cross-layer interaction in a multi-stacked layer structure of the three-dimensional flash memory of the memory. The memory also includes: A first storage unit located in any stacking layer is provided with a first power line; A second storage unit located in a different stacking layer than any of the stacking layers, and configured with a second power line; A load disposed between the first power line and the second power line; a thyristor device connected between an input port of the second storage unit and a reference ground of the second storage unit; in: The voltage sensed value at both ends of the load and the output signal of the output port of the first storage unit are compared to generate a driving signal, which is used to drive the thyristor device based on transistor triggering, and the driving signal is used to operate whether the matching transistor of the thyristor device is turned on or off; When the voltage difference between the first and second power lines exceeds the specification value due to different working conditions of the first and second storage units, the thyristor device is guided to be turned on to suppress the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit during cross-layer interaction; conversely, when the voltage difference between the first and second power lines is lower than the specification value, the thyristor device is disabled to allow the output signal to interact with the input port of the second storage unit.

2. The memory according to claim 1, characterized in that: An operational amplifier and a comparator are configured in each stacking layer, the voltage sensing value across the load is calculated by the operational amplifier, the output signal is coupled to the inverting terminal of the comparator by a coupling capacitor, and the output terminal of the operational amplifier is coupled to the non-inverting terminal of the comparator; The comparison result of the comparator is regarded as the driving signal for controlling whether the transistor is turned on or off.

3. The memory according to claim 1, characterized in that: A sampling circuit is configured in each stacking layer, and the sampling circuit includes a NOR gate, a delay unit, and an inverter; The sampling circuit samples the sudden voltage of the input port of the second storage unit, the voltage of the input port of the second storage unit is directly input to the first input end of the NOR gate, and the voltage of the input port of the second storage unit is input to the second input end of the NOR gate after passing through the delay unit and the inverter; The output of the NOR gate is coupled to the gate of the electrostatic protection transistor through another inverter and a capacitor. When the electrostatic protection transistor is reversely broken down and turned on due to a sudden voltage change, the electrostatic protection transistor is turned off again.

4. The memory according to claim 1, characterized in that: A sampling circuit is configured in each stacking layer, and the sampling circuit includes a NOR gate, a delay unit, and an inverter; The sampling circuit samples the sudden voltage of the input port of the second storage unit, the voltage of the input port of the second storage unit is input to the first input end of the NOR gate, and the voltage of the input port of the second storage unit is input to the second input end of the NOR gate after passing through the delay unit and the inverter; The output of the NOR gate and the driving signal are input to an AND gate to perform a logic AND operation. The output of the AND gate is coupled to the gate of the ESD protection transistor through another inverter and a capacitor. When the ESD protection transistor is reversely broken down and turned on due to a sudden voltage change, the ESD protection transistor is turned off again.

5. The memory according to claim 1, characterized in that: When the voltage difference between the first and second power lines exceeds a specification value, the logic high level of the output signal disables the drive signal and the logic low level of the output signal enables the drive signal, so that the drive signal is set to continuously and dynamically switch between the disabled and enabled states; When the voltage difference between the first and second power lines is lower than a specified value, both the logic high level and the logic low level of the output signal disable the driving signal.

6. The memory according to claim 1, characterized in that: Conditions under which the thyristor device enters the on state based on the voltage difference between the first and second power supply lines exceeding the specification value: The electrostatic protection transistor configured between the input port of the second storage unit and the second power line is clamped in an off state to cut off the dark current flowing from the first power line through the second power line, the electrostatic protection transistor, the thyristor device and to the reference ground.

7. The memory according to claim 6, characterized in that: At the moment when a voltage drop occurs between the first power line and the reference ground, and when the electrostatic protection transistor breaks down in reverse due to the turning-on of the thyristor device, the electrostatic protection transistor is forced to be turned off at least once to form a breakpoint of the dark current at the electrostatic protection transistor, but without affecting the original function of the thyristor device for suppressing the voltage or current impact of the output signal of the first storage unit on the input port of the second storage unit.

8. The memory according to claim 1, characterized in that: The thyristor device is a thyristor device based on a PNPN semiconductor structure.

9. The memory according to claim 8, characterized in that: The supporting transistor for triggering the thyristor device is an NMOS type transistor.

10. The memory according to claim 1, characterized in that: The load is an active load or a passive load.

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