NTP time synchronization device

Abstract

The NTP time synchronization device provided by the utility model comprises a core taming board and a rubidium atomic clock, the core taming board is provided with an ARM processor, a level conversion circuit, a first DB-9 interface and a rubidium clock output circuit, and the rubidium atomic clock comprises a second DB-9 interface and an SMA radio frequency output end. A data transmission pin of the ARM processor is correspondingly and electrically connected with the first DB-9 interface through the level conversion circuit, and a first input / output pin and a second input / output pin of the ARM processor are correspondingly and electrically connected with a locking state indication end and a holding state indication end of the first DB-9 interface respectively; the first DB-9 interface and the second DB-9 interface are electrically connected one by one, and the SMA radio frequency output end is electrically connected with the rubidium clock output circuit. According to the utility model, the ARM processor controls the rubidium atomic clock to output the standard IPPS signal to the rubidium clock output circuit of the core taming board, so that the core taming board uses the standard IPPS signal to carry out time synchronization of a computer.

Description

Technical Field

[0001] The utility model relates to the technical field of timing, and particularly relates to an NTP time synchronization device. Background Art

[0002] With the continuous development and progress of industry, China has entered the information age. Ensuring time accuracy is an important part of informatization. The rapid development of time service technology and network technology has continuously increased the precision requirements for time in all walks of life. The computer system time in the domestic market is determined by the crystal oscillator and clock chip on the motherboard. The crystal oscillator can generate an alternating current signal with a certain frequency, which can convert direct current electrical energy into alternating current electrical energy with a certain frequency. When designing the circuit, an external clock circuit for the crystal oscillator needs to be designed, generally an amplifier feedback circuit, and thus a crystal oscillator is formed. The oscillation frequency accuracy of the crystal oscillator determines the accuracy of the clock, and factors such as temperature and aging will affect the frequency of the crystal oscillator, thereby affecting the timing accuracy and causing clock errors. Long-term accumulation will cause large time errors. Therefore, it is impossible to achieve a precise clock using the clock of the computer itself, and time synchronization between computers needs to be achieved through time synchronization devices.

[0003] (1) Most foreign time synchronization servers use GPS time signals and are widely used in many fields. Most synchronization device manufacturers provide such devices. Well-known manufacturers include GlobalTime and Symmetricom, etc. From large-scale, fully interfaced time synchronization servers to easily installed and mobile time synchronization service modules, the product line is very complete. However, there is a problem of relatively high price.

[0004] (2) There are not many domestic time synchronization service manufacturers. Most of them are integrators, power equipment manufacturers or traditional clock manufacturers that have transformed. There are problems such as insufficient technical accumulation and technical content, low precision, and few adaptable time systems.

[0005] In a new time synchronization design scheme, it is necessary to establish, generate and output the local time reference using the rubidium atomic frequency standard frequency source signal. Therefore, there is an urgent need for a design circuit to connect the processor and the rubidium atomic clock. Summary of the Utility Model

[0006] In order to solve the above problems of the prior art, the utility model provides an NTP time synchronization device to realize the connection between the processor and the rubidium atomic clock.

[0007] To achieve the above object, the technical solution adopted by the utility model is as follows:

[0008] In a first aspect, the present utility model provides an NTP time synchronization device, which includes a core taming board and a rubidium atomic clock. An ARM processor, a level conversion circuit, a first DB-9 interface, and a rubidium clock output circuit are provided on the core taming board. The rubidium atomic clock includes a second DB-9 interface and an SMA radio frequency output terminal. A data transmission pin of the ARM processor is electrically connected to the first DB-9 interface through the level conversion circuit. A first input / output pin and a second input / output pin of the ARM processor are electrically connected to a lock status indication terminal and a hold status indication terminal of the first DB-9 interface respectively;

[0009] The first DB-9 interface and the second DB-9 interface are electrically connected one by one, and the SMA radio frequency output terminal is electrically connected to the rubidium clock output circuit.

[0010] The beneficial effect of the present utility model is that the level conversion circuit is used to ensure the same level between the level conversion circuit and the rubidium atomic clock, so that the ARM processor controls the rubidium atomic clock to output a standard IPPS signal to the rubidium clock output circuit of the core taming board, so that the core taming board uses the standard IPPS signal to synchronize the time of the computer.

[0011] Optionally, the data transmission pins are the third input / output pin and the fourth input / output pin of the ARM processor, and the level conversion circuit includes a level conversion chip;

[0012] The third input / output pin and the fourth input / output pin are respectively and electrically connected to a first transmission channel input pin and a first reception channel output pin of the level conversion chip. A first transmission channel output pin and a first reception channel input pin of the level conversion chip are respectively and electrically connected to a transmission data terminal and a reception data terminal of the first DB-9 interface.

[0013] Optionally, a pulse input circuit is further included. The pulse input circuit includes a first clock buffer. An input clock pin of the clock buffer is used to receive an external IPPS signal, and an output pin of the clock buffer is electrically connected to a pulse input terminal of the first DB-9 interface.

[0014] Optionally, the rubidium clock output circuit includes a second clock buffer. The SMA radio frequency output terminal is electrically connected to an input clock pin of the second clock buffer, and an output pin of the second clock buffer is used to output a standard IPPS signal.

[0015] Optionally, the level conversion chip is ADM3232EARNZ.

[0016] Optionally, the ARM processor is GD32F407VGT6. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the framework of the NTP time synchronization device according to an embodiment of the present utility model;

[0018] Figure 2 It is a circuit schematic diagram of the ARM processor, level conversion circuit, first DB-9 interface and pulse input circuit involved in an embodiment of the present utility model;

[0019] Figure 3 It is a schematic diagram of the rubidium clock output circuit involved in an embodiment of the present utility model.

[0020] Explanation of reference numerals:

[0021] 1. Display and control board; 2. Power distribution board; 3. Multi-source input board; 4. Core taming board; 5. Rubidium atomic clock; 6. Serial port 10M transfer board; 7. Time code board; 8. Network time service board. Specific implementation manners

[0022] In order to better understand the above technical solution, the exemplary embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present utility model are shown in the drawings, it should be understood that the present utility model can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present utility model can be understood more clearly and thoroughly, and the scope of the present utility model can be fully conveyed to those skilled in the art.

[0023] Embodiment 1

[0024] Please refer to Figure 2 and Figure 3 , the NTP time synchronization device includes a core taming board 4 and a rubidium atomic clock 5. Among them, an ARM processor U1, a level conversion circuit, a first DB-9 interface DB1, a pulse input circuit and a rubidium clock output circuit are provided on the core taming board 4. The rubidium atomic clock 5 includes a second DB-9 interface and an SMA radio frequency output terminal. The first DB-9 interface DB1 and the second DB-9 interface are electrically connected one by one. Therefore, nine pins are correspondingly provided on both of them, which are a pulse input terminal, a lock status indication terminal, a hold status indication terminal, a data sending terminal, a data receiving terminal, a positive power supply terminal, a frequency adjustment section and two ground terminals.

[0025] Among them, the data transmission pins of the ARM processor U1 are electrically connected to the first DB-9 interface DB1 through a level conversion circuit. Among them, the data transmission pins are the third input / output pin PB10 and the fourth input / output pin PB11 of the ARM processor U1, and the level conversion circuit includes a level conversion chip U2; the third input / output pin PB10 and the fourth input / output pin PB11 are respectively and electrically connected to the first transmission channel input pin T1_IN and the first reception channel output pin R1_OUT of the level conversion chip U2, and the first transmission channel output pin T1_OUT and the first reception channel input pin R1_IN of the level conversion chip U2 are respectively and electrically connected to the transmit data terminal RS232_RX_OEM and the receive data terminal RS232_TX_OEM of the first DB-9 interface DB1. Among them, data is sent or received between the ARM processor U1 and the first DB-9 interface DB1 through the RS-232 interface.

[0026] Among them, the first input / output pin PD9 and the second input / output pin PD8 of the ARM processor U1 are respectively and electrically connected to the lock status indicator terminal TLOCK and the hold status indicator terminal LOOP_LOCK of the first DB-9 interface DB1.

[0027] Among them, the pulse input circuit includes a first clock buffer U3. The input clock pin ICLK of the first clock buffer U3 is used to receive an external IPPS signal, and the output pin Q0 of the first clock buffer U3 is electrically connected to the pulse input terminal of the first DB-9 interface DB1.

[0028] Among them, the SMA radio frequency output terminal is electrically connected to the rubidium clock output circuit. The rubidium clock output circuit includes a second clock buffer U4. The SMA radio frequency output terminal is electrically connected to the input clock pin ICLK of the second clock buffer U4, and the output pin Q1 of the second clock buffer U4 is used to output a standard IPPS signal. That is, Figure 3 the interface P1 in is used to be electrically connected to the SMA radio frequency output terminal, and the terminal where the interface name is Rb_1PPS_OUT is used to output a standard IPPS signal.

[0029] In this embodiment, the ARM processor U1 is GD32F407VGT6, the level conversion chip U2 is ADM3232EARNZ, the first clock buffer U3 and the second clock buffer U4 are ICS553 one-to-four buffers, and the rubidium atomic clock 5 is an R2D miniature atomic clock.

[0030] In this embodiment, the peripheral circuits of each chip can use existing technologies, so they will not be described one by one. For example, the function of a capacitor is basically to filter out interference signals in the circuit, and the function of a resistor is basically to adjust the potential at different positions in the circuit to prevent the impact of changes in the magnitude of the current in the circuit on the power supply circuit, and effectively eliminate the parasitic coupling between circuit networks.

[0031] As Figures 2 to 3 shown in the circuit, at the intersections with connection relationships, there are solid circles for marking, that is, there is no solid circle at the intersection means there is no connection relationship. At the same time, in the attached drawings, the same names outside the chip are connected together. For example, Figure 2 in [diagram], the TLOCK of the ARM processor U1 and the TLOCK of the first DB-9 interface DB1 are connected to each other, which is common sense in the circuit diagram.

[0032] Referring to Figure 1 it can be seen that for the overall framework description of the NTP time synchronization device in this embodiment, it further includes a display control board 1, a power distribution board 2, a multi-source input board 3, a serial port 10M transfer board 6, a time code board 7, and a network time service board 8. Among them, the display control board 1 is designed in combination with buttons and a display screen to realize human-computer interaction functions such as setting information input and working status display. The power distribution board 2 is used to provide the power required for the entire device. The multi-source input board 3 is responsible for processing the output signals of each board and the device input signals, and forwarding the processed signals to the core taming board 4. The serial port 10M transfer board 6 converts the 10MHz signal input by the core taming board 4 through the multi-source input board 3 into a serial port signal. The time code board 7 performs functions such as 1PPS, B-code signal, level conversion, input / output control, and bus transmission control on the 1PPS signal and B-code output by the core taming board 4. The network time service board 8 receives the 10MHz signal from the 4-channel serial port 10M transfer board 6 and uses the NTP standard network time service protocol to provide it to computers or other terminal devices with time service requirements in the network. In this way, the multi-channel serial port 10M transfer board 6 can output multi-channel serial port signals, and the corresponding multi-channel network time service boards 8 can also output multi-channel NTP signals. The core taming board 4 outputs a 10MHz signal outward, and the time code board 7 can output 1PPS signals, B(AC) code, and B(DC) code, so that NTP time service signals, 1PPS+TOD, 10MHz, 1PPS, B(AC), B(DC) and other common time signals can be output, and a wider range of adaptable time systems can be achieved.

[0033] Thus, in this embodiment, the ARM processor controls the rubidium atomic clock 5 to output a standard IPPS signal to the rubidium clock output circuit of the core taming board 4, so that the core taming board 4 uses the standard IPPS signal for computer time synchronization, realizing the connection between the ARM processor and the rubidium atomic clock 5, and the accuracy can reach 10 - 100ms.

[0034] In the description of the present utility model, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality of" means two or more, unless otherwise specifically defined.

[0035] In the present utility model, unless otherwise clearly defined and limited, the terms such as "mounted", "connected", "connected to", "fixed" and the like shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium; it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0036] In the present utility model, unless otherwise clearly defined and limited, when the first feature is "on" or "under" the second feature, it may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, when the first feature is "above", "over" and "on top of" the second feature, it may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. When the first feature is "under", "beneath" and "underneath" the second feature, it may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0037] In the description of this specification, the descriptions of the terms "an embodiment", "some embodiments", "embodiments", "examples", "specific examples" or "some examples", etc. refer to that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0038] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present utility model.

Claims

1. NTP time synchronization device, characterized in that: It comprises a core taming board and a rubidium atomic clock, wherein the core taming board is provided with an ARM processor, a level conversion circuit, a first DB-9 interface and a rubidium clock output circuit, the rubidium atomic clock comprises a second DB-9 interface and an SMA radio frequency output terminal, a data transmission pin of the ARM processor is electrically connected to the first DB-9 interface via the level conversion circuit, and a first input-output pin and a second input-output pin of the ARM processor are electrically connected to a locking state indicating terminal and a holding state indicating terminal of the first DB-9 interface respectively; The first DB-9 interface and the second DB-9 interface are electrically connected one by one, and the SMA radio frequency output end is electrically connected to the rubidium clock output circuit.

2. The NTP time synchronization device according to claim 1, characterized in that: The data transmission pins are the third input / output pin and the fourth input / output pin of the ARM processor, and the level conversion circuit includes a level conversion chip; The third input / output pin and the fourth input / output pin are electrically connected to the first transmitting channel input pin and the first receiving channel output pin of the level conversion chip respectively, and the first transmitting channel output pin and the first receiving channel input pin of the level conversion chip are electrically connected to the transmitting data end and the receiving data end of the first DB-9 interface respectively.

3. The NTP time synchronization device according to claim 2, characterized in that: It also includes a pulse input circuit, which includes a first clock buffer, an input clock pin of the first clock buffer is used to receive an external IPPS signal, and an output pin of the first clock buffer is electrically connected to the pulse input end of the first DB-9 interface.

4. The NTP time synchronization device according to claim 2, characterized in that: The rubidium clock output circuit includes a second clock buffer, the SMA radio frequency output end is electrically connected to an input clock pin of the second clock buffer, and an output pin of the second clock buffer is used to output a standard IPPS signal.

5. The NTP time synchronization device according to claim 2, characterized in that: The level conversion chip is ADM3232EARNZ.

6. The NTP time synchronization device according to claim 1, characterized in that: The ARM processor is GD32F407VGT6.

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