Fan-out wafer level packaging unit

Abstract

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, a second dielectric layer, a plurality of first conducting circuits, a third dielectric layer, a fourth dielectric layer and an outer protective layer, wherein each first conductive connection circuit is manufactured and formed on the second surface of each bare crystal by using a technology of filling metal paste into the groove and then grinding and forming the conductive connection circuit; wherein each second conductive connection circuit is manufactured and formed on the second dielectric layer and the plurality of first conductive connection circuits by utilizing a technology of filling metal paste into the groove and then grinding and forming the conductive connection circuit; wherein each bare crystal can be electrically connected with the outside through each welding pad around the chip area on the second surface, so as to solve the problems that the existing fan-out packaging technology is easy to generate higher manufacturing cost and is not beneficial to environmental protection when each conducting circuit is manufactured.

Description

Technical Field

[0001] The utility model relates to a chip packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art

[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most critical. Because the conductive lines in the RDL can cause XY-plane electrical extension and interconnection of multiple pads on the bare die, enabling the formation of a relatively dispersed plurality of pads around the bare die, thereby effectively improving the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating XY-plane electrical extension and interconnection is the most crucial for the production of each conductive line in the RDL. However, the forming method of each conductive line in the RDL technology applied in the existing FOWLP packaging technology is to use electroless plating forming technology or electroplating forming technology for production. In this way, in addition to the relatively high material cost and production cost, the existing technology processes also do not meet or are not conducive to environmental protection requirements.

[0004] In addition, when FOWLP needs to meet the circuit layout of multiple applications, generally two or more redistribution layers are set in the FOWLP and integrated through the RDL to form a multi-chip type fan-out wafer-level packaging unit. At this time, the demand for the design space of each conductive line in the RDL of the FOWLP will relatively increase, and the production technology of each conductive line in the RDL is also relatively more critical. Summary of the Utility Model

[0005] The main object of the utility model is to provide a fan-out wafer-level packaging unit, which includes a carrier plate, at least one bare die, a first dielectric layer, a second dielectric layer, a plurality of first conductive lines, a third dielectric layer, a fourth dielectric layer, and an outer protective layer; wherein each first conductive line is formed on the second surface of each bare die by using the technology of first injecting metal paste into a groove and then grinding to form a conductive line; wherein each second conductive line is formed on the second dielectric layer and the plurality of first conductive lines by using the technology of first injecting metal paste into a groove and then grinding to form a conductive line; wherein each bare die can be externally electrically connected through the pads around the chip area on the second surface, effectively solving the problems that the existing fan-out packaging technology is prone to high manufacturing costs and is not conducive to environmental protection when manufacturing each conductive line.

[0006] To achieve the above object, the present utility model provides a fan-out wafer-level packaging unit, which includes a carrier plate, at least one bare die, a first dielectric layer, a second dielectric layer, a plurality of first connection lines, a third dielectric layer, a fourth dielectric layer, and an outer protective layer; wherein each of the bare dies is separated from a wafer, each of the bare dies is disposed on the carrier plate, each of the bare dies has a first surface and a second surface opposite thereto, the first surface of each of the bare dies is fixedly disposed on the carrier plate, a plurality of pads are provided on the second surface of each of the bare dies, and the vertical chip area of the second surface is defined as a chip area; wherein the first dielectric layer is disposed on the carrier plate and the second surface of each of the bare dies, the first dielectric layer has a plurality of first grooves formed by extending horizontally, and a plurality of the pads of each of the bare dies are exposed to the outside through the plurality of first grooves; wherein the second dielectric layer is disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves formed by extending horizontally, and each of the second grooves communicates with each of the first grooves; wherein each of the first connection lines is composed of metal paste filled in the plurality of first grooves and the plurality of second grooves, and each of the first connection lines is electrically connected to each of the pads of each of the bare dies; wherein the third dielectric layer is disposed on the second dielectric layer, the third dielectric layer has a plurality of third grooves formed by extending horizontally, and each of the third grooves communicates with each of the second grooves; wherein the fourth dielectric layer is disposed on the third dielectric layer, the fourth dielectric layer has a plurality of fourth grooves formed by extending horizontally, and each of the fourth grooves communicates with each of the third grooves; wherein each of the second connection lines is composed of metal paste filled in the plurality of third grooves and the plurality of fourth grooves, and each of the second connection lines is electrically connected to each of the first connection lines; wherein the outer protective layer is disposed on the fourth dielectric layer, the outer protective layer has a plurality of openings and at least two of the openings are located around the chip area on the second surface of each of the bare dies, and each of the second connection lines is exposed to the outside through the plurality of openings to form a solder pad in each of the openings; wherein each of the bare dies can be electrically connected to the outside in sequence through each of the pads, each of the first connection lines, each of the second connection lines, and the plurality of solder pads located around the chip area on the second surface of each of the bare dies, thereby forming the fan-out wafer-level packaging unit.

[0007] In a preferred embodiment of the present utility model, the carrier plate includes a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate.

[0008] In a preferred embodiment of the present utility model, the metal paste constituting each of the first connection lines and each of the second connection lines includes silver paste, nano silver paste, copper paste, or nano copper paste.

[0009] In a preferred embodiment of the present utility model, the first surface of each of the bare dies is further disposed on the carrier by using a die attach film (DAF).

[0010] In a preferred embodiment of the present utility model, a solder ball is further disposed on each of the openings, and each of the solder balls can be electrically connected to each of the pads in a plurality of the openings; wherein the fan-out wafer-level packaging unit can be disposed on a printed circuit board (PCB) in an electrically connected manner by using each of the solder balls.

[0011] The present utility model further provides a fan-out wafer-level packaging unit, which includes a carrier plate, at least two bare dies, a first dielectric layer, a second dielectric layer, a plurality of first connection lines, a third dielectric layer, a fourth dielectric layer, and an outer protection layer. Each of the bare dies is separated from the same wafer or different wafers. Each of the bare dies is arranged side by side on the carrier plate in parallel and at intervals. Each of the bare dies has a first surface and a second surface opposite thereto. The first surface of each of the bare dies is fixedly arranged on the carrier plate. A plurality of chip pads are provided on the second surface of each of the bare dies, and the vertical chip area of the second surface is defined as a chip area. The first dielectric layer is arranged on the carrier plate and the second surface of each of the bare dies. The first dielectric layer has a plurality of first grooves formed by extending horizontally. Each of the chip pads of each of the bare dies is exposed to the outside through the plurality of first grooves. The second dielectric layer is arranged on the first dielectric layer. The second dielectric layer has a plurality of second grooves formed by extending horizontally. Each of the second grooves communicates with each of the first grooves. Each of the first connection lines is composed of metal paste filled in the plurality of first grooves and the plurality of second grooves. Each of the first connection lines is electrically connected to the plurality of chip pads of each of the bare dies. The third dielectric layer is arranged on the second dielectric layer. The third dielectric layer has a plurality of third grooves formed by extending horizontally. Each of the third grooves communicates with each of the second grooves. The fourth dielectric layer is arranged on the third dielectric layer. The fourth dielectric layer has a plurality of fourth grooves formed by extending horizontally. Each of the fourth grooves communicates with each of the third grooves. Each of the second connection lines is composed of metal paste filled in the plurality of third grooves and the plurality of fourth grooves. Each of the second connection lines is electrically connected to each of the first connection lines. The outer protection layer is arranged on the fourth dielectric layer. The outer protection layer has a plurality of openings, and at least two of the openings are located around the chip area on the second surface of each of the bare dies. Each of the second connection lines is exposed to the outside through the plurality of openings to form a solder pad in each of the openings. Each of the bare dies can be electrically connected to the outside in sequence through each of the chip pads, each of the first connection lines, each of the second connection lines, and the plurality of solder pads located around the chip area on the second surface of each of the bare dies, thereby forming the fan-out wafer-level packaging unit.

[0012] In a preferred embodiment of the present utility model, the carrier plate includes a silicon carrier plate, a glass carrier plate, or a ceramic carrier plate.

[0013] In a preferred embodiment of the present utility model, the metal paste constituting each of the first connection lines and each of the second connection lines includes silver paste, nano silver paste, copper paste, or nano copper paste.

[0014] In a preferred embodiment of the present utility model, the first surface of each die is further disposed on the carrier by using a chip bonding film.

[0015] In a preferred embodiment of the present utility model, a solder ball is further provided on each opening, and each solder ball can be electrically connected to each solder pad in a plurality of the openings; wherein the fan-out wafer-level packaging unit can be disposed on a printed circuit board in an electrically connected manner by using each solder ball. Description of the Drawings

[0016] Figure 1 It is a schematic side cross-sectional view of an embodiment in which the fan-out wafer-level packaging unit of the present utility model is disposed on a printed circuit board.

[0017] Figure 2 It is a schematic side cross-sectional view of the die of the present utility model disposed on the carrier.

[0018] Figure 3 It is a schematic side cross-sectional view of the first dielectric layer of the present utility model disposed on the second surfaces of the carrier and the die.

[0019] Figure 4 It is a schematic side cross-sectional view of the second dielectric layer of the present utility model disposed on the first dielectric layer.

[0020] Figure 5 It is a schematic side cross-sectional view of the first groove and the second groove of the present utility model filled with metal paste.

[0021] Figure 6 is Figure 5 a schematic side cross-sectional view of grinding the metal paste higher than the surface of the second dielectric layer.

[0022] Figure 7 It is a schematic side cross-sectional view of the third dielectric layer of the present utility model disposed on the second dielectric layer.

[0023] Figure 8 It is a schematic side cross-sectional view of the fourth dielectric layer of the present utility model disposed on the third dielectric layer.

[0024] Figure 9 It is a schematic side cross-sectional view of the first groove and the second groove of the present utility model filled with metal paste.

[0025] Figure 10 is Figure 9 a schematic side cross-sectional view of grinding the metal paste higher than the surface of the fourth dielectric layer.

[0026] Figure 11 It is a schematic side cross-sectional view of the outer protective layer of the present utility model forming a plurality of openings.

[0027] Figure 12This is a schematic side cross-sectional view of an embodiment of the fan-out wafer-level packaging unit of the present utility model with solder balls.

[0028] Figure 13 This is a schematic side cross-sectional view of another embodiment of the fan-out wafer-level packaging unit of the present utility model with solder balls.

[0029] Figure 14 This is a schematic side cross-sectional view of another embodiment of the fan-out wafer-level packaging unit of the present utility model disposed on a printed circuit board.

[0030] Description of reference numerals: 1 - fan-out wafer-level packaging unit; 1a - chip area; 10 - carrier plate; 20 - bare die; 21 - first surface; 22 - second surface; 23 - pad; 30 - first dielectric layer; 31 - first groove; 40 - second dielectric layer; 41 - second groove; 50 - first conductive line; 50a - metal paste; 60 - third dielectric layer; 61 - third groove; 70 - fourth dielectric layer; 71 - fourth groove; 80 - second conductive line; 80a - metal paste; 81 - solder pad; 90 - outer protective layer; 91 - opening; 100 - chip bonding film; 110 - solder ball; 2 - printed circuit board. Detailed Description of the Invention

[0031] In conjunction with the drawings, the structure and its technical features of the present utility model will be described in detail below. Each drawing is only used to illustrate the structural relationship and related functions of the present utility model. Therefore, the dimensions of each component in each drawing are not drawn according to the actual proportion and are not used to limit the present utility model.

[0032] Reference Figure 1 and Figure 14 , the present utility model provides a fan-out wafer-level packaging unit 1, which includes a carrier plate 10, at least one bare die (Die) 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of first conductive lines 50, a third dielectric layer 60, a fourth dielectric layer 70, a plurality of second conductive lines 80, and an outer protective layer 90.

[0033] Each bare die 20 is separated from a wafer (Wafer). Each bare die 20 is disposed on the carrier plate 10. Each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is fixedly disposed on the carrier plate 10. A plurality of pads 23 are provided on the second surface 22 of each bare die 20, and the vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 2 shown. In Figure 2 , two pads 23 of each bare die 20 are taken as an example for illustration, but it is not used to limit the present utility model.

[0034] The first dielectric layer 30 is disposed on the second surface 22 of the carrier board 10 and each bare die 20. The first dielectric layer 30 has a plurality of first grooves 31 formed by extending in the horizontal direction, as Figure 3 shown; wherein each pad 23 of each bare die 20 is exposed to the outside through each first groove 31, as Figure 3 shown.

[0035] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 formed by extending in the horizontal direction. Each second groove 41 communicates with each first groove 31, as Figure 4 shown.

[0036] Each first connection line 50 is composed of a metal paste 50a filled in each first groove 31 and each second groove 41. Each first connection line 50 is electrically connected to each pad 23 of each bare die 20, as Figure 6 shown.

[0037] The third dielectric layer 60 is disposed on the second dielectric layer 40. The third dielectric layer 60 has a plurality of third grooves 61 formed by extending in the horizontal direction. Each third groove 61 communicates with each second groove 41, as Figure 7 shown.

[0038] The fourth dielectric layer 70 is disposed on the third dielectric layer 60. The fourth dielectric layer 70 has a plurality of fourth grooves 71 formed by extending in the horizontal direction. Each fourth groove 71 communicates with each third groove 61, as Figure 8 shown.

[0039] Each second connection line 80 is composed of a metal paste 80a filled in each third groove 61 and each fourth groove 71. Each second connection line 80 is electrically connected to each first connection line 50, as Figure 10 shown.

[0040] The outer protective layer 90 is disposed on the fourth dielectric layer 70. The outer protective layer 90 has a plurality of openings 91, and at least two of the openings 91 are located around the chip area 1a on the second surface 22 of each bare die 20, as Figure 11 shown; wherein each second connection line 80 is exposed to the outside through each opening 91 to form a pad 81 in each opening 91, as Figure 11 and Figure 13 shown. In Figure 11 the example of the outer protective layer 90 having eight openings 91 is used for illustration, but it is not intended to limit the present invention.

[0041] Each bare die 20 can be electrically connected externally in sequence via each pad 23, each first connection line 60, each second connection line 80, and each pad 81 around the chip region 1a on the second surface 22 of each bare die 20, thereby forming the fan-out wafer-level packaging unit 1, as Figure 11 and Figure 13 shown.

[0042] The process of manufacturing the fan-out wafer-level packaging unit 1 may include the following steps, but is not limited thereto:

[0043] Step S1: Provide a carrier 10, as Figure 2 shown.

[0044] Step S2: Dispose a plurality of bare dies 20 separated from the same wafer or different wafers on the carrier 10 at intervals, as Figure 2 shown; wherein each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is disposed on the carrier 10. A plurality of pads 23 are provided on the second surface 22 of each bare die 20, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as Figure 2 shown.

[0045] Step S3: Use the technology of first filling metal paste into the grooves and then grinding and forming connection lines to form a plurality of first connection lines 50 on the second surface 22 of each bare die 20: First, lay a first dielectric layer 30 on the carrier 10 and the second surface 22 of each bare die 20, and form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, so that each pad 23 of each bare die 20 can be exposed externally through each first groove 31, as Figure 3 shown, then lay a second dielectric layer 40 on the first dielectric layer 30, and form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, so that each second groove 41 can communicate with each first groove 31, as Figure 4 shown, then fill metal paste 50a into each first groove 31 and each second groove 41, and make the thickness of the metal paste 50a higher than the surface of the second dielectric layer 40, as Figure 5 shown, and finally grind the metal paste 50a higher than the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of the first connection lines 50, as Figure 6 shown.

[0046] Step S4: Fabricate a plurality of second conductive lines 80 on the second dielectric layer 40 and the plurality of first conductive lines 50 by using a technique of first filling a metal paste into the grooves and then grinding and forming the conductive lines: First, lay a third dielectric layer 60 on the second dielectric layer 40, and form a plurality of third grooves 61 extending horizontally on the third dielectric layer 60 so that each third groove 61 can communicate with each second groove 41, as Figure 7 shown. Then, lay a fourth dielectric layer 70 on the third dielectric layer 60, and form a plurality of fourth grooves 71 extending horizontally on the fourth dielectric layer 70 so that each fourth groove 71 can communicate with each third groove 61, as Figure 8 shown. After that, fill the metal paste 80a into each third groove 61 and each fourth groove 71, and make the thickness of the metal paste 80a higher than the surface of the fourth dielectric layer 70, as Figure 9 shown. Finally, grind the metal paste 80a higher than the surface of the fourth dielectric layer 70 so that the surface of the metal paste 80a is flush with the surface of the fourth dielectric layer 70 to form a plurality of the second conductive lines 80, as Figure 10 shown; wherein each second conductive line 80 is electrically connected to each first conductive line 50, as Figure 10 shown.

[0047] Step S5: Lay an outer protective layer 90 on the fourth dielectric layer 70, as Figure 11 shown.

[0048] Step S6: Form a plurality of openings 91 in the outer protective layer 90 and make at least one of the openings 91 formed around the chip area 1a on the second surface 22 of each bare die 20, so that each second conductive line 80 can be exposed to the outside through each opening 91 to form a solder pad 81 in each opening 91, as Figure 11 shown.

[0049] Step S7: Perform a dicing operation and dice to form a plurality of fan-out wafer-level packaging units 1 with one package having at least one of the bare dies 20 as a unit, as Figure 13 shown.

[0050] The manufacturing process from step S3 to step S4 in the above process for manufacturing the fan-out wafer-level packaging unit 1 can be regarded as the key steps for fabricating the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1. Among them, in step S3, a plurality of the first conductive lines 50 are formed on the second surface 22 of each die 20 by using a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. In step S4, a plurality of the second conductive lines 80 are formed on the second dielectric layer 40 and the plurality of the first conductive lines 50 by using the same technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. Since steps S3 to S4 are all processes that can be precisely implemented easily, the manufacturing process is relatively simplified. It is sufficient to enable each of the first conductive lines 50 and each of the second conductive lines 80 in the redistribution layer to generate XY-plane electrical extension and interconnection effects, and at the same time, the fabricated fan-out wafer-level packaging unit 1 can still maintain or achieve a certain degree of thinness, lightness, shortness, and small size. In addition, in the case where there are at least two dies 20 in the fan-out wafer-level packaging unit 1, it can still maintain or achieve a certain degree of thinness, lightness, shortness, and small size.

[0051] Reference Figure 2 , the carrier plate 10 includes a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate, which is conducive to diversified product development and applications.

[0052] Reference Figure 6 , the metal paste 50a constituting each of the first conductive lines 50 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has characteristics such as low cost, high conductivity, and the ability to sinter at low temperature. However, since the nano-silver paste material is a common material in the art, it will not be elaborated here.

[0053] Reference Figure 10 , the metal paste 80a constituting each of the second conductive lines 80 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has characteristics such as low cost, high conductivity, and the ability to sinter at low temperature. However, since the nano-silver paste material is a common material in the art, it will not be elaborated here.

[0054] Reference Figure 2 , the first surface 11 of each die 20 is further disposed on the carrier plate 10 by using a die attach film (DAF), but is not limited thereto.

[0055] Reference Figure 12 and Figure 13 , a solder ball 110 is further provided on each opening 91, but is not limited thereto. Each solder ball 110 can be electrically connected to each pad 81 in each opening 91.

[0056] ReferenceFigure 1 and Figure 14 , the fan-out wafer-level packaging unit 1 can be electrically connected to a printed circuit board (PCB) 2 through each solder ball 110.

[0057] The fan-out wafer-level packaging unit 1 of the present utility model can further include at least two bare dies 20, as Figures 1 to 11 disclosed herein, which can be regarded as one of the embodiments of the fan-out wafer-level packaging unit 1 of this case; wherein at least two bare dies 20 are each divided from the same wafer or different wafers, and each bare die 20 is arranged side by side in parallel and at intervals on the carrier 10. Each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is fixedly arranged on the carrier 10, and a plurality of pads 23 are provided on the second surface 22 of each bare die 20. And the vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 11 shown; when each bare die 20 is divided from the same wafer, each bare die 20 has the same specifications, performance, or functions to be achieved, but this is not limited; when each bare die 20 is divided from different wafers, it is beneficial to increase the diversified applications of the product, and each bare die 20 can have different specifications, performance, or functions to be achieved, but this is not limited.

[0058] When the fan-out wafer-level packaging unit 1 further includes at least two bare dies 20, the process of manufacturing the fan-out wafer-level packaging unit 1 can include the following steps, but is not limited thereto:

[0059] Step S1: Provide a carrier 10, as Figure 2 shown.

[0060] Step S2: Arrange a plurality of bare dies (Die) divided from the same wafer (Wafer) or different wafers side by side in parallel and at intervals on the carrier 10, as Figure 2 shown; wherein each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is arranged on the carrier 10, and a plurality of pads 23 are provided on the second surface 22 of each bare die 20. And the vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 2 shown.

[0061] Step S3: Fabricate a plurality of first conductive lines 50 on the second surface 22 of each bare die 20 by using the technique of first filling a metal paste into the grooves and then grinding and forming the conductive lines: First, lay a first dielectric layer 30 on the carrier board 10 and the second surface 22 of each bare die 20, and form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, so that each pad 23 of each bare die 20 can be exposed to the outside through each first groove 31, as Figure 3 shown. Then, lay a second dielectric layer 40 on the first dielectric layer 30, and form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, so that each second groove 41 can communicate with each first groove 31, as Figure 4 shown. After that, fill the metal paste 50a into each first groove 31 and each second groove 41, and make the thickness of the metal paste 50a higher than the surface of the second dielectric layer 40, as Figure 5 shown. Finally, grind the metal paste 50a higher than the surface of the second dielectric layer 40, so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of the first conductive lines 50, as Figure 6 shown.

[0062] Step S4: Fabricate a plurality of second conductive lines 80 on the second dielectric layer 40 and the plurality of first conductive lines 50 by using the technique of first filling a metal paste into the grooves and then grinding and forming the conductive lines: First, lay a third dielectric layer 60 on the second dielectric layer 40, and form a plurality of third grooves 61 extending horizontally on the third dielectric layer 60, so that each third groove 61 can communicate with each second groove 41, as Figure 7 shown. Then, lay a fourth dielectric layer 70 on the third dielectric layer 60, and form a plurality of fourth grooves 71 extending horizontally on the fourth dielectric layer 70, so that each fourth groove 71 can communicate with each third groove 61, as Figure 8 shown. After that, fill the metal paste 80a into each third groove 61 and each fourth groove 71, and make the thickness of the metal paste 80a higher than the surface of the fourth dielectric layer 70, as Figure 9 shown. Finally, grind the metal paste 80a higher than the surface of the fourth dielectric layer 70, so that the surface of the metal paste 80a is flush with the surface of the fourth dielectric layer 70 to form a plurality of the second conductive lines 80, as Figure 10 shown; wherein each second conductive line 80 is electrically connected to each first conductive line 50, as Figure 10 shown.

[0063] Step S5: Lay an outer protective layer 90 on the fourth dielectric layer 70, as Figure 11 shown.

[0064] Step S6: Form a plurality of openings 91 in the outer protective layer 90, and make at least one of the openings 91 surround the chip region 1a on the second surface 22 of each bare die 20, so that each second conductive line 80 can be exposed to the outside through each opening 91 and a solder pad 81 is formed in each opening 91, as Figure 11 shown.

[0065] Step S7: Perform a dicing operation and dice to form a plurality of fan-out wafer-level packaging units 1 in units of one package having at least two of the bare dies 20, as Figure 11 shown.

[0066] The manufacturing processes of steps S3 to S4 in the process of manufacturing the fan-out wafer-level packaging unit 1 can be regarded as key steps for manufacturing the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1. Among them, in step S3, a plurality of the first conductive lines 50 are formed on the second surface 22 of each bare die 20 by using a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. In step S4, a plurality of the second conductive lines 80 are formed on the second dielectric layer 40 and the plurality of the first conductive lines 50 by using a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. Since both steps S3 and S4 are processes that are easy to implement precisely, the manufacturing process is relatively simplified, which is sufficient to enable each first conductive line 50 and each second conductive line 80 in the redistribution layer to generate XY-plane electrical extension and interconnection effects, and at the same time enable the manufactured fan-out wafer-level packaging unit 1 to still maintain or achieve a certain degree of thinness, lightness, shortness and small size. Specifically, when there are at least two of the bare dies 20 in the fan-out wafer-level packaging unit 1, it can still maintain or achieve a certain degree of thinness, lightness, shortness and small size.

[0067] Compared with the existing fan-out wafer-level packaging unit technology, the fan-out wafer-level packaging unit 1 of the present utility model has the following advantages:

[0068] (1) In the process of manufacturing the fan-out wafer-level packaging unit 1 of the present utility model, such as steps S3 to S4, compared with the related manufacturing technologies of the existing fan-out wafer-level packaging units, manufacturing the fan-out wafer-level packaging unit of the present utility model enables each conductive line in the RDL to generate XY-plane electrical extension and interconnection effects through the production of each conductive line in the RDL, and at the same time can maintain or achieve a certain degree of thinness, lightness, shortness and small size. These are all simplified and easily precisely implemented steps, which are particularly beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present utility model is not only relatively simplified and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer-level packaging unit 1.

[0069] (2) When manufacturing the multiple first conductive lines 50 of the present utility model, the technology of first injecting metal paste into the grooves and then grinding and forming the conductive lines can be utilized to form them on the second surface 22 of each bare die 20. Therefore, manufacturing the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness that are prone to occur in the existing fan-out packaging technology when manufacturing each conductive line.

[0070] (3) When manufacturing the multiple second conductive lines 80 of the present utility model, the technology of first injecting metal paste into the grooves and then grinding and forming the conductive lines can be utilized to form them on the second dielectric layer 40 and the multiple first conductive lines 50. Therefore, manufacturing the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness that are prone to occur in the existing fan-out packaging technology when manufacturing each conductive line.

[0071] (4) Each bare die 20 of the present utility model can be electrically connected externally in sequence through each pad 23, each first conductive line 50 (formed by RDL technology), each second conductive line 80 (formed by RDL technology), and each pad 81 around the chip area 1a on the second surface 22 of each bare die 20. That is, in the state where each conductive line in RDL generates XY-plane electrical extension and interconnection effects, it can also enable the fan-out wafer-level packaging unit in a multi-chip form to maintain or achieve a certain degree of thin, light, short, and small integration effect, thereby increasing the market competitiveness of the product.

[0072] The above is only the preferred embodiment of the present utility model, which is illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.

Claims

1. A fan-out wafer-level packaging unit, characterized in that: Include: a carrier board; At least one bare die, each of which is separated from a wafer, each of which is disposed on the carrier, each of which has a first surface and an opposite second surface, the first surface of each of which is fixed on the carrier, the second surface of each of which has a plurality of die pads, and a vertical chip area of ​​the second surface is defined as a chip area; A first dielectric layer is disposed on the carrier and the second surface of each of the bare crystals, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the bare crystals is exposed to the outside by the plurality of the first grooves; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; A plurality of first conducting circuits, each of which is formed by metal paste filled in a plurality of the first grooves and a plurality of the second grooves, and each of which is electrically connected to a plurality of the die pads of each of the bare die; a third dielectric layer disposed on the second dielectric layer, the third dielectric layer having a plurality of third grooves extending in a horizontal direction, each of the third grooves being connected to each of the second grooves; a fourth dielectric layer disposed on the third dielectric layer, the fourth dielectric layer having a plurality of fourth grooves extending in a horizontal direction, each of the fourth grooves being connected to each of the third grooves; A plurality of second conducting circuits, each of which is formed by metal paste filled in a plurality of the third grooves and a plurality of the fourth grooves, and each of the second conducting circuits is electrically connected to each of the first conducting circuits; and An outer protective layer is disposed on the fourth dielectric layer, the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip region on the second surface of each of the die; Each of the second conducting circuits is exposed to the outside by a plurality of the openings and a welding pad is formed in each of the openings; Each of the bare die can be electrically connected to the outside via each of the die pads, each of the first conductive circuits, each of the second conductive circuits and a plurality of the bonding pads around the chip region on the second surface of each of the bare die in sequence, thereby forming the fan-out wafer-level packaging unit.

2. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

3. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The metal paste constituting each of the first conducting circuits and each of the second conducting circuits includes silver paste, nano silver paste, copper paste or nano copper paste.

4. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The first surface of each bare die is disposed on the carrier by using a chip bonding film.

5. The fan-out wafer level packaging unit according to claim 1, characterized in that: A solder ball is further disposed on each of the openings, and each of the solder balls can be electrically connected to each of the pads in the plurality of the openings; wherein the fan-out wafer-level packaging unit is electrically connected and disposed on a printed circuit board using the plurality of solder balls.

6. A fan-out wafer-level packaging unit, characterized in that: Include: a carrier board; At least two bare die, each of which is separated from the same wafer or different wafers, each of which is arranged parallel and spaced apart on the carrier, each of which has a first surface and an opposite second surface, the first surface of each of which is fixed on the carrier, the second surface of each of which has a plurality of pads, and a vertical chip area of ​​the second surface is defined as a chip area; A first dielectric layer is disposed on the carrier and the second surface of each of the bare crystals, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the bare crystals is exposed to the outside by the plurality of the first grooves; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; A plurality of first conducting circuits, each of which is formed by metal paste filled in a plurality of the first grooves and a plurality of the second grooves, and each of which is electrically connected to a plurality of the die pads of each of the bare die; a third dielectric layer disposed on the second dielectric layer, the third dielectric layer having a plurality of third grooves extending in a horizontal direction, each of the third grooves being connected to each of the second grooves; a fourth dielectric layer disposed on the third dielectric layer, the fourth dielectric layer having a plurality of fourth grooves extending in a horizontal direction, each of the fourth grooves being connected to each of the third grooves; A plurality of second conducting circuits, each of which is formed by metal paste filled in a plurality of the third grooves and a plurality of the fourth grooves, and each of the second conducting circuits is electrically connected to each of the first conducting circuits; and An outer protective layer is disposed on the fourth dielectric layer, the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip region on the second surface of each of the die; Each of the second conducting circuits is exposed to the outside by a plurality of the openings and a welding pad is formed in each of the openings; Each of the bare die can be electrically connected to the outside via each of the die pads, each of the first conductive circuits, each of the second conductive circuits and a plurality of the bonding pads around the chip region on the second surface of each of the bare die in sequence, thereby forming the fan-out wafer-level packaging unit.

7. The fan-out wafer level packaging unit according to claim 6, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

8. The fan-out wafer level packaging unit according to claim 6, characterized in that: The metal paste constituting each of the first conducting circuits and each of the second conducting circuits includes silver paste, nano silver paste, copper paste or nano copper paste.

9. The fan-out wafer level packaging unit according to claim 6, characterized in that: The first surface of each bare die is further disposed on the carrier using a chip bonding film.

10. The fan-out wafer level packaging unit according to claim 6, characterized in that: A solder ball is disposed on each of the openings, and each of the solder balls can be electrically connected to a plurality of the pads in a plurality of the openings; wherein the fan-out wafer-level packaging unit is electrically connected and disposed on a printed circuit board using a plurality of the solder balls.

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