Low junction capacitance diode

Abstract

The utility model relates to the technical field of semiconductors, and discloses a low-junction capacitance diode, which comprises a high-voltage diode and a clamping diode which are reversely connected in series, the clamping diode comprises a first epitaxial layer and a first diffusion region, and the first epitaxial layer and the first diffusion region form a first PN junction; the high-voltage diode comprises a second epitaxial layer and a P + + substrate, and the second epitaxial layer and the P + + substrate form a second PN junction. According to the utility model, the purpose of low junction capacitance is realized through the double-layer epitaxial structure, the realization process is simple, the cost is low, the repeatability is high, batch production is easy, and the reliability level of high junction temperature is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a low-junction-capacitance diode. Background Art

[0002] There is capacitance between the PN junctions of a diode, which can be regarded as a capacitor connected in parallel to the diode. It is formed by the charge storage effect caused by the potential barrier region of the PN junction. When the voltage across the diode changes, it will cause a change in the number of charges in this region, thus showing a capacitance effect. In high-frequency circuits, due to the rapid change of the reverse bias polarity, the junction capacitance becomes an important influencing factor. The size of the junction capacitance affects the communication effect, and generally, the smaller the better.

[0003] A low-capacitance diode is a diode with a relatively low capacitance, mainly used in high-frequency, high-speed, and other capacitance-sensitive electronic devices. For example, in radio frequency (RF) circuits and the microwave field, diodes with smaller capacitance values can provide higher frequency responses and shorter response times; in high-speed communication and wireless communication fields, low-capacitance diodes can be used for the protection of high-speed data interfaces; in high-speed switching circuits, low-junction-capacitance diodes can effectively reduce transmission delays; in reducing stray noise, they have excellent performance in low-frequency amplification circuits, etc.

[0004] A transient voltage suppression diode (TVS), also called a clamping diode, is a commonly used high-performance circuit protection device at present. Its appearance is the same as that of an ordinary diode, but it can absorb surge power of up to several kilowatts. In a TVS, the size of the junction capacitance reflects the ability of the capacitor to store charges. The larger the junction capacitance, the stronger the ability of the capacitor to store or release charges, that is, the larger the junction capacitance, the stronger its ability to absorb and suppress more overvoltage. However, in a high-frequency lightning protection circuit, if the PN junction capacitance is too large, high-frequency signals will be lost, and only a TVS with a low junction capacitance can be selected. The junction capacitance of a TVS is divided into two types: high-junction-capacitance type, generally several hundred to several thousand pF, and low-capacitance type, generally several pF (picofarad, the international unit of capacitance). Generally speaking, the junction capacitance of a diode decreases with the increase of the working voltage and increases with the decrease of the voltage. The junction capacitance of a low-voltage TVS with a common structure will be relatively high. Therefore, in order to manufacture a low-capacitance low-voltage TVS diode suitable for high-frequency circuits, it can only be achieved through special structural design.

[0005] The current design methods for low junction capacitance include: connecting a TVS diode in series with a low-capacitance diode, which can reduce the capacitance value of the device. However, packaging the TVS diode and the low-capacitance diode in series together has a high cost. There is also a method of covering a semiconductor substrate on an insulator, and on the surface of the epitaxial layer on the substrate, using an isolation structure to divide it into a TVS diode region and multiple low-capacitance diode regions, thus designing a TVS diode structure with a lower clamping voltage. In particular, this isolation groove penetrates the epitaxial layer and extends to the surface of the insulating layer, and the groove is filled with silicon dioxide or polysilicon. This kind of isolation groove requires deep groove dry etching with low efficiency, and both the filled silicon dioxide or polysilicon have high requirements for equipment and processes.

[0006] In summary, the diode structures designed by the above design methods are all relatively complex, the implementation processes are also very complex, the parameters are not easy to control. Especially, they all adopt the PN regions on the same surface, and the current is transmitted laterally, which is difficult to achieve for high-power devices. Moreover, the designed diode junction capacitance is still very large, the achieved junction temperature is relatively low, and the reliability is poor. Summary of the Invention

[0007] In view of this, the present invention provides a low junction capacitance diode to solve the problem of large diode junction capacitance.

[0008] In a first aspect, the present invention provides a low junction capacitance diode, which includes a high-voltage diode and a clamping diode connected in reverse series;

[0009] The clamping diode includes a first epitaxial layer and a first diffusion region, and the first epitaxial layer and the first diffusion region form a first PN junction; the high-voltage diode includes a second epitaxial layer and a P++ substrate, and the second epitaxial layer and the P++ substrate form a second PN junction.

[0010] The low junction capacitance diode provided by the present invention adopts a double epitaxial structure of the first epitaxial layer and the second epitaxial layer. The first PN junction is formed by using the first epitaxial layer and the first diffusion region to form the clamping diode, and the second PN junction is formed by the second epitaxial layer and the P++ substrate to form the high-voltage diode connected in reverse series with the clamping diode. The purpose of lower junction capacitance is achieved through the double epitaxial structure, and the implementation process is simple, the cost is low, the repeatability is high, it is easy to mass-produce, and it has a high reliability level of junction temperature.

[0011] In an optional implementation manner, the first epitaxial layer and the second epitaxial layer are respectively an N-- layer and an N- layer diffused successively on the P++ substrate;

[0012] The first diffusion region includes a P+ region formed by boron diffusion on the N- layer, and the N- layer and the P+ region form the first PN junction;

[0013] The N-- layer and the P++ substrate form a second PN junction.

[0014] A low-junction-capacitance diode provided by the present utility model, the first epitaxial layer and the second epitaxial layer are respectively an N-- layer and an N- layer sequentially diffused on the P++ substrate; the first diffusion region includes a P+ region formed by boron diffusion on the N- layer, and the N- layer and the P+ region form a first PN junction; the N-- layer and the P++ substrate form a second PN junction, achieving the purpose of forming a clamping diode by the first PN junction and a high-voltage diode connected in reverse series by the second PN junction, and having the advantage of simple implementation process.

[0015] In an optional implementation manner, the low-junction-capacitance diode further includes a first trench, a first deposition region, and a first passivation layer;

[0016] The depth of the first trench is greater than the sum of the depths of the first PN junction and the second PN junction;

[0017] The first deposition region is disposed in the first trench, and the first deposition region includes polysilicon and silicon oxide;

[0018] Photolithographic glass is also filled in the first trench, and a first passivation layer is disposed on the outer surface of the first trench.

[0019] A low-junction-capacitance diode provided by the present utility model, the depth of the first trench is greater than the sum of the depths of the first PN junction and the second PN junction; the first deposition region is disposed in the first trench, the first deposition region includes polysilicon and silicon oxide, photolithographic glass is also filled in the first trench, the trench width process window is large, a wet etching process with higher efficiency is adopted, a first passivation layer is disposed on the outer surface of the first trench, the depth and slope of the trench can be reduced, the multi-layer passivation process reduces the leakage current of the high-voltage diode and the clamping diode, and also improves the junction temperature Tj of the diode device, and the first passivation layer can protect the first PN junction and the second PN junction.

[0020] In an optional implementation manner, the surfaces of the high-voltage diode and the clamping diode region both include metal electrodes, and the metal electrodes are formed on the first diffusion region and the P++ substrate.

[0021] A low-junction-capacitance diode provided by the present utility model, by forming metal electrodes on the first diffusion region and the P++ substrate, improves the use performance of the low-junction-capacitance diode.

[0022] In a second aspect, the present utility model provides a low-junction-capacitance diode, the low-junction-capacitance diode includes a high-voltage diode and a clamping diode connected in reverse series;

[0023] The clamping diode includes a single-crystal silicon wafer N+ layer and a second diffusion region, and the single-crystal silicon wafer N+ layer and the second diffusion region form a first PN junction;

[0024] The high-voltage diode includes a single-crystalline silicon wafer N-layer and a third diffusion region, and the single-crystalline silicon wafer N-layer and the third diffusion region form a second PN junction.

[0025] A low-junction-capacitance diode provided by the present utility model uses a single-crystalline silicon wafer with lower cost, and replaces a double-layer epitaxial structure with a second diffusion region and a third diffusion region formed by two-step diffusion, achieving the purpose of lower junction capacitance. Moreover, the implementation process is simple, the cost is low, the repeatability is high, mass production is easy, and it has a high reliability level of junction temperature.

[0026] In an optional implementation manner, the single-crystalline silicon wafer N+-layer is a single-crystalline silicon wafer N+-layer with a preset concentration formed by a phosphorus implantation method or a gaseous phosphorus diffusion method using phosphorus oxychloride.

[0027] The second diffusion region includes a P+2 region formed by coating a boron latex source on the single-crystalline silicon wafer N+-layer and performing boron diffusion. The single-crystalline silicon wafer N+-layer and the P+2 region form a first PN junction.

[0028] The third diffusion region includes a P+1 region formed by coating a boron latex source on the single-crystalline silicon wafer N-layer and performing boron diffusion. The single-crystalline silicon wafer N-layer and the P+1 region form a second PN junction.

[0029] A low-junction-capacitance diode provided by the present utility model, the second diffusion region includes a P+2 region formed by coating a boron latex source on the single-crystalline silicon wafer N+-layer and performing boron diffusion. The single-crystalline silicon wafer N+-layer and the P+2 region form a first PN junction. The third diffusion region includes a P+1 region formed by coating a boron latex source on the single-crystalline silicon wafer N-layer and performing boron diffusion. The single-crystalline silicon wafer N-layer and the P+1 region form a second PN junction, and the purpose of reducing the junction capacitance of the first PN junction can be achieved.

[0030] In an optional implementation manner, when the single-crystalline silicon wafer N+-layer and the P+2 region form a first PN junction, and the single-crystalline silicon wafer N-layer and the P+1 region form a second PN junction, the low-junction-capacitance diode further includes a second trench, a second deposition region, and a second passivation layer.

[0031] The depth of the second trench is greater than the sum of the depth of the first PN junction and the depth of the second PN junction.

[0032] The second deposition region is disposed in the second trench, and the second deposition region includes polysilicon and silicon oxide.

[0033] Photolithographic glass is also filled in the second trench, and a second passivation layer is disposed on the outer surface of the second trench.

[0034] A low-junction-capacitance diode provided by the present utility model. The second trench significantly reduces the series resistance of the diode, thereby reducing power loss and improving efficiency. Photolithographic glass is also filled in the second trench to expand the process window of the trench width, reduce the leakage current of the high-voltage diode and the clamping diode, and has the advantage of a high reliability level of the junction temperature. The second passivation layer can protect the first PN junction and the second PN junction.

[0035] In an alternative embodiment, the single-crystal silicon wafer N+ layer is a single-crystal silicon wafer N+ layer with a preset concentration formed by a phosphorus implantation method or a gaseous phosphorus diffusion method using phosphorus oxychloride.

[0036] The second diffusion region further includes a first window lithographed on the single-crystal silicon wafer N+ layer. After boron diffusion on the first window, a first PN junction is formed.

[0037] The third diffusion region further includes a second window that is thermally oxidized and lithographed on the single-crystal silicon wafer N- layer. After boron diffusion on the second window, a second PN junction is formed.

[0038] A low-junction-capacitance diode provided by the present utility model. A first window is lithographed on the single-crystal silicon wafer N+ layer. After boron diffusion on the first window, a first PN junction is formed. A second window is thermally oxidized and lithographed on the single-crystal silicon wafer N- layer. After boron diffusion on the second window, a second PN junction is formed. The structures of the first PN junction and the second PN junction are directly formed through the lithographic window and the boron implantation method, realizing simple process, low cost, high repeatability, easy mass production, and the reliability can meet the junction temperature of 175 degrees.

[0039] In an alternative embodiment, the low-junction-capacitance diode further includes a third passivation layer. The third passivation layer wraps the outer surface of the first PN junction formed by thermally oxidizing and lithographing a first window on the single-crystal silicon wafer N- layer and performing boron diffusion on the first window, and the outer surface of the second PN junction formed by lithographing a second window on the single-crystal silicon wafer N+ layer and performing boron diffusion on the second window.

[0040] A low-junction-capacitance diode provided by the present utility model achieves the purpose of protecting the first PN junction and the second PN junction through the third passivation layer.

[0041] In an alternative embodiment, the surfaces of the high-voltage diode and the clamping diode region both include metal electrodes, and the metal electrodes are formed in the second diffusion region and the third diffusion region. Description of the Drawings

[0042] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 is a schematic structural diagram of a low junction capacitance diode according to an embodiment of the present invention;

[0044] Figure 2a is a schematic structural diagram of another low junction capacitance diode according to an embodiment of the present invention;

[0045] Figure 2b is a top view and a longitudinal sectional view of a trench of another low junction capacitance diode according to an embodiment of the present invention;

[0046] Figure 3 is a schematic structural diagram of yet another low junction capacitance diode according to an embodiment of the present invention;

[0047] Figure 4 is a schematic structural diagram of still another low junction capacitance diode according to an embodiment of the present invention. Specific Embodiments

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0049] In the description of the present invention, it should be noted that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0050] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can also be the communication inside two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0051] In addition, the technical features involved in different embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0052] According to an embodiment of the present utility model, an embodiment of a low-junction-capacitance diode is provided. Figure 1 It is a schematic structural diagram of a low-junction-capacitance diode according to an embodiment of the present utility model, as Figure 1 shown, including:

[0053] The low-junction-capacitance diode includes a high-voltage diode and a clamping diode connected in reverse series; the clamping diode includes a first epitaxial layer 11 and a first diffusion region 12, and the first epitaxial layer 11 and the first diffusion region 12 form a first PN junction 13; the high-voltage diode includes a second epitaxial layer 14 and a P++ substrate 15, and the second epitaxial layer 14 and the P++ substrate 15 form a second PN junction 16. Specifically, a thin single-crystal layer is deposited on a single-crystal substrate, and this newly deposited single-crystal layer is called an epitaxial layer, that is, the first epitaxial layer and the second epitaxial layer formed by deposition on the P++ substrate in this embodiment. The first diffusion region can be formed by boron diffusion. In this embodiment, the breakdown voltage design of the high-voltage diode is between 500V and 700V. A low-junction-capacitance diode provided in this embodiment adopts a double-epitaxial structure of a first epitaxial layer and a second epitaxial layer, and uses the first epitaxial layer and the first diffusion region to form a first PN structure to form a clamping diode, and the second epitaxial layer and the P++ substrate form a second PN structure to form a high-voltage diode connected in reverse series with the clamping diode. Through the double-epitaxial structure, the purpose of lower junction capacitance is achieved, and the implementation process is simple, the cost is low, the repeatability is high, it is easy to mass-produce, and it has a high reliability level of junction temperature.

[0054] In an alternative embodiment, as Figure 2a shown, the first epitaxial layer and the second epitaxial layer are respectively an N-- layer 151 and an N- layer 152 sequentially diffused on the P++ substrate 15; the first diffusion region includes a P+ region 121 formed by boron diffusion on the N- layer, and the N- layer 152 and the P+ region 121 form a first PN junction 13; the N-- layer 151 and the P++ substrate 15 form a second PN junction 16.

[0055] Specifically, an N-- layer and an N- layer are sequentially diffused on a P++ substrate. The N- layer is used as the first epitaxial layer, and the N-- layer is used as the second epitaxial layer. The second epitaxial layer is located outside the first epitaxial layer.

[0056] The first diffusion region is a P+ region formed by boron diffusion on the N- layer. The concentration of boron diffusion is determined according to the breakdown voltage of the clamping diode, and no specific limitation is made here.

[0057] A low junction capacitance diode provided in this embodiment, the first epitaxial layer and the second epitaxial layer are respectively an N-- layer and an N- layer sequentially diffused on a P++ substrate; the first diffusion region includes a P+ region formed by boron diffusion on the N- layer, and the N- layer and the P+ region form a first PN junction; the N-- layer and the P++ substrate form a second PN junction, achieving the purpose of forming a clamping diode by the first PN junction and a high-voltage diode connected in reverse series by the second PN junction, and having the advantage of simple implementation process.

[0058] In an optional implementation manner, the low junction capacitance diode further includes a first trench 17, a first deposition region, and a first passivation layer 18; the depth of the first trench 17 is greater than the sum of the depths of the first PN junction and the second PN junction; the first deposition region is disposed in the first trench, and the first deposition region includes polysilicon and silicon oxide; a lithographic glass 19 is further filled in the first trench, and a first passivation layer is disposed on the outer surface of the first trench.

[0059] Specifically, the specific processes implemented by the first trench, the first deposition region, and the first passivation layer are as follows:

[0060] Step 1), protect the clamping diode and the high-voltage diode by lithography, and only expose the surrounding areas of the clamping diode and the high-voltage diode.

[0061] Step 2), open the first trench with a silicon etching solution, corresponding to the first trenches on both sides as shown in Figure 2a shown.

[0062] Step 3), form the first deposition region in the first trench by CVD (Chemical Vapor Deposition, abbreviated as CVD), and doped oxygen polysilicon and silicon oxide are deposited in the first deposition region;

[0063] Step 4), in order to increase the strength and improve the reliability of the clamping diode and the high-voltage diode, fill the first trench with lithographic glass and sinter at high temperature to form a composite first passivation layer, and the first passivation layer is as shown in Figure 2b the top view and longitudinal sectional view of the trench.

[0064] In an alternative embodiment, the surfaces of the high-voltage diode and the surface of the clamping diode region both include metal electrodes, and the metal electrodes are formed on the first diffusion region and the P++ substrate.

[0065] Specifically, a metal evaporation operation is performed on the upper surface of the P++ substrate of the high-voltage diode and the surface of the first diffusion region of the clamping diode region, and finally metal electrodes are formed on the first diffusion region and the P++ substrate.

[0066] A low-junction-capacitance diode provided in this embodiment adopts a double-layer epitaxial structure. The PN junction formed by the first epitaxial layer and the P++ substrate constitutes a high-voltage diode connected in reverse series, and the PN junction formed by boron diffusion on the second epitaxial layer constitutes a TVS diode. Through simple wet trench opening, the process efficiency is high. Then, polysilicon and silicon oxide are deposited, and a first passivation layer is formed by processes such as glass sintering passivation, which can achieve the passivation protection effect for the two diodes in one step. The purpose of having a lower junction capacitance is achieved, and it has a high-reliability level of junction temperature. The junction capacitance can be controlled below 10 PF (picofarad), and the reliability level of the junction temperature can reach 175 degrees.

[0067] The present utility model also provides a low-junction-capacitance diode, as Figure 3 and Figure 4 shown, the low-junction-capacitance diode includes a high-voltage diode and a clamping diode connected in reverse series;

[0068] The clamping diode includes a single-crystal silicon wafer N+ layer 20 and a second diffusion region, and the single-crystal silicon wafer N+ layer and the second diffusion region form a first PN junction; the high-voltage diode includes a single-crystal silicon wafer N- layer and a third diffusion region, and the single-crystal silicon wafer N- layer and the third diffusion region form a second PN junction.

[0069] Specifically, both the second diffusion region and the third diffusion region can be implanted with a certain concentration of boron and formed by boron diffusion. The certain concentration of boron is determined according to the breakdown voltage of the clamping diode, and no specific limitation is made here.

[0070] A low-junction-capacitance diode provided in this embodiment uses a single-crystal silicon wafer with a lower cost, and replaces the double-layer epitaxial structure with the second diffusion region and the third diffusion region formed by two-step diffusion, achieving the purpose of having a lower junction capacitance, and the implementation process is simple, the cost is low, the repeatability is high, it is easy to mass-produce, and it has a high-reliability level of junction temperature.

[0071] In an alternative embodiment, the N+ layer 20 of the single-crystalline silicon wafer is a single-crystalline silicon wafer N+ layer with a preset concentration formed by phosphorus implantation or gaseous phosphorus diffusion using phosphorus oxychloride; the second diffusion region includes a P+2 region 21 formed by coating a boron latex source on the N+ layer of the single-crystalline silicon wafer and performing boron diffusion, and the N+ layer 20 of the single-crystalline silicon wafer and the P+2 region 21 form a first PN junction 13. The third diffusion region includes a P+1 region 23 formed by coating a boron latex source on the N- layer 22 of the single-crystalline silicon wafer and performing boron diffusion, and the N- layer 22 of the single-crystalline silicon wafer and the P+1 region 23 form a second PN junction 16.

[0072] Specifically, the single-crystalline silicon wafer can be implemented using a lower-cost N-type single-crystalline silicon wafer or P-type single-crystalline silicon wafer. Taking the N-type single-crystalline silicon wafer as an example, the specific implementation process of forming the first PN junction and the second PN junction using the second diffusion region and the third diffusion region respectively is as follows:

[0073] Step 1), coat a liquid boron latex source on one side of the N- layer of the N-type single-crystalline silicon wafer;

[0074] Step 2), form a P+1 region by diffusion at a high temperature (such as setting the temperature at 1250 degrees for 4 hours) on the boron latex source, and the N- layer of the single-crystalline silicon wafer and the P+1 region form the second PN junction of the high-voltage diode;

[0075] Step 3), form a single-crystalline silicon wafer N+ layer with a preset concentration (the preset concentration is determined according to the breakdown voltage of the target clamping diode TVS and is not specifically limited here) on one side of the N+ layer of the N-type single-crystalline silicon wafer by phosphorus implantation or POCl3 gaseous phosphorus diffusion;

[0076] Step 4), coat a liquid boron latex source on the single-crystalline silicon wafer N+, and form a P+2 region by diffusion at a high temperature (set the temperature at 1200 degrees, and the diffusion time is further fine-tuned according to the voltage of the target clamping diode TVS), and the N+ layer of the single-crystalline silicon wafer and the P+2 region form the first PN junction of the target clamping diode TVS.

[0077] It should be noted that the production order of the first PN junction and the second PN junction can be changed, that is, the first PN junction can be made first and then the second PN junction, or the second PN junction can be made first and then the first PN junction.

[0078] A low-junction-capacitance diode provided in this embodiment, the second diffusion region includes a P+2 region formed by coating a boron latex source on the N+ layer of the single-crystalline silicon wafer and performing boron diffusion, the N+ layer of the single-crystalline silicon wafer and the P+2 region form a first PN junction, the third diffusion region includes a P+1 region formed by coating a boron latex source on the N- layer of the single-crystalline silicon wafer and performing boron diffusion, the N- layer of the single-crystalline silicon wafer and the P+1 region form a second PN junction, which can achieve the purpose of reducing the junction capacitance of the first PN junction and has the advantage of a high reliability level of the junction temperature.

[0079] In an alternative embodiment, as Figure 3 shown, when the N+ layer of the single-crystal silicon wafer and the P+2 region form a first PN junction, and the N- layer of the single-crystal silicon wafer and the P+1 region form a second PN junction, the low-junction capacitance diode further includes a second trench 24, a second deposition region, and a second passivation layer; the depth of the second trench is greater than the sum of the depths of the first PN junction and the second PN junction; the second deposition region is disposed in the second trench, and the second deposition region includes polysilicon and silicon oxide; a photolithographic glass is further filled in the second trench, and a second passivation layer is disposed on the outer surface of the second trench.

[0080] Specifically, as Figure 3 shown, when the N+ layer of the single-crystal silicon wafer and the P+2 region form a first PN junction, and the N- layer of the single-crystal silicon wafer and the P+1 region form a second PN junction, the specific implementation processes of the second trench, the second deposition region, and the second passivation layer are as follows:

[0081] Step 1), using a double-sided exposure machine, after exposure and development (process: coating photoresist - double-sided exposure - exposing the area where trenches need to be opened through development), simultaneously open a second trench in the P+1 region of the high-voltage diode and the P+2 region of the target clamping diode TVS with a silicon etching solution (as Figure 3 shown), and the depth of the second trench is greater than the sum of the depths of the first PN junction and the second PN junction.

[0082] Step 2), form a second deposition region in the second trench by CVD (Chemical Vapor Deposition, abbreviated as CVD), and polysilicon and silicon oxide are deposited in the second deposition region; form a second deposition region in the second trench by CVD (Chemical Vapor Deposition, abbreviated as CVD), and polysilicon and silicon oxide are deposited in the second deposition region.

[0083] Step 3), in order to increase the strength and improve the reliability of the clamping diode and the high-voltage diode, fill the second trench with a photolithographic glass and sinter at a high temperature to form a composite second passivation layer.

[0084] For the low-junction capacitance diode provided in this embodiment, the second trench significantly reduces the series resistance of the diode, thereby reducing power loss and improving efficiency. A photolithographic glass is further filled in the second trench to reduce the depth and slope of the trench, reduce the leakage current of the high-voltage diode and the clamping diode, and the second passivation layer can protect the first PN junction and the second PN junction.

[0085] In an alternative embodiment, as Figure 4As shown, the N+ layer of the single-crystal silicon wafer is an N+ layer of single-crystal silicon wafer with a preset concentration formed by phosphorus implantation or gaseous phosphorus diffusion using phosphorus oxychloride; the second diffusion region further includes a first window lithographed on the N+ layer of the single-crystal silicon wafer, and a first PN junction is formed after boron diffusion on the first window; the third diffusion region further includes a second window formed by thermal oxidation and lithography on the N- layer of the single-crystal silicon wafer, and a second PN junction is formed after boron diffusion on the second window.

[0086] Specifically, taking an N-type single-crystal silicon wafer as an example, the specific implementation process of forming the first PN junction and the second PN junction using the second diffusion region and the third diffusion region respectively is as follows:

[0087] Step 1), an N+ layer with a preset concentration (the preset concentration is determined according to the breakdown voltage of the target clamping diode TVS, and no specific limitation is made here) is formed on the single-crystal silicon wafer by gaseous phosphorus diffusion of POCl3 of phosphorus oxychloride;

[0088] Step 2), on the N+ of the single-crystal silicon wafer, a first window is lithographed, boron is selectively implanted in the first window, and high-temperature diffusion is performed to form a P region 25. The N+ of the single-crystal silicon wafer and the P region form a first PN junction, and the concentration of implanted and diffused boron can be finely adjusted to match the target voltage of the target clamping diode TVS.

[0089] Step 3), the N- layer of the single-crystal silicon wafer is thermally oxidized in a high-temperature diffusion furnace, a second window is lithographed on the N- layer of the single-crystal silicon wafer, boron is selectively implanted in the second window, and after boron diffusion, a P+1 region is formed. The N- layer of the single-crystal silicon wafer and the P+1 region form the second PN junction of the high-voltage diode;

[0090] It should be noted that the production order of the first PN junction and the second PN junction can be changed, that is, the first PN junction can also be made first and then the second PN junction, or the second PN junction can be made first and then the first PN junction.

[0091] A low-junction-capacitance diode provided in this embodiment, the second diffusion region includes a P+2 region formed after coating a boron latex source on the N+ layer of the single-crystal silicon wafer and performing boron diffusion. The N+ layer of the single-crystal silicon wafer and the P+2 region form a first PN junction. The third diffusion region includes a P+1 region formed after coating a boron latex source on the N- layer of the single-crystal silicon wafer and performing boron diffusion. The N- layer of the single-crystal silicon wafer and the P+1 region form a second PN junction, which can achieve the purpose of reducing the junction capacitance of the first PN junction and has the advantage of a high reliability level of the junction temperature.

[0092] In an alternative embodiment, the low junction capacitance diode further includes a third passivation layer, which wraps the outer surfaces of the first PN junction formed by thermal oxidation and photolithography of a first window on the N-layer of the single crystal silicon wafer followed by boron diffusion in the first window, and the outer surfaces of the second PN junction formed by photolithography of a second window on the N+-layer of the single crystal silicon wafer followed by boron diffusion in the second window.

[0093] In an alternative embodiment, the surfaces of the high-voltage diode and the surface of the clamping diode region both include metal electrodes, which are formed in the second diffusion region and the third diffusion region.

[0094] Specifically, the outer surfaces of the first PN junction formed by thermal oxidation and photolithography of a first window on the N-layer of the single crystal silicon wafer followed by boron diffusion in the first window, and the outer surfaces of the second PN junction formed by photolithography of a second window on the N+-layer of the single crystal silicon wafer followed by boron diffusion in the second window are deposited with silicon oxide and silicon nitride by CVD (Chemical Vapor Deposition, abbreviated as CVD), and the silicon oxide and silicon nitride depositions form a highly reliable third passivation layer after deposition.

[0095] After the third passivation layer is formed, as Figure 3 shown, a metal evaporation operation is performed on the surface of the P+1 region of the high-voltage diode and the surface of the P+2 region of the clamping diode region, and finally metal electrodes are formed in the second diffusion region and the third diffusion region.

[0096] Or,

[0097] After the third passivation layer is formed, as Figure 4 shown, a metal evaporation operation is performed on the surface of the P+1 region of the high-voltage diode and the surface of the P region of the clamping diode region, and finally metal electrodes are formed in the second diffusion region and the third diffusion region.

[0098] The low junction capacitance diode provided in this embodiment achieves the purpose of protecting the first PN junction and the second PN junction through the third passivation layer.

[0099] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A low junction capacitance diode, characterized in that: The low junction capacitance diode comprises a high voltage diode and a clamping diode connected in reverse series; The clamping diode includes a first epitaxial layer and a first diffusion region, wherein the first epitaxial layer and the first diffusion region form a first PN junction; the high-voltage diode includes a second epitaxial layer and a P++ substrate, wherein the second epitaxial layer and the P++ substrate form a second PN junction.

2. The low junction capacitance diode according to claim 1, characterized in that: The first epitaxial layer and the second epitaxial layer are respectively an N-- layer and an N-- layer diffused sequentially on a P++ substrate; The first diffusion region includes a P+ region formed on the N-layer by boron diffusion, and the N-layer and the P+ region form a first PN junction; The N-- layer and the P++ substrate form a second PN junction.

3. The low junction capacitance diode according to claim 1, characterized in that: The low junction capacitance diode further includes a first trench, a first deposition region and a first passivation layer; The depth of the first trench is greater than the sum of the first PN junction depth and the second PN junction depth; The first deposition area is disposed in the first trench, and the first deposition area includes polysilicon and silicon oxide; The first trench is also filled with photolithography glass, and a first passivation layer is disposed on an outer surface of the first trench.

4. The low junction capacitance diode according to claim 3, characterized in that: The surface of the high-voltage diode and the surface of the clamping diode region both include metal electrodes, and the metal electrodes are formed on the first diffusion region and the P++ substrate.

5. A low junction capacitance diode, characterized in that: The low junction capacitance diode comprises a high voltage diode and a clamping diode connected in reverse series; The clamping diode comprises a single crystal silicon wafer N+ layer and a second diffusion region, wherein the single crystal silicon wafer N+ layer and the second diffusion region form a first PN junction; The high-voltage diode comprises a single-crystal silicon wafer N-layer and a third diffusion region, and the single-crystal silicon wafer N-layer and the third diffusion region form a second PN junction.

6. The low junction capacitance diode according to claim 5, characterized in that: The single crystal silicon wafer N+ layer is a single crystal silicon wafer N+ layer with a preset concentration formed by phosphorus injection or by gaseous phosphorus diffusion of phosphorus oxychloride; The second diffusion region includes a P+2 region formed by boron diffusion after a boron latex source is coated on the N+ layer of the single crystal silicon wafer, and the N+ layer of the single crystal silicon wafer and the P+2 region form a first PN junction; The third diffusion region includes a P+1 region formed by boron diffusion of a boron latex source coated on the N-layer of the single crystal silicon wafer, and the N-layer of the single crystal silicon wafer and the P+1 region form a second PN junction.

7. The low junction capacitance diode according to claim 6, characterized in that: When the single crystal silicon wafer N-layer and the P+1 region form a first PN junction, and the single crystal silicon wafer N+ layer and the P+2 region form a second PN junction, the low junction capacitance diode further includes a second trench, a second deposition region, and a second passivation layer; The depth of the second trench is greater than the sum of the first PN junction depth and the second PN junction depth; The second deposition area is disposed in the second trench, and the second deposition area includes polysilicon and silicon oxide; The second trench is also filled with photolithography glass, and a second passivation layer is disposed on an outer surface of the second trench.

8. The low junction capacitance diode according to claim 5, characterized in that: The single crystal silicon wafer N+ layer is a single crystal silicon wafer N+ layer with a preset concentration formed by phosphorus injection or by gaseous phosphorus diffusion of phosphorus oxychloride; The second diffusion region also includes a first window photoetched on the N+ layer of the single crystal silicon wafer, and a first PN junction is formed after boron diffusion is performed on the first window; The third diffusion region also includes a second window formed on the N-layer of the single crystal silicon wafer through thermal oxidation and photolithography, and a second PN junction is formed after boron diffusion is performed on the second window.

9. The low junction capacitance diode according to claim 8, characterized in that: The low junction capacitance diode also includes a third passivation layer, which wraps around the outer surface of a first PN junction formed by photolithography of a first window on the N+ layer of the single crystal silicon wafer and boron diffusion on the first window, and the outer surface of a second PN junction formed by thermal oxidation and photolithography of a second window on the N- layer of the single crystal silicon wafer and boron diffusion on the second window.

10. The low junction capacitance diode according to claim 5, characterized in that: The surface of the high-voltage diode and the surface of the clamping diode region both include metal electrodes, and the metal electrodes are formed in the second diffusion region and the third diffusion region.

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