Optical package

Abstract

The utility model provides an optical package comprising an optical interposer and a semiconductor device. The optical interposer includes an external connector layer, a first interconnect structure, an active device layer, a dielectric substrate, a first bonding layer, and a reflective pad. A first interconnect structure is over the outer connector layer. The first interconnect structure includes a conductive feature embedded in a dielectric layer. An active device layer is over the first interconnect structure. The active device layer includes a grating coupler. A dielectric substrate is over the active device layer. A first bonding layer is over the dielectric substrate. The reflective pad overlaps the grating coupler in a plan view. A semiconductor device is bonded to the first bonding layer of the optical interposer. The semiconductor device includes a second bonding layer, a second interconnect structure, and an electronic device layer.

Description

Technical Field

[0001] The utility model relates to an integrated circuit, and in particular to an optical package. Background Art

[0002] Electrical signaling and processing is a technology used for signal transmission and processing. In recent years, optical signaling and processing has been used in an increasing number of applications, in particular due to the use of optical fiber related applications for signal transmission.

[0003] Optical communication and processing are often combined with electrical communication and processing to provide sophisticated applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission and processing and control. Thus, a device integrating long-distance optical components and short-distance electrical components is formed for conversion between optical and electrical signals and processing of optical and electrical signals. Thus, a package may include both an optical (photonic) die including an optical device and an electronic die including an electronic device. Utility Model Content

[0004] The utility model provides an optical package, including an optical interposer and a semiconductor device. The optical interposer includes an external connector layer, a first internal connection structure, an active device layer, a dielectric substrate, a first bonding layer and a reflective pad. The first internal connection structure is located on the external connector layer. The first internal connection structure includes a conductive feature embedded in the dielectric layer. The active device layer is located on the first internal connection structure. The active device layer includes a grating coupler. The dielectric substrate is located on the active device layer. The first bonding layer is located on the dielectric substrate. The reflective pad overlaps with the grating coupler in a plan view. The semiconductor device is attached to the first bonding layer of the optical interposer. The semiconductor device includes a second bonding layer, a second internal connection structure and an electronic device layer.

[0005] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10Intermediate stages in forming an optical interposer are shown according to some embodiments.

[0008] Fig.11 Intermediate stages in the formation of a semiconductor device in accordance with some embodiments are shown.

[0009] Figures 12 to 15 Intermediate stages in forming an optical package are shown according to some embodiments.

[0010] Figure 16 to Figure 17 Intermediate stages in forming an optical interposer are shown according to some embodiments.

[0011] Fig.18 Intermediate stages in the formation of a semiconductor device in accordance with some embodiments are shown.

[0012] Figures 19 to 21 Intermediate stages in forming an optical package are shown according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the utility model. The following describes specific examples of components and arrangements to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature illustrated in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] The embodiments provided herein are discussed with respect to certain embodiments in which a photonic integrated circuit (PIC) device (e.g., an optical interposer) is formed and an electronic integrated circuit (EIC) device (e.g., a semiconductor device) is bonded to the PIC device to form an optical package such as a compact universal photonic engine (COUPE). In some embodiments, the optical interposer includes a plurality of PIC devices in the form of a wafer, and the EIC device can be singulated from the wafer and bonded to the PIC device in a face-to-back layout. Various advantages can be achieved by using a face-to-back layout. It should be understood that the embodiments presented herein are intended to be illustrative and are not intended to limit the embodiments to the precise description discussed. Instead, the embodiments discussed can be incorporated into a variety of implementations, and all such implementations are fully intended to be included within the scope of the embodiments.

[0016] Figures 1 to 15 An exemplary embodiment of forming a first optical interposer 100 and a first semiconductor device 200 and combining the first optical interposer 100 and the first semiconductor device 200 to form a first optical package 300 is shown. Figures 1 to 10 denoting an exemplary embodiment of a first optical intermediary layer 100, Fig.11 shows an exemplary embodiment of a first semiconductor device 200, and Figures 12 to 15 An exemplary embodiment of processing these components to form the first optical package 300 is shown.

[0017] Figure 1 A partially formed first optical interposer 100 (substantially assembled on Fig.10 In the illustrated embodiment, as described above, the first optical interposer 100 comprises a photonic integrated circuit (e.g., a PIC device), and at this stage comprises a substrate 101, a first insulator layer 103, and a substrate for optical components 109 (see Figure 2 ). In an embodiment, when the manufacturing process of the first optical interposer 100 is close to the beginning, the substrate 101, the first insulator layer 103, and the material layer 105 for the active layer 107 of the optical component 109 may be collectively part of a silicon-on-insulator (SOI) substrate. The substrate 101 may be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that can be used for structural support of overlying devices and other components discussed further below.

[0018] The first insulator layer 103 may be a dielectric layer that separates the substrate 101 from an overlying material 105 (e.g., a subsequent active layer 107), and in some embodiments, the first insulator layer 103 may additionally serve as part of a cladding material surrounding a subsequently fabricated optical component 109 (discussed further below). In embodiments, the first insulator layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like formed using methods such as implantation (e.g., forming a buried oxide (BOX) layer), or may be deposited onto the substrate 101 using deposition methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. However, any suitable materials and fabrication methods may be used.

[0019] The material 105 for the active layer 107 is initially (before patterning) a conformal material layer of the active layer 107 used to begin fabricating the optical component 109. In embodiments, the material 105 for the active layer 107 may be a semi-transparent material that may be used as a core material for the desired optical component 109, such as a semiconductor material (e.g., silicon, germanium, silicon germanium, combinations thereof, or the like), while in other embodiments, the material 105 for the active layer 107 may be a dielectric material (e.g., silicon nitride or the like), although in other embodiments, the material 105 for the active layer 107 may be a III-V material, a lithium niobate material, or a polymer. In embodiments where the material 105 for the active layer 107 is deposited, the material 105 for the active layer may be deposited using methods such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. In other embodiments where implantation is used to form first insulator layer 103, material 105 of active layer 107 may initially be part of substrate 101 prior to the implantation process to form first insulator layer 103. However, material 105 of active layer 107 may be formed of any suitable material and fabrication method.

[0020] Figure 2As shown, once the material 105 for the active layer 107 has been formed, the optical component 109 of the active layer 107 is manufactured using the material 105 for the active layer 107. According to some embodiments, the optical component 109 of the active layer 107 may include components such as optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers, etc.), directional couplers, photodetectors, optical modulators (e.g., Mach-Zehnder silicon photonic switches, micro-electromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical to electrical converters (e.g., PN junctions), electrical to optical converters, lasers, combinations thereof, or similar components. However, any suitable optical component 109 may be used. As shown, among the optical components 109, the coupler may include a grating coupler 109G.

[0021] In order to form the active layer 107 of the optical component 109 starting from the initial material 105, the material 105 of the active layer 107 may be patterned into a desired shape of the active layer 107 of the optical component 109. In an embodiment, the material 105 of the active layer 107 may be patterned using, for example, one or more photolithography masking and etching processes. However, any suitable method of patterning the material 105 of the active layer 107 may be used. For some of the optical components 109, such as waveguides, edge couplers, or grating couplers 109G, the patterning process may be all or at least a majority of the manufacturing process used to form these optical components 109.

[0022] Figure 3 As shown, for those components that utilize other fabrication processes (e.g., Mach-Zander silicon photonic switches with resistive heating components), additional processing may be performed before or after patterning the material of the active layer 107. For example, implantation processes for different materials (e.g., resistive heating components, III-V materials for converters), additional deposition and patterning processes, combinations of all of these processes, or the like may be employed to facilitate further fabrication of various desired optical components 109. In certain embodiments, epitaxial deposition of semiconductor material 111, such as germanium (e.g., for electrical / optical signal modulation and conversion) may be performed on the patterned portions of the material 105 of the active layer 107. In such embodiments, the semiconductor material 111 may be epitaxially grown to facilitate fabrication of, for example, photodiodes for light-to-electrical converters. All such fabrication processes and all suitable optical components 109 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

[0023] Figure 4109 and 110, and the like. As shown, once the individual optical components 109 of the active layer 107 have been formed, a second insulating layer 115 of the active layer 107 may be deposited to cover the optical components 109 and provide additional cladding material. In embodiments, the second insulating layer 115 may be a dielectric layer that separates the individual components of the active layer 107 from each other and from the overlying structures, and may additionally serve as another portion of the cladding material surrounding the optical components 109. In embodiments, the second insulating layer 115 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like formed using deposition methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. Once the material of the second insulating layer 115 has been deposited, the material may be planarized using, for example, a chemical mechanical polishing process to planarize the top surface of the second insulating layer 115 (in embodiments where the second insulating layer 115 is intended to completely cover the optical components 109) or to planarize the second insulating layer 115 and the top surfaces of the optical components 109. However, any suitable materials and manufacturing methods may be used.

[0024] Figure 5 107 and the second insulating layer 115 are formed, a through device via (TDV) 119 is formed through the active layer 107 and the first insulator layer 103. In addition, an interconnect structure 121 is formed to electrically connect the TDV 119 and the active layer 107 of the optical component 109 to the control circuit system, to electrically connect the TDV 119 and the active layer 107 of the optical component 109 to each other, and to electrically connect the TDV 119 and the active layer 107 of the optical component 109 to a subsequently bonded device ( Figure 5 Not shown, but will be addressed below Figures 11 to 15 101 ). In various embodiments (not specifically shown), TDV 119 may be formed before forming active layer 107 or after forming some or all of interconnect structures 121. Additionally, TDV 119 may extend to substrate 101 or partially extend into substrate 101.

[0025] In an embodiment, the interconnect structure 121 is formed of alternating layers of dielectric material and conductive material and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In a particular embodiment, there may be multiple metallization layers or conductive features used to interconnect the various optical components 109, but the exact number of metallization layers of the interconnect structure 121 depends on the design of the first optical interposer 100.

[0026] Additionally, during the fabrication of interconnect structure 121, additional optical components (not specifically shown) may be formed as part of interconnect structure 121. In some embodiments, the additional optical components of interconnect structure 121 may include similar components as discussed above in conjunction with optical component 109, such as couplers (e.g., edge couplers, grating couplers, etc.) for connecting to external signals, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), photodetectors, optical modulators (e.g., Mach-Jander silicon photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical to electrical converters (e.g., PN junctions), electrical to optical converters, lasers, combinations thereof, or the like. However, any suitable optical components may be used for the additional optical components.

[0027] In some embodiments, the additional optical component may be formed by initially depositing a material for the additional optical component. In embodiments, the material for the additional optical component may be a dielectric material such as silicon nitride, silicon oxide, a combination of these or the like, or a semiconductor material such as silicon, deposited using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination of these or the like, or a semiconductor material such as silicon. However, any suitable material and any suitable deposition method may be used.

[0028] Once the material for the additional optical component has been deposited or otherwise formed, the material may be patterned into the desired shape of the additional optical component. In an embodiment, the material for the additional optical component may be patterned using, for example, one or more photolithography masking and etching processes. However, any suitable method of patterning the material for the additional optical component may be employed.

[0029] For some of the additional optical components, such as waveguides or couplers, the patterning process may be all or at least a majority of the manufacturing process used to form those components. Additionally, for those components that employ other manufacturing processes (e.g., Mach-Zander silicon photonic switches with resistive heating components), additional processing may be performed before or after patterning the materials used for the additional optical components, similar to that described above in connection with optical component 109. For example, implantation processes for different materials, additional deposition and patterning processes, combinations of all of these processes, or the like may be used to help further manufacture various desired additional optical components. All such manufacturing processes and all suitable additional optical components may be manufactured, and all such combinations are fully intended to be included within the scope of the embodiments.

[0030] Figure 6It is shown that a metal pad layer 131 is formed on the interconnect structure 121 according to some embodiments. The metal pad layer 131 may include a metal pad 135 and a dielectric layer (e.g., a first passivation layer 133 and a second passivation layer 137). For example, the dielectric layer may include one or more layers formed of silicon nitride, silicon oxide, silicon oxynitride, similar materials, or a combination thereof. In some embodiments, the first passivation layer 133 may be a nitride, and the second passivation layer 137 may be an oxide. Each of the dielectric layers may be formed using a suitable process (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), similar processes, or a combination thereof). In some embodiments, a first passivation layer 133 is formed on the interconnect structure 121, and one or more openings are formed in the first passivation layer 133. The first passivation layer 133 may include one or more layers formed of one or more materials. The openings in the first passivation layer 133 may be formed using suitable photolithography and etching processes. Openings are formed to expose portions of the conductive material of the interconnect structure 121 for electrical connection.

[0031] According to some embodiments, metal pads 135 are formed over first passivation layer 133. Additionally, metal pads 135 may be formed extending through openings in first passivation layer 133 to electrically connect to the conductive material of interconnect structure 121. In some embodiments, metal pads 135 may be formed by first depositing a blanket layer of a conductive material, such as aluminum. For example, a layer of aluminum may be deposited over first passivation layer 133, the openings, and the exposed conductive material of interconnect structure 121 using CVD, PVD, or the like. A photoresist layer (not shown separately) may then be formed over the aluminum layer, and the aluminum layer may be etched to form metal pads 135. Metal pads 135 formed of aluminum in this manner may be referred to as "aluminum pads."

[0032] In some embodiments, the metal pad 135 is formed by first forming a seed layer (not shown separately) on the first passivation layer 133 and the opening. For example, the seed layer may be a metal layer including one or more layers that may be formed of different materials. The seed layer may be formed using, for example, PVD or a similar process. A photoresist is formed on the seed layer and patterned, and a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. In some embodiments, the conductive material may be formed using a plating process (e.g., using an electroplating or electroless plating process or a similar plating process). The conductive material may include one or more materials, such as copper, titanium, tungsten, gold, cobalt, a similar material, or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed using, for example, a suitable ashing or stripping process (e.g., using oxygen plasma or the like). Once the photoresist is removed, an acceptable etching process (e.g., a wet etching process or a dry etching process) may be used to remove the remaining exposed portion of the seed layer. The remaining portion of the seed layer and the conductive material form the metal pad 135. As shown, in some embodiments, the via portion 135V of the metal pad 135 extends through the opening in the first passivation layer 133 to contact the conductive material of the interconnect structure 121. In other embodiments, other techniques may be used to form the metal pad 135, and all such techniques are considered to be within the scope of the present disclosure. In some embodiments, the via portion 135V may be first formed through the first passivation layer 133, and then the metal pad 135 may be formed on the first passivation layer 133 and the via portion 135V. As such, the via portion 135V and the metal pad 135 may be formed of the same or different materials.

[0033] In some embodiments, some of the metal pads 135 electrically connected to the interconnect structure 121 may be used as test pads before additional processing steps are performed. For example, the metal pads 135 may be probed as part of a wafer-acceptance-test, a circuit test, a known good die (KGD) test, or the like. Probing may be performed to verify the functionality of active devices or passive devices of the active layer 107 or various electrical connections within the integrated circuit. For example, probing may be performed by contacting a probe needle (not shown separately) to the metal pads 135.

[0034] In some embodiments, the conductive material of the metal pad 135 may be different from the conductive material of the interconnect structure 121. For example, the metal pad 135 may be aluminum, and the conductive material of the interconnect structure 121 may be copper, but other conductive materials may also be used.

[0035] Still refer to Figure 6, a second passivation layer 137 is formed on the first passivation layer 133 and the metal pad 135. The second passivation layer 137 may be formed of one or more layers of one or more dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, similar materials, or combinations thereof). In some embodiments, the second passivation layer 137 may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), similar materials, or combinations thereof. The second passivation layer 137 may be formed using a deposition process such as CVD, PECVD, PVD, ALD, similar processes, or combinations thereof. In some embodiments (not specifically shown), the second passivation layer 137 may be formed to have a thickness greater than the thickness of the metal pad 135, so that the material of the second passivation layer 137 laterally surrounds and covers the top surface of the metal pad 135, and so that the second passivation layer 137 can be planarized without exposing the metal pad 135.

[0036] Figure 6 Also shown as part of the fabrication process of the first optical interposer 100, a region 145 within the interconnect structure 121 and the metal pad layer 131 remains free of conductive features (e.g., free of conductive material of the interconnect structure 121 and the metal pad 135) and optical components (e.g., free of optical component 109 or any other optical component within the interconnect structure 121). As shown, in one embodiment, the region 145 is located directly above the grating coupler 109G. The dielectric layer of the interconnect structure 121 and the corresponding portions of the metal pad layer 131 are subsequently removed and replaced with a uniform dielectric material that is transparent to optical signals (e.g., at least a desired range of optical wavelengths) (see Figure 8 As such, region 145 is formed by not placing an optical component or conductive material directly over grating coupler 109G in a corresponding layer.

[0037] Figure 7 An opening 151 is shown formed in region 145 and further through active layer 107 to expose grating coupler 109G. For example, material is removed from second passivation layer 137, first passivation layer 133, dielectric layer of interconnect structure 121, and optionally second insulating layer 115 to grating coupler 109G. In an embodiment, the removal of material may be performed using, for example, an anisotropic etching process, an isotropic etching process, or a combination thereof. For example, the etching process may include one or more reactive ion etching processes. However, any suitable removal process or combination of removal processes may be used. In some embodiments (not specifically shown), the opening may have a shallow depth, wherein grating coupler 109G remains covered by some of the dielectric layers in the lower dielectric layer of second insulating layer 115 and interconnect structure 121.

[0038] Figure 8 The opening 151 is shown filled with a dielectric fill layer 153. In some embodiments, the dielectric fill layer 153 may be an oxide or nitride that is transparent to an optical signal at a desired wavelength or wavelength range (e.g., a desired range of light wavelengths). For example, the dielectric fill layer 153 may be a continuous dielectric region, such as a continuous oxide region. For example, the dielectric fill layer 153 may be formed of TEOS, PSG, BSG, BPSG, FSG, similar materials, or a combination thereof. The dielectric fill layer 153 may be formed using a deposition process such as CVD, PECVD, PVD, ALD, a similar process, or a combination thereof. Although not specifically shown, in some embodiments, the opening 151 may be formed before the second passivation layer 137 is deposited, and the dielectric fill layer 153 may be formed simultaneously with the second passivation layer 137 and be formed of the same material as the second passivation layer 137.

[0039] As described above, in some embodiments (not specifically shown), the opening 151 (see Figure 7 ) and the dielectric filling layer 153 may extend to a depth that does not reach the grating coupler 109G. In this way, other layers such as some of the dielectric layers of the interconnect structure 121 and the second insulating layer 115 may remain sandwiched between the dielectric filling layer 153 and the grating coupler 109G. It should be noted that these other layers are thin enough (and may be transparent or semi-transparent materials) to allow optical signals to pass between the dielectric filling layer 153 and the grating coupler 109G (see Fig.15 ).

[0040] Fig. 91. As shown, once the metal pads 135 have been formed and the dielectric fill layer 153 has been deposited (e.g., and optionally, after the first optical interposer 100 has undergone initial testing), the first carrier substrate 161 is bonded to the first optical interposer 100. In embodiments, a bonding layer 163 along the first optical interposer 100 and the first carrier substrate 161 facilitates bonding. In some embodiments, the bonding layer 163 includes a bonding layer on each of the components that form a dielectric-to-dielectric bond with each other. For example, as described below, a first bonding layer may first be formed over the first optical interposer 100 (e.g., over the second passivation layer 137 and the dielectric fill layer 153), and the first bonding layer may be used to make a dielectric-to-dielectric bond with a second bonding layer disposed along the first carrier substrate 161. Note that in such embodiments, the bonding layers are shown together. In some embodiments, the second passivation layer 137 (and the dielectric fill layer 153) can be used to perform dielectric-to-dielectric bonding with a second bonding layer along the first carrier substrate 161. According to some embodiments, the bonding layers are each formed of a dielectric material such as silicon oxide, silicon nitride, or the like. The bonding layer can be deposited using any suitable method (e.g., CVD, high density plasma chemical vapor deposition (HDPCVD), PVD, ALD, or the like). However, any suitable material and deposition process can be used. However, any suitable method of bonding the first carrier substrate 161 can be used.

[0041] Fig. 9 The substrate 101 is further shown removed to expose the through device via (TDV) 119 and optionally expose the back side of the first insulator layer 103. In some embodiments (not specifically shown), some or all of the first insulator layer 103 may also be removed. In embodiments, a planarization process (e.g., a chemical mechanical polishing (CMP) process, a grinding process, one or more etching processes, combinations of these, or the like) may be used to remove and / or thin the substrate 101 and the first insulator layer 103. However, any suitable method may be used to remove the substrate 101 and / or the first insulator layer 103. The remaining portion of the first insulator layer 103 may be referred to as a dielectric substrate of the first optical interposer 100. As shown, in embodiments, the TDV 119 extends through the active layer 107 and the first insulator layer 103 to provide a fast channel for power, data, and ground through the first optical interposer 100.

[0042] In some embodiments, the backside TDV 169 may be formed by initially forming a backside TDV opening in the first insulator layer 103 to expose some of the optical components 109 of the active layer 107. The backside TDV opening may be formed by applying a suitable photoresist (not shown) and developing the photoresist and removing the exposed portions of the first insulator layer 103.

[0043] Once the backside TDV opening has been formed in the first optical interposer 100, the backside TDV opening may be lined with a liner. The liner may be, for example, an oxide or silicon nitride formed from TEOS, but any suitable dielectric material may alternatively be used. The liner may be formed using a PECVD process, but other suitable processes (such as physical vapor deposition or thermal processes) may alternatively be used.

[0044] Once the liner has been formed along the sidewalls and bottom of the backside TDV opening, a barrier layer (also not shown separately) may be formed, and the remaining portion of the backside TDV opening may be filled with a first conductive material. The first conductive material may include copper, but may be other suitable materials such as aluminum, alloys, doped polycrystalline silicon, combinations thereof, and the like. The first conductive material may be formed by electroplating copper onto a seed layer (not shown), filling and overfilling the backside TDV opening. Once the backside TDV opening has been filled, the excess liner, barrier layer, seed layer, and first conductive material outside the backside TDV opening may be removed by a planarization process such as CMP, but any suitable removal process may be used. In this way, the remaining conductive material forms the backside TDV 169.

[0045] Optionally, in some embodiments (not specifically shown), once the substrate 101 and the first insulator layer 103 have been removed, an active layer of a backside optical component may be formed on the backside of the active layer 107 (or, for example, the first insulator layer 103 if present). For example, the backside optical component may be formed using similar materials and similar processes as the optical component of the interconnect structure 121 described above. The backside optical component may be directly electrically coupled to the optical component 109 of the active layer 107 via a backside TDV, or directly electrically coupled to the interconnect structure 121 via a TDV 119.

[0046] Additionally, optionally (not specifically shown), a backside interconnect structure or a rewiring structure electrically connected to TDV 119 and backside TDV 169 may be formed. In an embodiment, the backside interconnect structure may be formed as described above with respect to interconnect structure 121 (e.g., alternating layers of dielectric material and conductive material formed using a damascene process, a dual damascene process, or the like). In other embodiments, a plating process may be used to form the backside interconnect structure to form and shape the conductive material, and the conductive material may then be covered with a dielectric material. However, any suitable structure and manufacturing method may be utilized.

[0047] Fig.10 1, once the substrate 101 has been removed and the TDV 119 has been exposed (and optionally, the backside TDV 169 has been formed), a first bonding layer 171 is formed over the TDV 119 and the first insulator layer 103. In an embodiment, the first bonding layer 171 can then be used to perform dielectric-to-dielectric bonding and metal-to-metal bonding (see Fig.12 According to some embodiments, the first bonding layer 171 is formed of a first dielectric bonding material (e.g., silicon oxide, silicon nitride, or the like). The first dielectric bonding material 175 may be deposited using any suitable method (e.g., CVD, HDPCVD, PVD, ALD, or the like). However, any suitable material and deposition process may be used.

[0048] Once the first dielectric bonding material 175 has been formed, a first opening is formed in the first dielectric bonding material 175 to expose the underlying TDV 119 and the backside TDV 169 to form a first bonding pad 173 in the first bonding layer 171. Once the first opening has been formed in the first dielectric bonding material 175, the first opening may be filled with a seed layer and a plate metal to form a first bonding pad 173 in the first dielectric bonding material 175. The seed layer may be blanket deposited on the top surface of the first dielectric bonding material 175, the exposed conductive portion of the underlying layer, and the sidewalls of the opening and the second opening. In some embodiments, the seed layer may include a copper layer. The seed layer may be deposited using processes such as sputtering, evaporation, PECVD, or the like depending on the desired material. The plate metal may be deposited on the seed layer by a plating process such as electroplating or electroless plating. The plate metal may include copper, a copper alloy, or the like. For example, the plate metal may be a filler material. A barrier layer (not shown separately) may be blanket deposited on the top surface of the first dielectric bonding material 175 and the sidewalls of the opening and the second opening before the seed layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. After filling the first opening, a planarization process such as CMP is performed to remove excess portions of the seed layer and the plate metal, thereby forming the first bonding pad 173 in the first bonding layer 171.

[0049] Still refer to Fig.10 , the process for forming the first bonding pad 173 may include forming a reflection pad 174 in the first dielectric bonding material 175. The reflection pad 174 is used to reflect the optical signal to or from the grating coupler 109G. In an embodiment, the reflection pad 174 is directly located above the grating coupler 109G. In various embodiments, the reflection pad 174 may have a width that is substantially the same as or greater than the footprint of the grating coupler 109G or the footprint of the dielectric fill layer 153 (e.g., overlapping in a plan view).

[0050] Additionally, the first bonding layer 171 may also include additional optical components (not specifically shown) bonded to the first bonding layer 172. In such embodiments, the additional optical components may be fabricated using similar methods and materials as any of the optical components described above, such as by being fabricated as waveguides and other structures formed at least in part through deposition and patterning processes, prior to depositing the first dielectric bonding material 175. However, any suitable structures, materials, and any suitable fabrication methods may be utilized.

[0051] Fig.11 The first semiconductor device 200 to be bonded to the first optical interposer 100 is shown (see FIG. Fig.12 ). In some embodiments, first semiconductor device 200 may include an electronic integrated circuit (EIC—e.g., a device without optical devices), and may include semiconductor substrate 203, active device layer 205 (e.g., an electronic device layer), and overlying interconnect structure 207. In embodiments, semiconductor substrate 203 may be similar to substrate 101 (e.g., a semiconductor material such as silicon or silicon germanium in wafer form), active device 205 may include transistors, capacitors, resistors, and the like formed on semiconductor substrate 203, and interconnect structure 207 may be similar to interconnect structure 121 (albeit without optical components). However, any suitable device may be utilized.

[0052] In some embodiments, the first semiconductor device 200 may be configured to work with the first optical interposer 100 to achieve the desired functionality. In some embodiments, the first semiconductor device 200 may be a logic die, a high bandwidth memory (HBM) module, a heterogeneous processing unit (xPU), a three-dimensional integrated circuit (3DIC) die, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC) die, a micro-electromechanical system (MEMS) die, a combination of these, or the like. Any suitable device having any suitable functionality may be used, and all such devices are fully intended to be included within the scope of the embodiments.

[0053] Fig.11 Further shown are metal pads 211, bonding pad vias 215, and second bonding layer 225 (e.g., including second dielectric bonding material 229 and second bonding pad 227) electrically connected to the interconnect structure 207 according to some embodiments. As shown, the structure may also include a third passivation layer 209 and a fourth passivation layer 213 disposed around the metal pad 211. For example, the third passivation layer 209, the metal pad 211 (e.g., including via portion 211V), and the fourth passivation layer 213 may be formed using similar methods and similar materials as the first passivation layer 133, the metal pad 135, and the second passivation layer 137 described above, respectively. In some embodiments, the fourth passivation layer 213 having a greater thickness is deposited on the metal pad 211, and a bonding pad via 215 is formed through the fourth passivation layer 213 and the third passivation layer 209 to electrically connect to the interconnect structure 207. Furthermore, the second bonding layer 225 (eg, the second dielectric bonding material 229 and the second bonding pads 227 ) may be formed using similar methods and similar materials as the first bonding layer 171 (eg, the first dielectric bonding material 175 and the first bonding pads 173 ).

[0054] According to some embodiments, after forming the metal pad 211 and the fourth passivation layer 213, the bonding pad via 215 may be formed by initially forming an opening to the conductive feature of the interconnect structure 207 and / or to the metal pad 221. Acceptable photolithography and etching techniques may be used to form the opening. For example, the photolithography process may include forming a photoresist (not shown) on the fourth passivation layer 213, patterning the photoresist to correspond to the desired opening, extending the opening through the fourth passivation layer 213 and the third passivation layer 209 to expose the interconnect structure 207, and then removing the photoresist.

[0055] According to some embodiments, a bonding pad via 215 is then formed in the opening. As shown, the bonding pad via 215 may have a tapered profile, such as a linear tapered or a concave tapered. In some embodiments, forming the bonding pad via 215 includes first forming a barrier layer (not separately shown) within the opening. The barrier layer may be, for example, a liner, a diffusion barrier, an adhesion layer, or the like. The barrier layer may include one or more layers comprising titanium, titanium nitride, tantalum, tantalum nitride, similar materials, or combinations thereof. The barrier layer may be deposited as a blanket layer over the dielectric layer 122 and within the opening. The barrier layer may be formed using a deposition process, such as CVD, PECVD, PVD, similar processes, or combinations thereof.

[0056] Forming the bonding pad via 215 may include depositing a conductive material on the barrier layer. The conductive material may include cobalt, copper, copper alloy, titanium, silver, gold, tungsten, aluminum, nickel, similar materials or combinations thereof. The conductive material of the bonding pad via 215 may be formed using a deposition process such as CVD, PECVD, PVD, similar processes or combinations thereof. In some embodiments, the conductive material of the bonding pad via 215 is formed by depositing a seed layer (not shown) on the barrier layer, the seed layer may include copper, copper alloy, titanium or similar materials, and then filling the remaining portion of the opening using, for example, a plating process, an electroless plating process or a similar process. After forming the conductive material, a planarization process (such as a grinding process, a CMP process or a similar process) may be performed to remove excess material from the surface of the fourth passivation layer 213. The remaining barrier layer and the conductive material thus form the bonding pad via 215. In this way, the bonding pad via 215 can be formed using a single damascene process.

[0057] Fig.11 It is further shown that a second bonding layer 225 is formed on the interconnect structure 207 and the bonding pad via 215, similar to that described above in conjunction with the first bonding layer 171. In an embodiment, the second bonding layer 225 is used to perform dielectric-to-dielectric bonding and metal-to-metal bonding with the first dielectric bonding material 175. According to some embodiments, the second bonding layer 225 is formed of a second dielectric bonding material 229 (e.g., silicon oxide, silicon nitride, or the like). The second dielectric bonding material 229 can be deposited using any suitable method (e.g., CVD, HDPCVD, PVD, ALD, or the like). In addition, an opening is formed in the second dielectric bonding material 229, and a second bonding pad 227 is formed in the opening. The second bonding pad 227 may include a suitable seed layer formed by sputtering, evaporation, PECVD, or the like, and the filling material (e.g., plate metal) may include copper, copper alloy, or the like formed by electroplating or electroless plating. In some embodiments, the second bonding pad 227 may further include a barrier layer including titanium, titanium nitride, tantalum, tantalum nitride, or the like. However, any suitable material and deposition process may be used to form the second bonding layer 225 .

[0058] Additionally, the support substrate 201 may be attached to the semiconductor substrate 203 using, for example, an adhesive (not separately shown). Additionally, in some embodiments, the support substrate 201 may be bonded using, for example, a bonding process. Any suitable method of attaching the support substrate 201 may be used.

[0059] In some embodiments, a singulation process is performed along the scribe line groove area (not specifically labeled) to separate adjacent EICs of the first semiconductor device 200. The singulation process may include a dicing process, a sawing process, a laser process, the like, or a combination thereof. In some embodiments, similar to the above, the singulated EICs that are probed and found to be known good dies (KGDs) are used in subsequent process steps to form an optical package, such as a compact universal photonic engine (COUPE).

[0060] Figures 12 to 15 The first semiconductor device 200 is shown bonded to the first optical interposer 100 to form a first optical package 300. As described above and discussed in more detail below, after bonding these components, the first optical package 300 may be subsequently processed to form, for example, a COUPE device.

[0061] Fig.12 The first semiconductor device 200 (e.g., an EIC device singulated from a wafer) is shown bonded to the first optical interposer 100 (e.g., a PIC device that remains as part of a wafer). In other embodiments, the first semiconductor device 200 may remain as part of a wafer, while the first optical interposer 100 is first singulated from its wafer. In other embodiments, both the first semiconductor device 200 and the first optical interposer 100 may remain in wafer form for the bonding process.

[0062] As shown, the first semiconductor device 200 and the first optical interposer 100 are bonded in a front-to-back layout. For example, the second bonding layer 225 along the front side of the first semiconductor device 200 is bonded to the first bonding layer 171 along the back side of the first optical interposer 100. According to various embodiments, the second bonding layer 225 and the first bonding layer 171 can be bonded using dielectric-to-dielectric bonding and metal-to-metal bonding processes. However, any other suitable bonding process may also be used.

[0063] In a specific embodiment of a dielectric-to-dielectric bonding and metal-to-metal bonding process, the process can be started by activating the surface of the first bonding layer 171 and the second bonding layer 225. As an example, the activation of the top surface of the first bonding layer 171 and the second bonding layer 225 may include dry processing, wet processing, plasma processing, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, a combination thereof, or a similar processing method. In an embodiment using a wet process, for example, an RCA cleaning process may be used. In some embodiments, the activation process may include other types of processing. The activation process helps to bond the first bonding layer 171 to the second bonding layer 225.

[0064] After the activation process, the first optical interposer 100 and the first semiconductor device 200 may be cleaned using, for example, a chemical rinse, and then aligned and placed in physical contact with the first optical interposer 100 in a chip-to-wafer alignment process. The first optical interposer 100 and the first semiconductor device 200 are then subjected to heat treatment and contact pressure to bond the first optical interposer 100 to the first semiconductor device 200. For example, the first optical interposer 100 and the first semiconductor device 200 may be subjected to a pressure of about 200 kPa or less and a temperature between about 25° C. and about 250° C. to fuse the first semiconductor device 200 to the first optical interposer 100. The first optical interposer 100 and the first semiconductor device 200 may then be subjected to a temperature at or above the eutectic point of the materials of the first bonding pad 173 and the second bonding pad 227 (e.g., between about 150° C. and about 650° C.) to fuse the metals. In this manner, the first optical interposer 100 and the first semiconductor device 200 form a dielectric-to-dielectric bonded and metal-to-metal bonded device. In some embodiments, the bonded device is subsequently baked, annealed, pressed, or otherwise processed to strengthen the bond or complete the bond.

[0065] In addition, although the above description describes dielectric-to-dielectric and metal-to-metal bonding processes, this is intended to be illustrative and not intended to be limiting. In yet other embodiments, the first optical interposer 100 may be bonded to the first semiconductor device 200 by metal-to-metal bonding or another bonding process. For example, the first semiconductor device 200 and the first optical interposer 100 may be bonded by metal-to-metal bonding achieved by fusing conductive components. Any suitable bonding process may be utilized, and all such methods are fully intended to be included within the scope of the embodiments.

[0066] As shown, in some embodiments, the first semiconductor device 200 may not have corresponding second bonding pads 227 aligned with the reflective pads 174 along the first optical interposer 100 to form a metal-to-metal bond. Therefore, the reflective pads 174 may remain electrically isolated from the first semiconductor device 200 and the integrated circuit system of the first optical interposer 100. For example, due to the small width of the first semiconductor device 200, the first semiconductor device 200 may not have components overlapping with the reflective pads 174 along the first optical interposer 100. In some embodiments (not specifically shown), the first semiconductor device 200 may overlap with the reflective pads 174, so that the second dielectric bonding material 229 along the first semiconductor device 200 physically contacts the entire outermost surface of the reflective pads 174. Similarly, one of the second bonding pads 227 along the first semiconductor device 200 may be a dummy pad and is aligned to form a metal-to-metal bond with the reflective pad 174 in the above process.

[0067] Fig.13 Gap filling material 303 is shown formed on and around the first semiconductor device 200. For example, according to some embodiments, gap filling material 303 may be formed on and around the exposed surfaces of the first optical interposer 100 and the exposed surfaces of the first semiconductor device 200. As shown, in some embodiments, before depositing the gap filling material 303, a liner layer 301 may be first deposited on the structure. For example, the liner layer 301 may be formed of a dielectric material having good adhesion to the first optical interposer 100 and the first semiconductor device 200. In some embodiments, the liner layer 301 is formed of a nitride-containing material (e.g., silicon nitride) or an oxide-containing material (silicon oxide). The liner layer 301 may be conformally deposited by a deposition process such as ALD, CVD, or a similar process.

[0068] The gap filling material 303 may be formed of a material different from that of the liner layer 301. In some embodiments, the gap filling material 303 may be formed of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, PSG, BSG, BPSG, or similar materials. For example, the gap filling material 303 may be formed of any of the above oxide-containing materials (e.g., silicon oxide). The gap filling material 303 may be formed using CVD, HDPCVD, flowable CVD, spin coating, or similar processes. The gap filling material 303 may fill the remaining portion of the space between adjacent first semiconductor devices 200. After the liner layer 301 and the gap filling material 303 are deposited, a planarization process (e.g., CMP, a grinding process, an etch-back process, a similar process, or a combination thereof) is performed to remove excess portions of the liner layer 301 and the gap filling material 303, thereby exposing the supporting substrate 201 of the first semiconductor device 200. In some embodiments, the planarization process may include thinning the support substrate 201 to achieve a desired thickness dimension of the first semiconductor device 200 (eg, the first optical package 300). After the planarization process, the first semiconductor device 200, the gap filling material 303, and the liner layer 301 may have substantially flat surfaces.

[0069] Fig.14 As shown, once the gap filler material 303 has been formed, a second carrier substrate 311 is bonded over the first semiconductor device 200 and the first carrier substrate 161 is removed. In an embodiment, a bonding layer 313 is disposed along the second carrier substrate 311 to form a bond with the gap filler material 303 and / or the first semiconductor device 200 (if exposed). For example, the bonding layer 313 can be formed using similar materials and processes as the adhesive layer 163 (or using one or more bonding layers), similar to what is discussed above in connection with bonding the first carrier substrate 161 to the first optical interposer 100. In some embodiments (not specifically shown), the bonding layer 313 includes a plurality of dielectric layers, wherein another bonding layer is first formed along the gap filler material 303 and the support substrate 201 to facilitate dielectric-to-dielectric bonding between the respective bonding layers 313. In addition, various types of bonding between these components can also be implemented similarly to what is discussed above in connection with bonding the first carrier substrate 161 to the first optical interposer 100.

[0070] In an embodiment, the first carrier substrate 161 is removed using a planarization process (e.g., a chemical mechanical polishing process, a grinding process, one or more etching processes, a combination of these processes, or the like). However, any suitable method may be used to remove the first carrier substrate 161. As shown, the adhesive layer 163 (or one or more of the bonding layers) may remain along the first optical interposer 100 and be exposed after the first carrier substrate 161 is removed. In some embodiments (not specifically shown), the adhesive layer 163 is also removed, and the second passivation layer 137 and the dielectric fill layer 153 are exposed.

[0071] Fig.15 1 shows that, according to some embodiments, an external connector layer 321 including a dielectric layer 325 and an external connector is formed on the first optical interposer 100 of the first optical package 300. For example, the dielectric layer 325 is deposited on the second passivation layer 137 (or the adhesive layer 163 (if present)) and the dielectric filler layer 153. In some embodiments, the dielectric layer 325 is formed of a photosensitive material (e.g., polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or a similar material) that can be patterned using a lithography mask. The dielectric layer 325 can be formed by spin coating, lamination, CVD, a similar process, or a combination thereof. The dielectric layer 325 is then patterned. The patterning forms an opening that exposes a portion of the metal pad 153. The patterning may be performed by an acceptable process, such as by exposing the dielectric layer 325 to light and developing it when the dielectric layer 325 is a photosensitive material, or by etching using, for example, anisotropic etching.

[0072] External connectors are then formed in the openings and may include under bump metal (UBM) 331 and conductive connector 333. In some embodiments, UBM 331 has a main body portion located on and extending along the main surface of dielectric layer 325, and has a via portion extending through dielectric layer 325 to physically and electrically couple to the integrated circuit system (e.g., metal pad 135 and / or interconnect structure 121). UBM 331 may be formed of the same material as the conductive material of metal pad 135 and / or interconnect structure 121.

[0073] UBM 331 may include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, those skilled in the art will recognize that there are many suitable arrangements of materials and layers suitable for forming UBM 331, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that can be used for UBM 331 is fully intended to be included within the scope of the embodiments.

[0074] In an embodiment, UBM 331 is fabricated by forming each layer over metal pad 135 and interconnect structure 121. Formation of each layer may be performed using a plating process such as electrochemical plating, but other formation processes such as sputtering, evaporation, or PECVD processes may alternatively be used depending on the desired material.

[0075] Conductive connectors 333 are formed on UBM 331. Conductive connectors 333 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel palladium immersion gold technology (ENEPIG), or similar devices. Conductive connectors 333 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or combinations thereof. In some embodiments, conductive connectors 333 are formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball planting, or a similar process. Once a solder layer has been formed on the structure, reflow may be performed to shape the material into a desired bump shape. In another embodiment, conductive connectors 333 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or a similar process. The metal pillars may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillars. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, similar materials or combinations thereof and may be formed by a plating process.

[0076] Fig.15 As further shown, after forming external connectors (e.g., UBM 331 and conductive connector 333), the dielectric layer 325 can be further patterned to form an opening 341 to the dielectric fill layer 153. In addition, an optical fiber 345 used as an optical input / output port to the first optical intermediary 100 can be attached at the opening 341. In an embodiment, the optical fiber 345 is positioned to optically couple the optical fiber 345 with an optical input (e.g., grating coupler 109G) located within the first optical intermediary 100. By positioning the optical fiber 345 to be optically connected to the grating coupler 109G, the optical signal leaving the optical fiber 345 is directed to the optical components of the first optical intermediary 100. Similarly, the optical fiber 345 is positioned so that the optical signal leaving the first optical intermediary 100 is directed to the optical fiber 345 for transmission. However, any suitable position may also be utilized.

[0077] According to some embodiments, optical fiber 345 may be held in place using, for example, optical glue 347 disposed in opening 341 and along dielectric filler layer 153. In some embodiments, optical glue 347 includes a polymer material such as epoxy acrylate oligomer, and may have a refractive index between about 1 and about 3. However, any suitable material or method of securing optical fiber 345 may be utilized.

[0078] Various advantages are achieved through the layout of the first optical package 300. For example, the layout enables external input / output connections for both optical signals (e.g., through the optical fiber 345) and electrical signals (e.g., through the conductive connector 333) to be along the same side of the first optical package 300. In addition, the optical signal between the optical fiber 345 and the grating coupler 109G can travel a shorter distance through a portion of the thickness of the first optical interposer 100 than through a longer distance through the entire thickness of the second carrier substrate 311, the first semiconductor device 200 (e.g., the gap filler material 303), and the first bonding layer 171 and the second bonding layer 225. As further shown, the optical fiber 345 can be directed into the first optical package 300 without a lens (for comparison, see Fig.21 In addition, the first optical interposer 100 may be formed without a backside redistribution structure and a passivation layer, which reduces the total thickness of the first optical interposer 100 and the first optical package 300.

[0079] Although not specifically shown, the first optical package 300 can then be singulated and attached to a package substrate (e.g., a printed circuit board (PCB)) to be incorporated into a semiconductor package or electronic device. For example, the conductive connector 333 can be electrically coupled to the conductive features along the package substrate. Due to the location of the opening 341 in the dielectric layer 325, the edge of the package substrate can stop without the opening 341, or the package substrate can be configured to replace the optical glue 347 or use the optical glue 347 in combination to help fix the optical fiber 345 relative to the opening 341.

[0080] For example, once the first optical package 300 has been formed, the first optical package 300 may be attached to an interposer substrate for coupling the first optical package 300 with other devices to form, for example, a chip-on-wafer-on-substrate (Chip-on-wafer-on-substrate). In an embodiment, the interposer substrate includes a semiconductor substrate, an interconnect structure, a through-hole, and external connectors for bonding and electrically connecting to other devices.

[0081] Figures 16 to 216. and related discussions refer to embodiments in which the second optical interposer 400 and the second semiconductor device 500 are combined to form a second optical package 600. Unless otherwise noted, these embodiments of the second optical package 600 may be formed similarly and approximately as described above in conjunction with the first optical package 300. Additionally, the second optical interposer 400 and the second semiconductor device 500 may be formed similarly as described above in conjunction with the first optical interposer 100 and the first semiconductor device 200, respectively. As discussed in more detail below, the formation and structure of the second optical package 600 may differ from the formation and structure of the first optical package 300 due to changes associated with conditioning signals transmitted to and received from an optical fiber that is located on an opposite side of the second optical package 600 as compared to the first optical package 300.

[0082] Fig.16 After forming the opening 151 (see Figure 7 ) A second optical interposer 400 is formed similarly to the intermediate stage of the first optical interposer 100. Similarly, according to some embodiments, an opening is optionally formed through the region 145, which can expose the grating coupler 109G. The opening is filled with a reflective pad 401, and a dielectric filling layer 403 is formed in the opening.

[0083] For example, the reflection pad 401 may be a near-end reflection pad 401A formed at a position close to the grating coupler 109G, or the reflection pad 401 may be a remote reflection pad 401B formed at a greater distance from the grating coupler 109G. However, the reflection pad 401 may be formed at any suitable distance relative to the grating coupler 109G. In the embodiment where the opening is completely filled with the dielectric filling layer 403, in a subsequent step, a reflection pad is formed on the grating coupler 109G (see Fig. 20 ).

[0084] According to an embodiment, the dielectric filling layer 403 is formed in multiple steps. For example, the dielectric filling layer 403 can be formed in the opening above and around the grating coupler 109G, similar to the dielectric filling layer 153 described above in conjunction with the first optical interposer 100 (see Figure 8 ). The dielectric filling layer 403 may then be planarized to be flush with the surface of the second optical interposer 400 and recessed to a desired depth for the reflective pad 401. The reflective pad 401 is then formed by depositing a conductive material in the recess using a plating process such as electroplating or electroless plating or the like. The conductive material may include a reflective metal (e.g., copper), however, any suitable reflective material or combination of materials (e.g., alloys) may be used.

[0085] If desired, after forming the reflection pad 401, the remaining portion of the opening may be refilled with the dielectric filling layer 403. As shown, in an embodiment where the proximal reflection pad 401A is formed in the opening, the dielectric filling layer 403 will include two portions. That is, the dielectric filling layer 403 will include a proximal dielectric filling layer 403A and a remote dielectric filling layer 403B located on opposite sides of the proximal reflection pad 401A. In some embodiments, the remote reflection pad 401B may be formed at the top of the opening so that the additional component of the dielectric filling layer 403 is not required to fill any remaining portion of the opening above the reflection pad 401. After the upper portion of the opening is filled with reflective material, a planarization process may be performed to remove excess reflective material from the upper surface of the optical interposer (e.g., the metal pad layer 131). As a result, the remote reflection pad 401B will have a surface flush with the metal pad layer 131.

[0086] Fig.17 The subsequent process performed on the second optical intermediary layer 400 is shown, which is similar to that described above in conjunction with the first optical intermediary layer 100. For example, the first carrier substrate 161 is attached and the substrate 101 is removed from the second optical intermediary layer 400 (see Fig. 9 ). In addition, TDV 119 may be exposed, and backside TDV 169 may be formed to electrically connect optical component 109 and interconnect structure 121 to the backside of second optical interposer 400 (see Fig. 9 ). In addition, a first bonding layer 171 electrically connected to the TDV 119 and the backside TDV 169 may then be formed on the TDV 119 and the backside TDV 169 (see Fig.10 ).

[0087] Fig.18 A second semiconductor device 500 is shown that is formed similarly to that described above in connection with the first semiconductor device 200. In some embodiments, the second semiconductor device 500 may be an EIC device formed at the wafer level. As discussed in more detail below, the second semiconductor device 500 may be singulated from the wafer form and bonded to a second optical interposer to form a second optical package 600.

[0088] Fig.19 The second semiconductor device 500 (e.g., an EIC device singulated from a wafer) is shown bonded to the second optical interposer 400 (e.g., a PIC device that remains as part of the wafer). In addition, a gap filler material 603 (e.g., optionally including a liner layer 601) is formed on and around the exposed surfaces of the second optical interposer 400 and the exposed surfaces of the second semiconductor device 500, similar to the gap filler material 303 (and liner layer 301) described above in conjunction with forming the first optical package 300 (see Fig.13), unless otherwise specified below. In addition, the second carrier substrate 311 is attached to the first semiconductor device 200 and the first carrier substrate 161 is removed, similar to the above description in conjunction with the first optical package (see Fig.14 Similarly, a bonding layer 313 is disposed along the second carrier substrate 311 to form a bond with the gap filling material 303 and / or the second semiconductor device 500 (if exposed).

[0089] According to some embodiments, the gap filling material 603 and the liner layer 601 are formed so that light of a desired wavelength range can pass through these layers to the grating coupler 109G. In the embodiment shown, the liner layer 601 can be patterned or deposited to have an opening 605 directly above the grating coupler 109G. In some embodiments, the liner layer 601 is formed of a material that is transparent or translucent to the desired range of wavelengths and / or is deposited thin enough to be substantially transparent and / or sufficiently transparent. Furthermore, in some embodiments, the gap filling material 603 can be formed around the second semiconductor device 500, and the deposition of the liner layer 601 can be omitted.

[0090] Fig. 20 An external connector layer 621 including a dielectric layer 625 and external connectors (eg, UBM 631 and conductive connector 633) is shown formed on the second optical interposer 400 of the second optical package 600, similar to that described above in conjunction with the first optical interposer 100 of the first optical package 300 (see Fig.15 As further shown in the figure, in some embodiments, the reflective pad 401 may not be formed in the second optical interposer 400, as described above with respect to Fig.16 In such embodiments, the reflection pad 635 may be formed before, after, or simultaneously with the UBM 631. For example, the reflection pad 635 may be formed in the external connector layer 621 simultaneously with the UBM 631 and formed of the same material as that used for the UBM 631. In some embodiments, before or after forming the UBM 631, an opening may be patterned in the dielectric layer 625 of the external connector layer 621, and the reflection pad 635 may be formed similarly as described above in conjunction with the reflection pad 401.

[0091] Fig.21The lens 641 is shown formed within the second carrier substrate 311. In an embodiment, a photosensitive material (not shown separately) may be deposited, exposed, developed, and reflowed to form the desired shape and outline of the lens 641 in the mask. Once the mask exists, the formation of the lens 641 may be performed using, for example, an anisotropic etching process (e.g., reactive ion etching) that uses the mask as a sacrificial mask. Specifically, when the etching process is performed to etch the second carrier substrate 311, the etching process will also etch the material of the mask. As the thinner portions of the mask are removed, additional portions of the second carrier substrate 311 are exposed to the etching process until some, most, or all of the mask is consumed. In this way, the shape of the mask is transferred to the second carrier substrate 311, thereby forming the lens 641 within the second carrier substrate 311. However, any suitable process may be utilized.

[0092] In some embodiments, an anti-reflective coating (ARC) 643 may be formed over the lens 641. In embodiments, the ARC 643 may be one or more material layers that help prevent unwanted reflections when light is focused through the lens 641. In particular embodiments, the one or more material layers may be a material such as silicon oxide, silicon nitride, a combination of these materials, or the like formed using processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, oxidation, nitridation, combinations of these, or the like.

[0093] In a particular embodiment, the ARC 643 may be formed using a first silicon oxide layer and a first silicon nitride layer formed on the first silicon oxide layer. A second silicon oxide layer and a second silicon nitride layer are deposited on the first silicon oxide layer and the first silicon nitride layer to form an alternating stack of silicon oxide and silicon nitride. However, any suitable combination of materials may be utilized. It should also be noted that the lens 641 and the ARC 643 may be formed before or after the second carrier substrate 311 is bonded to the second semiconductor device 500.

[0094] Fig.21Further shown is the placement of an optical fiber 645, which serves as an optical input / output port to a second optical package (e.g., the second optical interposer 400). In an embodiment, the optical fiber 645 is placed to optically couple the optical fiber 645 to an optical input (e.g., a grating coupler 109G) located within the second optical interposer 400. By positioning the optical fiber 645 to be optically connected to the grating coupler 109G, the optical signal exiting the optical fiber 645 is directed through the lens 641, the gap filling material 603 (and the backing layer 601 (if present)) and other components of the second carrier substrate 311, and into the grating coupler 109G of the second optical interposer 400. Similarly, the optical fiber 645 is positioned so that the optical signal exiting the second optical interposer 400 is directed into the optical fiber 645 for transmission. However, any suitable location may also be utilized.

[0095] Optical fiber 645 may be held in place using, for example, optical glue 647. In some embodiments, optical glue 647 includes a polymer material such as epoxy acrylate oligomer, and may have a refractive index between about 1 and about 3. However, any suitable material may be utilized.

[0096] Various advantages are achieved by the layout of the second optical package 600. For example, the layout enables the optical signal between the optical fiber 645 and the grating coupler 109G to travel a short distance through the thickness of the second semiconductor device 500 and a small portion of the thickness of the second optical interposer 400 (e.g., the first bonding layer 171 and the first insulator layer 103), rather than traveling a long distance through the thickness of the second semiconductor device 500 in addition to the majority of the thickness of the second optical interposer 400. As further shown, such a layout enables multiple locations of the reflection pad (e.g., the proximal reflection pad 401A, the remote reflection pad 401B, or the reflection pad 635) depending on manufacturing considerations and convenience.

[0097] It should be noted that although many configurations have been presented in the above description, these precise configurations are intended to be merely illustrative and are not intended to limit the embodiments to these precise configurations. Instead, according to various embodiments, the first optical package 300 or the second optical package 600 may be formed in any suitable configuration, such as a stack of the first semiconductor device 200 or the second semiconductor device 500 and / or a stack of the first optical interposer 100 or the second optical interposer 400. Any suitable configuration may be utilized, and all such configurations are fully intended to be included within the scope of the embodiments.

[0098] By utilizing the above layout of the first optical package 300 and the second optical package 600, various advantages and efficiencies can be achieved in the resulting device. In particular, a greater variety of package layouts enable flexibility in the location of optical input / output signals. In addition, the optical input / output signals can follow a shorter path to or from the grating coupler 109G, which improves the efficiency and reliability of the device. Furthermore, the optical interposers 100, 400 can be thinner without the need for a backside rewiring structure, which can form thinner optical packages 300, 600, respectively.

[0099] In an embodiment, a method includes: forming an optical interposer, forming the optical interposer includes: forming an optical device layer on a front side of a first substrate, the optical device layer including a grating coupler; forming a first interconnect structure on the optical device layer, the first interconnect structure including a conductive feature and a dielectric layer; etching an opening through the dielectric layer to expose the grating coupler; filling the opening with an oxide layer; forming a first bonding layer on a back side of the first substrate, the first bonding layer including a first bonding pad and a first dielectric bonding layer; attaching a semiconductor device to the optical interposer, the semiconductor device including: an active device layer on a front side of a second substrate; a second interconnect structure on the active device layer; and a second bonding layer on the second interconnect structure, the second bonding layer including a second bonding pad and a second dielectric bonding layer; and forming an external connector electrically connected to the first interconnect structure on the first interconnect structure of the optical interposer. In another embodiment, the first bonding layer includes a reflective pad, and wherein the reflective pad overlaps the grating coupler in a plan view. In another embodiment, bonding the semiconductor device includes dielectric-to-dielectric bonding and metal-to-metal bonding. In another embodiment, the first substrate includes a silicon-on-insulator substrate. In another embodiment, the method further includes: forming a device through-hole extending through the optical device layer before forming the first interconnect structure; and removing at least a portion of the back side of the first substrate to expose the device through-hole. In another embodiment, the method further includes: forming a gap fill material above and around the semiconductor device. In another embodiment, the method further includes: bonding a carrier substrate above the semiconductor device, the semiconductor device being sandwiched between the carrier substrate and the optical interposer; and forming a lens in the carrier substrate. In another embodiment, the grating coupler is configured to receive and transmit a range of light wavelengths, and wherein the region extending from the lens to the grating coupler is transparent to the range of light wavelengths.

[0100] In an embodiment, a method includes: forming a device layer on a front side of a first substrate, the device layer including an optical input / output device and an optical waveguide, the optical input / output device being configured to receive a range of wavelengths of light; forming a device through hole extending through the device layer and at least a portion of the first substrate; forming an interconnect structure on the front side of the device layer; forming an opening through the interconnect structure to expose the optical input / output device; depositing an insulating material in the opening, the insulating material being transparent to the range of wavelengths of light; attaching a first carrier over the interconnect structure; exposing the device through hole from a back side of the first substrate; forming a first bonding layer over the exposed device through hole electrically connected to the exposed device through hole; bonding the first bonding layer to an electronic integrated circuit device, the electronic integrated circuit device including a second bonding layer; attaching a silicon substrate over the electronic integrated circuit device; forming an external connector layer over the interconnect structure electrically connected to the interconnect structure; and forming a lens in the silicon substrate, the region extending from the lens to the optical input / output device being transparent to the range of wavelengths of light. In another embodiment, depositing the insulating material comprises: forming a first portion of the insulating material in the opening; forming a first reflective pad on the first portion of the insulating material; and forming a second portion of the insulating material to fill a remaining portion of the opening. In another embodiment, depositing the insulating material comprises: filling the opening with the insulating material; etching the insulating material to form a recess; and filling the recess with a reflective material to form a second reflective pad. In another embodiment, the external connector layer comprises an under bump metal and a third reflective pad. In another embodiment, forming the external connector layer comprises forming the third reflective pad simultaneously with the under bump metal. In another embodiment, the insulating material comprises an oxide.

[0101] In an embodiment, an optical package includes: an optical interposer, the optical interposer including: an external connector layer; a first interconnect structure located on the external connector layer, the first interconnect structure including a conductive feature embedded in a dielectric layer; an active device layer located on the first interconnect structure, the active device layer including a grating coupler; a dielectric substrate located on the active device layer; a first bonding layer located on the dielectric substrate; and a reflective pad, the reflective pad overlapping the grating coupler in a plan view; and a semiconductor device attached to the first bonding layer of the optical interposer, the semiconductor device including a second bonding layer, a second interconnect structure and an electronic device layer. In another embodiment, the conductive feature is not present in the dielectric layer overlapping the grating coupler in the plan view. In another embodiment, the reflective pad is located in the first bonding layer. In another embodiment, the reflective pad is located in the external connector layer. In another embodiment, the dielectric layer includes a continuous oxide region disposed around the grating coupler. In another embodiment, the reflective pad is located in the continuous oxide region.

[0102] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An optical package, characterized in that: include: Optical interposer, comprising: External connector layer; a first interconnect structure located above the external connector layer, the first interconnect structure comprising conductive features embedded in a dielectric layer; an active device layer, located on the first interconnect structure, the active device layer comprising a grating coupler; a dielectric substrate located above the active device layer; A first bonding layer located on the dielectric substrate; and a reflective pad, the reflective pad overlaps the grating coupler in a plan view; and a semiconductor device adhered to the first bonding layer of the optical interposer, the semiconductor device comprising a second bonding layer, a second interconnect structure and an electronic device layer.

2. The optical package according to claim 1, characterized in that: The dielectric layer that overlaps the grating coupler in the plan view does not have the conductive features therein.

3. The optical package according to claim 1, characterized in that: The reflective pad is located in the first bonding layer.

4. The optical package according to claim 1, wherein: The reflective pad is located in the external connector layer.

5. The optical package according to claim 1, wherein: The dielectric layer includes a continuous oxide region disposed around the grating coupler.

6. The optical package according to claim 5, characterized in that: The reflective pad is located in the continuous oxide region.

7. An optical package, characterized in that: include: Optical interposer, comprising: External connector layer; a first interconnect structure located above the external connector layer, the first interconnect structure comprising conductive features embedded in a dielectric layer; an active device layer, located on the first interconnect structure, the active device layer comprising a grating coupler; a dielectric substrate located above the active device layer; A first bonding layer located on the dielectric substrate; and A reflection pad overlaps the grating coupler in a plan view.

8. The optical package according to claim 7, characterized in that: Also includes: A semiconductor device is attached to the first bonding layer of the optical interposer, and the semiconductor device includes a second bonding layer, a second interconnect structure and an electronic device layer.

9. The optical package according to claim 7, characterized in that: The dielectric layer that overlaps the grating coupler in the plan view does not have the conductive features therein.

10. The optical package according to claim 7, characterized in that: The reflective pad is located in the first bonding layer, in the external connector layer, or the dielectric layer includes a continuous oxide region disposed around the grating coupler and the reflective pad is located in the continuous oxide region.

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