Offset circuit

Abstract

The utility model provides an offset circuit, which comprises a power supply module, a first differential pair transistor, a second differential pair transistor and a load module, the power supply module is connected with a power end and provides bias current; the first differential pair transistor is used for receiving the bias current and the differential input voltage and outputting differential current; the second differential pair transistors receive the bias current and the differential reference voltage and output differential bias current; the input end of the load module is connected with the output end of the first differential pair transistor and the output end of the second differential pair transistor so as to receive the current formed by superposing the differential current and the differential bias current, and the connection node of the load module and the differential input pair transistor outputs an output signal. The offset of the differential input voltage is related to the offset of the differential reference voltage, and the offset of the differential input voltage can be adjusted by adjusting the differential reference voltage, so that the offset of the differential input voltage is less affected by process fluctuation, power supply voltage fluctuation and temperature change.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to an offset circuit. Background Art

[0002] In circuits such as comparator circuits or operational amplifier circuits, an offset (offset voltage) is often required between two input terminals to meet specific design requirements or application scenarios.

[0003] At present, the circuit structure that realizes offset between input terminals is very sensitive to changes in factors such as process, supply voltage, and temperature, which makes the offset between input terminals have obvious deviations under different processes, different supply voltages, and different temperatures, and cannot meet the needs. Utility Model Content

[0004] The utility model aims to provide an offset circuit, which is used to solve the problem that the offset between the input ends of the existing offset circuit has obvious large deviation under different processes, different power supply voltages and different temperatures.

[0005] In order to achieve the above object, the utility model provides an offset circuit, comprising:

[0006] A power supply module is connected to the power supply terminal to provide bias current;

[0007] A first differential pair tube receives the bias current and the differential input voltage, and outputs a differential current;

[0008] The second differential pair tube receives the bias current and the differential reference voltage and outputs a differential bias current;

[0009] A load module, wherein an input end of the load module is connected to an output end of the first differential pair of tubes and an output end of the second differential pair of tubes to receive a current obtained by superimposing the differential current and the differential bias current, and a connection node between the load module and the differential input pair of tubes outputs an output signal.

[0010] Optionally, the first differential pair transistor includes a first transistor and a second transistor, and the first ends of the first transistor and the second transistor are connected and then connected to the power supply module;

[0011] The second differential pair transistor comprises a third transistor and a fourth transistor, and the first ends of the third transistor and the fourth transistor are connected and then connected to the power supply module;

[0012] The load module comprises a first load module and a second load module, the first end of the first load module is connected to the second ends of the first transistor and the third transistor, and the second end of the first load module is grounded;

[0013] The second load module has the same specifications as the first load module, a first end of the second load module is connected to the second ends of the second transistor and the fourth transistor, and a second end of the second load module is grounded; and,

[0014] The control ends of the first transistor and the second transistor are connected to a first voltage and a second voltage respectively, the control ends of the third transistor and the fourth transistor are connected to a third voltage and a fourth voltage respectively, and the offset between the first voltage and the second voltage is positively correlated with the offset between the fourth voltage and the third voltage.

[0015] Optionally, the first load module and the second load module are in a mirror relationship, and the load module outputs a single-ended output signal or a double-ended output signal.

[0016] Optionally, both the first load module and the second load module are resistors, and the load modules output double-ended output signals.

[0017] Optionally, the offset circuit is a comparison circuit, the first voltage and the second voltage are input signals of the comparison circuit, and the first end of the second load module outputs a comparison signal.

[0018] Optionally, the first end of the first load module outputs a first output signal, the second end of the second load module outputs a second output signal, and the first output signal and the second output signal are converted into single-ended signals via a double-ended to single-ended circuit.

[0019] Optionally, the offset circuit is an operational amplifier circuit, the first voltage is an input signal of the operational amplifier circuit, and the first end of the second load module is connected to the control end of the second transistor to output an amplified signal.

[0020] Optionally, the transconductances of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same, and when the first terminal voltage of the first load module is equal to the first terminal voltage of the second load module, the offset between the first voltage and the second voltage is equal to the offset between the fourth voltage and the third voltage.

[0021] Optionally, the power supply module includes a fifth transistor, a sixth transistor, a seventh transistor and a current source, the sixth transistor and the seventh transistor have the same specifications, the first ends of the fifth transistor, the sixth transistor and the seventh transistor are connected and then connected to the power supply end, the control ends of the fifth transistor, the sixth transistor and the seventh transistor are connected and then connected to the second end of the fifth transistor and one end of the current source, the other end of the current source is grounded, and the second ends of the sixth transistor and the seventh transistor both output the bias current.

[0022] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all MOS transistors, the first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their sources, the second ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their drains, and the control ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their gates; or,

[0023] The first transistor, the second transistor, the third transistor and the fourth transistor are all triodes, the first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are emitters, the second ends of the first transistor, the second transistor, the third transistor and the fourth transistor are collectors, and the control ends of the first transistor, the second transistor, the third transistor and the fourth transistor are bases.

[0024] Optionally, the first load module includes an eighth transistor, and the second load module includes a ninth transistor. The eighth transistor and the ninth transistor have the same specifications. The first end and the second end of the eighth transistor serve as the second end and the first end of the first load module respectively, and the first end and the second end of the ninth transistor serve as the second end and the first end of the second load module respectively. The second end of the eighth transistor is also connected to its control end and the control end of the ninth transistor.

[0025] The offset circuit provided in the utility model includes a power supply module, a first differential pair of tubes, a second differential pair of tubes and a load module; the power supply module is connected to the power supply end to provide a bias current; the first differential pair of tubes receives the bias current and the differential input voltage and outputs the differential current; the second differential pair of tubes receives the bias current and the differential reference voltage and outputs the differential bias current; the input end of the load module is connected to the output end of the first differential pair of tubes and the output end of the second differential pair of tubes to receive the current after the differential current and the differential bias current are superimposed, and the connection node between the load module and the differential input pair of tubes outputs an output signal. The offset of the differential input voltage is related to the offset of the differential reference voltage, specifically, in a proportional relationship, and the offset of the differential input voltage can be adjusted by adjusting the differential reference voltage, so that the offset of the differential input voltage is less affected by process fluctuations, power supply voltage fluctuations, and temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A circuit diagram of an offset circuit provided in Embodiment 1 of the present utility model;

[0027] Figure 2 A circuit diagram of an offset circuit provided in Embodiment 2 of the present utility model;

[0028] Figure 3 A circuit diagram of an offset circuit provided in Embodiment 3 of the present utility model;

[0029] Wherein, the accompanying drawings are marked as follows:

[0030] 10-power supply module; 11-second differential pair tube; 12-first differential pair tube; 13-first load module; 14-second load module; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; VIN1-first voltage; VIN2-second voltage; VREF1-third voltage; VREF2-fourth voltage; IREF-quiescent current; Ib-bias current; R1-first resistor; R2-second resistor; VOUT1-first output signal; VOUT2-second output signal; VOUT-output signal. DETAILED DESCRIPTION

[0031] The following will describe the specific implementation of the utility model in more detail with reference to the schematic diagram. The advantages and features of the utility model will become clearer according to the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0032] Embodiment 1

[0033] Figure 1 FIG. 1 is a circuit diagram of an offset circuit provided in this embodiment. Figure 1As shown, the offset circuit includes a power supply module 10, a first differential pair of transistors 12, a second differential pair of transistors 11 and a load module. The power supply module 10 is connected to the power supply end to provide a bias current Ib; the first differential pair of transistors 12 receives the bias current Ib and the differential input voltage and outputs a differential current; the second differential pair of transistors 11 receives the bias current Ib and the differential reference voltage and outputs a differential bias current; the input end of the load module is connected to the output end of the first differential pair of transistors and the output end of the second differential pair of transistors to receive the current after the differential current and the differential bias current are superimposed, and the connection node between the load module and the differential input pair of transistors outputs an output signal VOUT. In the utility model, the offset of the differential input voltage is related to the offset of the differential reference voltage, specifically, in proportional relationship. The offset of the differential input voltage can be adjusted by adjusting the differential reference voltage. After the values ​​of the third voltage VREF1 and the fourth voltage VREF2 are determined, the offset between the first voltage VIN1 and the second voltage VIN2 is also fixed, so that the offset of the differential input voltage is less affected by process fluctuations, power supply voltage fluctuations, and temperature changes.

[0034] In this embodiment, the power supply module 10 is an active current mirror, which includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a current source, and the current source is used to provide a static current IREF. The first ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are connected and then connected to the power supply end, the control ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are connected and then connected to the second end of the fifth transistor M5 and one end of the current source, the other end of the current source is grounded, and the second end of the sixth transistor M6 and the second end of the seventh transistor M7 both output a bias current Ib.

[0035] In this embodiment, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all PMOS transistors, the first ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their sources, the second ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their drains, and the control ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their gates. Of course, in some embodiments, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 may also be triodes, in which case the first ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their emitters, the second ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their collectors, and the control ends of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are their bases.

[0036] In this embodiment, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 have the same specifications, and the mirror ratio of the power supply module 10 is 1:1:1. At this time, the quiescent current IREF and the two bias currents Ib are equal, but it should not be limited to this. The mirror ratio of the power supply module 10 can also be other ratios, but it is necessary to ensure that the specifications of the sixth transistor M6 and the seventh transistor M7 are the same, so that the two bias currents Ib are equal.

[0037] The first differential pair 12 includes a first transistor M1 and a second transistor M2. The first ends of the first transistor M1 and the second transistor M2 are connected to the power supply module 10 (specifically, the second end of the seventh transistor M7) to receive the bias current Ib. The control ends of the first transistor M1 and the second transistor M2 are connected to the first voltage VIN1 and the second voltage VIN2 respectively. The second ends of the first transistor M1 and the second transistor M2 output differential current. The first voltage VIN1 and the second voltage VIN2 constitute the differential input voltage, which is usually an external input voltage.

[0038] In this embodiment, the first transistor M1 and the second transistor M2 are both PMOS transistors, the first end of the first transistor M1 and the second transistor M2 are their sources, the second end of the first transistor M1 and the second transistor M2 are their drains, and the control end of the first transistor M1 and the second transistor M2 are their gates. Of course, in some embodiments, the first transistor M1 and the second transistor M2 can also be triodes, in which case, the first end of the first transistor M1 and the second transistor M2 are their emitters, the second end of the first transistor M1 and the second transistor M2 are their collectors, and the control end of the first transistor M1 and the second transistor M2 are their bases.

[0039] It should be noted that, in order to form a differential pair of transistors, the specifications of the first transistor M1 and the second transistor M2 should be equal.

[0040] The second differential pair transistor 11 includes a third transistor M3 and a fourth transistor M4, the first ends of the third transistor M3 and the fourth transistor M4 are connected to the power supply module 10 (specifically, the second end of the sixth transistor M6) to receive the bias current Ib, the control ends of the third transistor M3 and the fourth transistor M4 are connected to the third voltage VREF1 and the fourth voltage VREF2 respectively, and the second ends of the third transistor M3 and the fourth transistor M4 output the differential bias current. The third voltage VREF1 and the fourth voltage VREF2 constitute the differential reference voltage, which can usually be a voltage on a node inside the circuit or an external input voltage.

[0041] In this embodiment, the third transistor M3 and the fourth transistor M4 are both PMOS transistors, the first ends of the third transistor M3 and the fourth transistor M4 are their sources, the second ends of the third transistor M3 and the fourth transistor M4 are their drains, and the control ends of the third transistor M3 and the fourth transistor M4 are their gates. Of course, in some embodiments, the third transistor M3 and the fourth transistor M4 may also be triodes, in which case the first ends of the third transistor M3 and the fourth transistor M4 are their emitters, the second ends of the third transistor M3 and the fourth transistor M4 are their collectors, and the control ends of the third transistor M3 and the fourth transistor M4 are their bases.

[0042] It should be noted that, in order to form a differential pair of transistors, the specifications of the third transistor M3 and the fourth transistor M4 should be equal.

[0043] The load module includes a first load module 13 and a second load module 14, the first load module and the second load module are in a mirror relationship, and the load module can output a single-end output signal or a double-end output signal. The first end of the first load module 13 is connected to the second end of the first transistor M1 and the third transistor M3, the second end of the first load module 13 is grounded, the first end of the second load module 14 is connected to the second end of the second transistor M2 and the fourth transistor M4, and the second end of the second load module 14 is grounded. In this embodiment, the first load module 13 and the second load module 14 constitute an active load, the first load module 13 includes an eighth transistor M8, the second load module 14 includes a ninth transistor M9, the first end and the second end of the eighth transistor M8 are respectively used as the second end and the first end of the first load module 13, respectively connected to the second end of the first transistor M1 and the third transistor M3 and grounded; the first end and the second end of the ninth transistor M9 are respectively used as the second end and the first end of the second load module 14, respectively connected to the second end of the second transistor M2 and the fourth transistor M4 and grounded, and the second end of the eighth transistor M8 is also connected to its control end and the control end of the ninth transistor M9.

[0044] In this embodiment, the eighth transistor M8 and the ninth transistor M9 are both PMOS transistors, the first ends of the eighth transistor M8 and the ninth transistor M9 are their sources, the second ends of the eighth transistor M8 and the ninth transistor M9 are their drains, and the control ends of the eighth transistor M8 and the ninth transistor M9 are their gates. Of course, in some embodiments, the eighth transistor M8 and the ninth transistor M9 may also be triodes, in which case the first ends of the eighth transistor M8 and the ninth transistor M9 are their emitters, the second ends of the eighth transistor M8 and the ninth transistor M9 are their collectors, and the control ends of the eighth transistor M8 and the ninth transistor M9 are their bases.

[0045] In this embodiment, the second load module 14 has the same specifications as the first load module 13 , that is, the eighth transistor M8 and the ninth transistor M9 have the same specifications, thereby ensuring that the currents flowing through the eighth transistor M8 and the ninth transistor M9 are equal.

[0046] Of course, the second load module 14 and the first load module 13 may also be passive loads. For example, the second load module 14 and the first load module 13 may be resistors with the same specifications or transistors with the same specifications, which will not be described one by one here.

[0047] Please continue reading Figure 1In this embodiment, the current I M8 The current I M1 and the current I on the third transistor M3 M3 Provided that the current I on the ninth transistor M9 M9 The current I M2 and the current I M4 Since the eighth transistor M8 and the ninth transistor M9 have the same specifications, when the circuit reaches a steady state, that is, when the voltage at the first end of the first load module 13 is equal to the voltage at the first end of the second load module 14, the current I M8 The current I M9 should be equal, where the steady state of the offset circuit refers to the critical moment when the output signal of the offset circuit flips, that is: I M8 =I M9 =I M1 +I M3 =I M2 +I M4 .

[0048] From the voltage and current characteristics of the differential pair tube, we can get:

[0049] I M4 -I M3 =g m3,4 (VREF2-VREF1);

[0050] I M1 -I M2 =g m1,2 (VIN1-VIN2);

[0051] From this we can get:

[0052] VIN1-VIN2=g m3,4 / g m1,2 (VREF2-VREF1);

[0053] Wherein, VIN1 is the first voltage, VIN2 is the second voltage, VREF1 is the third voltage, VREF2 is the fourth voltage, g m1,2 is the transconductance of the first transistor M1 and the second transistor M2, g m3,4 is the transconductance of the third transistor M3 and the fourth transistor M4.

[0054] It can be seen that the offset between the first voltage VIN1 and the second voltage VIN2 (i.e., the offset of the differential input voltage) is related to the offset VREF2-VREF1 between the fourth voltage VREF2 and the third voltage VREF1 (i.e., the offset of the differential reference voltage). Specifically, they are in proportional relationship. The offset between the first voltage VIN1 and the second voltage VIN2 can be adjusted by adjusting the third voltage VREF1 and the fourth voltage VREF2, so that the offset between the first voltage VIN1 and the second voltage VIN2 is less affected by process fluctuations, power supply voltage fluctuations, and temperature changes.

[0055] Specifically, when the circuit reaches a steady state, if the fourth voltage VREF2 is greater than the third voltage VREF1, the current I M3 is greater than the current I on the fourth transistor M4 M4 , due to I M1 +I M3 =I M2 +I M4 , so the current I on the first transistor M1 M1 should be smaller than the current I M2 Therefore, the first voltage VIN1 is greater than the second voltage VIN2, and the first voltage VIN1 is positively offset compared to the second voltage VIN2.

[0056] Similarly, when the circuit reaches a steady state, if the fourth voltage VREF2 is less than the third voltage VREF1, the current I M3 is less than the current I on the fourth transistor M4 M4 , due to I M1 +I M3 =I M2 +I M4 , so the current I on the first transistor M1 M1 should be greater than the current I M2 Therefore, the first voltage VIN1 is less than the second voltage VIN2, and the first voltage VIN1 is negatively offset compared to the second voltage VIN2.

[0057] In this embodiment, the specifications of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are the same. At this time, the transconductance g of the first transistor M1 and the second transistor M2 is m1,2 and the transconductance g of the third transistor M3 and the fourth transistor M4 m3,4Equal, at this time, the offset between the first voltage VIN1 and the second voltage VIN2 is VIN1-VIN2=VREF2-VREF1. It can be seen that the offset between the first voltage VIN1 and the second voltage VIN2 is equal to the offset between the fourth voltage VREF2 and the third voltage VREF1.

[0058] For further information, please refer to Figure 1 In this embodiment, the offset circuit may be a comparison circuit, in which the first voltage VIN1 and the second voltage VIN2 are used as input signals of the comparison circuit, the first end of the second load module 14 is used as an output end, and the output signal VOUT is a comparison signal. The offset between the first voltage VIN1 and the second voltage VIN2 is set by setting the values ​​of the third voltage VREF1 and the fourth voltage VREF2, thereby introducing a fixed offset voltage at the two input ends of the comparison circuit, thereby realizing voltage comparison under specific circumstances.

[0059] In some implementations, the first end of the first load module 13 may also output a first output signal, the second end of the second load module 14 may output a second output signal, and the first output signal and the second output signal may output the comparison signal via a double-ended to single-ended circuit. The double-ended to single-ended circuit may be, for example, an operational amplifier.

[0060] Embodiment 2

[0061] Figure 2 FIG. 1 is a circuit diagram of an offset circuit provided in this embodiment. Figure 2 As shown, the difference from the first embodiment is that, in this embodiment, the offset circuit can be an operational amplifier circuit (such as a unit gain buffer circuit), the first voltage VIN1 is the input signal of the operational amplifier circuit, the first end of the second load module 14 is connected to the control end of the second transistor M2 as the output end, and the output signal VOUT is the amplified signal. Similarly, the offset between the first voltage VIN1 and the second voltage VIN2 is set by setting the values ​​of the third voltage VREF1 and the fourth voltage VREF2. After the values ​​of the third voltage VREF1 and the fourth voltage VREF2 are determined, the offset between the first voltage VIN1 and the second voltage VIN2 is also fixed, thereby introducing a fixed offset voltage at the two input ends of the comparison circuit, so that the amplified signal output by the operational amplifier circuit follows the input signal with the offset.

[0062] Specifically, the amplified signal can be expressed by the following formula:

[0063] VOUT=VIN2=VIN1-g m3,4 / g m1,2 (VREF2-VREF1).

[0064] Embodiment 3

[0065] Figure 3 FIG. 1 is a circuit diagram of an offset circuit provided in this embodiment. Figure 3 As shown, the difference from the first embodiment is that in this embodiment, the first load module 13 and the second load module 14 are both resistors, and the load modules output a two-terminal output signal. Specifically, the first load module 13 includes a first resistor R1, the first end of the first resistor R1 is connected to the second end of the first transistor M1 and the third transistor M3, and the second end of the first resistor R1 is grounded. The second load module 14 includes a second resistor R2, the first end of the second resistor R2 is connected to the second end of the second transistor M2 and the fourth transistor M4, and the second end of the second resistor R2 is grounded. The specifications of the first resistor R1 and the second resistor R2 are also the same.

[0066] In this embodiment, the first ends of the first load module 13 and the second load module 14 are both used as output ends to output a first output signal VOUT1 and a second output signal VOUT2. The first differential signal VOUT1 and the second output signal VOUT2 are output via a double-ended to single-ended circuit to achieve single-ended output. The double-ended to single-ended circuit can be, for example, an operational amplifier.

[0067] Furthermore, in the present embodiment, when the offset circuit is used as a comparison circuit, the first ends of the first load module 13 and the second load module 14 output a comparison signal after passing through a double-ended to single-ended circuit; when the offset circuit is used as an operational amplifier circuit, the first ends of the first load module 13 and the second load module 14 output a single-ended signal after passing through a double-ended to single-ended circuit, and the single-ended signal is connected to the control end of the second transistor M2 to output an amplified signal.

[0068] In summary, the offset circuit provided in the embodiment of the utility model includes a power supply module, a first differential pair of tubes, a second differential pair of tubes and a load module; the power supply module is connected to the power supply end to provide a bias current; the first differential pair of tubes receives the bias current and the differential input voltage and outputs a differential current; the second differential pair of tubes receives the bias current and the differential reference voltage and outputs a differential bias current; the input end of the load module is connected to the output end of the first differential pair of tubes and the output end of the second differential pair of tubes to receive the current after the differential current and the differential bias current are superimposed, and the connection node between the load module and the differential input pair of tubes outputs an output signal. The offset of the differential input voltage is related to the offset of the differential reference voltage, specifically, in a proportional relationship. The offset of the differential input voltage can be adjusted by adjusting the differential reference voltage, so that the offset of the differential input voltage is less affected by process fluctuations, power supply voltage fluctuations, and temperature changes.

[0069] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0070] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0071] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0072] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the utility model. It must be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the utility model may include performing the selected task manually, automatically, or in combination.

Claims

1. An offset circuit, characterized in that: include: A power supply module is connected to the power supply terminal to provide bias current; A first differential pair tube receives the bias current and the differential input voltage, and outputs a differential current; The second differential pair tube receives the bias current and the differential reference voltage and outputs a differential bias current; A load module, wherein an input end of the load module is connected to an output end of the first differential pair of tubes and an output end of the second differential pair of tubes to receive a current obtained by superimposing the differential current and the differential bias current, and a connection node between the load module and the differential pair of tubes outputs an output signal.

2. The offset circuit according to claim 1, wherein: The first differential pair transistor comprises a first transistor and a second transistor, and the first ends of the first transistor and the second transistor are connected and then connected to the power supply module; The second differential pair transistor comprises a third transistor and a fourth transistor, and the first ends of the third transistor and the fourth transistor are connected and then connected to the power supply module; The load module comprises a first load module and a second load module, the first end of the first load module is connected to the second ends of the first transistor and the third transistor, and the second end of the first load module is grounded; The second load module has the same specifications as the first load module, a first end of the second load module is connected to the second ends of the second transistor and the fourth transistor, and a second end of the second load module is grounded; and, The control ends of the first transistor and the second transistor are connected to a first voltage and a second voltage respectively, the control ends of the third transistor and the fourth transistor are connected to a third voltage and a fourth voltage respectively, and the offset between the first voltage and the second voltage is positively correlated with the offset between the fourth voltage and the third voltage.

3. The offset circuit according to claim 2, wherein: The first load module and the second load module are in a mirror relationship, and the load module outputs a single-ended output signal or a double-ended output signal.

4. The offset circuit according to claim 2, wherein: The first load module and the second load module are both resistors, and the load modules output double-ended output signals.

5. The offset circuit according to claim 3, wherein: The offset circuit is a comparison circuit, the first voltage and the second voltage are input signals of the comparison circuit, and the first end of the second load module outputs a comparison signal.

6. The offset circuit according to claim 4, characterized in that The first end of the first load module outputs a first output signal, the second end of the second load module outputs a second output signal, and the first output signal and the second output signal are output as single-ended signals via a double-ended to single-ended circuit.

7. The offset circuit according to claim 3, characterized in that The offset circuit is an operational amplifier circuit, the first voltage is an input signal of the operational amplifier circuit, and the first end of the second load module is connected to the control end of the second transistor to output an amplified signal.

8. The offset circuit according to any one of claims 2 to 7, characterized in that: The transconductances of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same, and when the first terminal voltage of the first load module is equal to the first terminal voltage of the second load module, the offset between the first voltage and the second voltage is equal to the offset between the fourth voltage and the third voltage.

9. The offset circuit according to claim 1, wherein: The power supply module includes a fifth transistor, a sixth transistor, a seventh transistor and a current source. The sixth transistor and the seventh transistor have the same specifications. The first ends of the fifth transistor, the sixth transistor and the seventh transistor are connected and then connected to the power supply end. The control ends of the fifth transistor, the sixth transistor and the seventh transistor are connected and then connected to the second end of the fifth transistor and one end of the current source. The other end of the current source is grounded. The second ends of the sixth transistor and the seventh transistor both output the bias current.

10. The offset circuit according to claim 2, wherein: The first transistor, the second transistor, the third transistor and the fourth transistor are all MOS transistors, the first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their sources, the second ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their drains, and the control ends of the first transistor, the second transistor, the third transistor and the fourth transistor are their gates; or, The first transistor, the second transistor, the third transistor and the fourth transistor are all triodes, the first ends of the first transistor, the second transistor, the third transistor and the fourth transistor are emitters, the second ends of the first transistor, the second transistor, the third transistor and the fourth transistor are collectors, and the control ends of the first transistor, the second transistor, the third transistor and the fourth transistor are bases.

11. The offset circuit according to claim 3, characterized in that: The first load module includes an eighth transistor, and the second load module includes a ninth transistor. The eighth transistor and the ninth transistor have the same specifications. The first end and the second end of the eighth transistor serve as the second end and the first end of the first load module respectively, and the first end and the second end of the ninth transistor serve as the second end and the first end of the second load module respectively. The second end of the eighth transistor is also connected to its control end and the control end of the ninth transistor.

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