Display panel and electronic equipment

Abstract

The utility model provides a display panel and electronic equipment. The display panel comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a pixel circuit with a light-emitting element and a power supply voltage line connected with the pixel circuit, and the non-display area comprises a first non-display area and a second non-display area used for being bound with a circuit board / driving chip. The display panel comprises a power-on circuit and a power-off circuit, and the power-on circuit and the power-off circuit are both connected with the pixel circuit and used for controlling the power supply voltage of the light-emitting element; the display panel further comprises a voltage stabilizing circuit arranged in the first non-display area. The voltage stabilizing circuit is electrically connected with the power-on circuit, the power-off circuit and the power supply voltage line. Crosstalk caused by coupling between a power supply voltage line and a data line close to the power supply voltage line can be avoided, and the display effect and the display stability are improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and an electronic device. Background Art

[0002] In recent years, with the continuous development of the semiconductor industry, the types of display panels have become more diverse, such as LCD, QLED, mini-LED, OLED, WOLED, QD-OLED, and micro-LED, etc. To drive the display panel, a plurality of driving chips (Display Driver Integrated Circuit, DDIC) are generally arranged in the non-display area of the display panel, and each driving chip corresponds to a plurality of data lines or gate lines located in the display area.

[0003] The die size of a wafer directly affects the cost of the display driving chip. Currently, a display driving chip using a two-input multiplexer (Mux2) can reduce the number of source pins of the DDIC by half, thereby effectively reducing the die size of the DDIC and lowering the cost of the DDIC. Therefore, Mux2 DDIC will become the development direction of future OLED DDIC. Summary of the Utility Model

[0004] Aiming at the shortcomings of the prior art, the present application provides a display panel and an electronic device to solve the technical problem of the lack of stability of the voltage of ELVDD in the display panel in the prior art.

[0005] An embodiment of the present application provides a display panel. The display panel includes a display area and at least a part of a non-display area surrounding the display area. The display area includes a pixel circuit having a light-emitting element and a power supply voltage line connected to the pixel circuit. The non-display area includes a first non-display area and a second non-display area for binding with a circuit board / driving chip. The display panel includes a power-on circuit and a power-off circuit, both of which are connected to the pixel circuit and used to control the power supply voltage of the light-emitting element. The display panel further includes a voltage stabilizing circuit disposed in the first non-display area. The voltage stabilizing circuit is electrically connected between the power-on circuit, the power-off circuit, and the power supply voltage line respectively.

[0006] According to the above embodiments, it can be known that in the technical solution provided by the present application, a voltage stabilizing circuit is added between the power-on circuit and the power-off circuit to stabilize the power supply voltage connected to the voltage stabilizing circuit, and the charging and discharging of the electronic components in the voltage stabilizing circuit are controlled during the power-on or power-off stage. Compared with the related art in which a voltage stabilizing capacitor is directly added to the circuit where the power supply voltage is located, resulting in the voltage stabilizing capacitor generating a large current during charging and discharging, causing the display panel to easily trigger the overcurrent protection function of the circuit where the power supply voltage is located at the moment of turning on or off, resulting in a black screen phenomenon, the technical solution provided by the present application can ensure the stability of the power supply voltage, avoid crosstalk caused by coupling between the power supply voltage line and the data line that is close to it, and improve the display effect and display stability.

[0007] In one embodiment, the display panel further includes a gate driving circuit electrically connected to the pixel circuit, the first non-display area includes a first sub-non-display area and a second sub-non-display area located on opposite sides of the display area, and a third sub-non-display area located on a side of the display area away from the second non-display area, the direction from the second non-display area to the display area is a first direction, the direction from the first sub-non-display area to the second sub-non-display area is a second direction, and the first direction intersects with the second direction.

[0008] The gate driving circuit is arranged in the first sub-non-display area and / or the second sub-non-display area, the voltage stabilizing circuit is arranged in the first sub-non-display area and / or the second sub-non-display area and / or the third sub-non-display area, and the voltage stabilizing circuit is electrically connected to the gate driving circuit through a scanning line extending along the second direction.

[0009] In one embodiment, the display panel is further provided with a first signal line and a second signal line extending along the first direction, the voltage stabilizing circuit is electrically connected to the power-on circuit through the first signal line, and the voltage stabilizing circuit is electrically connected to the power-off circuit through the second signal line.

[0010] In one embodiment, the voltage stabilizing circuit includes a first switching circuit, a voltage stabilizing element, and a second switching circuit. The first switching circuit has a first switching end point, a second switching end point, and a first control end point. The first switching end point is connected to the power supply voltage line, and the first control end point is connected to the power-on circuit for receiving a control signal output by the power-on circuit. The voltage stabilizing element has a first voltage stabilizing end point and a second voltage stabilizing end point. The first voltage stabilizing end point is connected to the second switching end point; the second voltage stabilizing end point is connected to the ground terminal. The second switching circuit has a third switching end point, a fourth switching end point, and a second control end point. The third switching end point is connected to both the first voltage stabilizing end point of the voltage stabilizing element and the second switching end point of the first switching circuit; the fourth switching end point is connected to both the second voltage stabilizing end point of the voltage stabilizing element and the ground terminal; the second control end point is connected to the power-off circuit for receiving a control signal output by the power-off circuit.

[0011] In one embodiment, when powering on the power supply voltage line at a first time point, a first control signal is provided to the power-off circuit at the first time point to raise the voltage of the power-off circuit, so that the second switching circuit is turned off; a second control signal is provided to the power-on circuit at a second time point to lower the voltage of the power-off circuit, so that the first switching circuit is turned on; and the voltage stabilizing element is charged; wherein the first time point is earlier than the second time point.

[0012] In one embodiment, the difference between the first time point and the second time point is 1 to 3 milliseconds.

[0013] In one embodiment, when powering off the power supply voltage line at a third time point, a third control signal is provided to the power-on circuit at the third time point to raise the voltage of the power-on circuit, so that the first switching circuit is turned off; a fourth control signal is provided to the power-off circuit at a fourth time point to lower the voltage of the power-off circuit, so that the second switching circuit is turned on; and the voltage stabilizing element is discharged; wherein the third time point is earlier than the fourth time point.

[0014] In one embodiment, the difference between the third time point and the fourth time point is 1 to 5 milliseconds.

[0015] In one embodiment, the first switching circuit includes: at least one first N-type field effect transistor switch or at least one first P-type field effect transistor switch;

[0016] And / or, the second switching circuit includes: at least one second N-type field effect transistor switch or at least one second P-type field effect transistor switch.

[0017] In one embodiment, the voltage stabilizing element is a voltage stabilizing capacitor.

[0018] In some embodiments, the number of the voltage stabilizing circuits is determined by the capacitance-resistance simulation of the line where the pixel circuit is located and the resolution of the display panel.

[0019] In some embodiments, the display panel further includes a power voltage line and a data line that are connected between the circuit board / driving chip and extend to the display area, and the capacitance in the capacitance-resistance simulation is the coupling parasitic capacitance between the power voltage line and the data line.

[0020] This application also provides an electronic device, including the display panel provided in the foregoing embodiments.

[0021] Additional aspects and advantages of this application will be given in part in the following description, and will become apparent from the following description, or be learned through the practice of this application. Description of the Drawings

[0022] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0023] Figure 1 Shown is a schematic structural diagram of a display panel in the related art;

[0024] Figure 2 Shown is a schematic diagram of the black screen phenomenon occurring in the display panel in the related art;

[0025] Figure 3 Shown is a schematic structural diagram of a display panel provided by this application;

[0026] Figure 4 Shown is a schematic structural diagram of a voltage stabilizing circuit provided by this application;

[0027] Figure 5 Shown is Figure 4 a timing diagram of the control signal corresponding to the voltage stabilizing circuit;

[0028] Figure 6 Shown is a schematic structural diagram of a voltage stabilizing circuit distributed in a display panel provided by an embodiment of this application;

[0029] Figure 7 Shown is Figure 6 the structural diagram of the voltage stabilizing circuit in

[0030] Figure 8 Shown is a schematic structural diagram of a pixel circuit provided by an embodiment of this application.

[0031] In the figure:

[0032] 10 - Voltage stabilizing circuit; 100 - Voltage stabilizing element; 101 - First voltage stabilizing terminal; 102 - Second voltage stabilizing terminal; 200 - First switching circuit; 201 - First switching terminal; 202 - Second switching terminal; 203 - First control terminal; 300 - Second switching circuit; 301 - Third switching terminal; 302 - Fourth switching terminal; 303 - Second control terminal; 20 - Pixel circuit; 30 - Gate driving circuit; 40 - Power - on circuit; 41 - First signal line; 50 - Power - off circuit; 51 - Second signal line; 60 - Power supply voltage line; AA - Display area; NA - Non - display area; NA1 - First non - display area; NA11 - First sub - non - display area; NA12 - Second sub - non - display area; NA13 - Third sub - non - display area; NA2 - Second non - display area. Detailed implementation mode

[0033] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0035] In the present application, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. The "element having a certain electrical effect" can be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.

[0036] For those skilled in the art, power - on (switching on) refers to the process from when the power supply is connected until the system stabilizes and can work, which is called the power - on time. Power - off (switching off) refers to disconnecting the device from the power supply.

[0037] With the continuous update and replacement of technology, consumers have higher and higher requirements for display screens in terms of high resolution, wide viewing angle, high response speed, high aperture ratio, etc. At the same time, along with the reduction of pixel size, the line pitch on the TFT substrate is getting smaller and smaller, and the coupling effect between different signal lines is intensifying. When a signal jumps, it may affect the stability of other surrounding signals. For example, when Mux2 DDIC charges pixels, the data line is easily coupled by the ELVDD (power supply voltage) line, causing crosstalk between lines and reducing the display effect. How to avoid the problem of line crosstalk while ensuring the charging rate of pixels (pixel), the voltage stability of ELVDD as the coupling medium becomes the key to the problem.

[0038] For example, the gate driver on array (GOA) circuit of the array substrate is the driving method of most current display panels. As Figure 1 shown, when charging the pixel circuit (not shown in the figure, see Figure 2 ), the Mux of the odd-numbered columns is turned on to charge the data lines of the odd-numbered columns. After charging, the Mux of the even-numbered columns is turned on to charge the pixels of the even-numbered columns. Since the source voltage is coupled to the power supply voltage (ELVDD) when the Mux switches, the ELVDD line and the data line are parallelly distributed in the film layers with a relatively close distance, and the data line of the odd-numbered columns is in a floating state after the Mux of the even-numbered columns is turned off. Therefore, the data line is easily coupled (couple) with the ELVDD, triggering the crosstalk phenomenon (as Figure 2 shown, the DDIC is at the bottom of the image, and the background is gray (RGB(128, 128, 128)) with black in the middle, resulting in a black screen phenomenon), resulting in a poor display effect. Therefore, the voltage stability of ELVDD as the coupling medium becomes the key to the problem. If a voltage stabilizing capacitor is directly added on the flexible printed circuit (FPC) on the side of the driving chip away from the display area, since the voltage stabilizing capacitor is far from the display area, it cannot play a role in rapid filtering, so the improvement of line crosstalk is weak and almost negligible. If the voltage stabilizing capacitor is directly set in the border area surrounding both sides of the display area, the voltage stabilizing capacitor will increase the thickness of the display panel, affecting the aesthetics and precision of the device.

[0039] The display panel and electronic device provided by this application aim to solve the above technical problems of the prior art.

[0040] The embodiments of the present application provide a display panel and an electronic device. The display panel and the electronic device in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or combine with each other.

[0041] The present application embodiment provides a display panel, such as Figure 1 and Figure 3 As shown, the display panel includes a display area AA and a non-display area NA at least partially surrounding the display area AA, the display area AA includes a pixel circuit 20 having a light-emitting element (not shown in the figure) and a power supply voltage line 60 connected to the pixel circuit 20, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 for binding with a circuit board / driving chip, the display panel includes a power-on circuit 40 and a power-off circuit 50, both of which are connected to the pixel circuit 20 for controlling the power supply voltage of the light-emitting element; the display panel also includes a voltage stabilizing circuit 10 arranged in the first non-display area NA1; the voltage stabilizing circuit 10 is electrically connected to the power-on circuit 40, the power-off circuit 50 and the power supply voltage line 60, respectively.

[0042] According to the above embodiments, in the technical solution provided by the present application, a voltage stabilizing circuit 10 is added between the power-on circuit 40 and the power-off circuit 50 to stabilize the power supply voltage connected to the voltage stabilizing circuit 10, and the charging and discharging of the electronic components in the voltage stabilizing circuit 10 are controlled during the power-on or power-off stage. Compared with the related art in which a voltage stabilizing capacitor is directly added to the circuit where the power supply voltage is located, resulting in the voltage stabilizing capacitor generating a large current during charging and discharging, causing the display panel to easily trigger the overcurrent protection function of the circuit where the power supply voltage is located at the moment of turning on or off, resulting in a black screen phenomenon, the technical solution provided by the present application can ensure the stability of the power supply voltage, avoid crosstalk caused by coupling between the power supply voltage line 60 and the data line (dataline) that is close to it, and improve the display effect and display stability.

[0043] In some embodiments, Figure 1 and Figure 3 As shown, the display panel further includes a gate driving circuit 30 (GOA) electrically connected to the pixel circuit 20, the first non-display area NA1 includes a first sub-non-display area NA11 and a second sub-non-display area NA12 located on opposite sides of the display area AA, and a third sub-non-display area NA13 located on the side of the display area AA away from the second non-display area NA2, the direction from the second non-display area NA2 to the display area AA is the first direction x, the direction from the first sub-non-display area NA11 to the second sub-non-display area NA12 is the second direction y, and the first direction x intersects the second direction y. Wherein,

[0044] The gate driving circuit 30 is disposed in the first non-display area NA11 and / or the second non-display area NA12, and the voltage stabilizing circuit 10 is disposed in the first non-display area NA11 and / or the second non-display area NA12 and / or the third non-display area NA13. The voltage stabilizing circuit 10 is electrically connected to the gate driving circuit 30 through a scanning line extending along the second direction y.

[0045] In this embodiment, the voltage stabilizing circuit 10 is disposed in the left and right borders and the upper border where the gate driving circuit 30 is located, which can make the voltage stabilizing circuit 10 closer to the display area AA. Therefore, it can play a role in rapid filtering, improve the crosstalk problem between circuit traces, and at the same time, disposing the voltage stabilizing circuit 10 in the non-display area NA can avoid the influence of the traces of the voltage stabilizing circuit 10 itself on the traces of the central display area AA.

[0046] It should be noted that the first direction x and the second direction y in this application are approximately perpendicular, and the included angle between the first direction and the second direction is approximately 90°.

[0047] In some embodiments, as Figure 3 shown, a first signal line 41 and a second signal line 51 extending along the first direction x are further disposed in the display panel. The voltage stabilizing circuit 10 is electrically connected to the power-on circuit 40 through the first signal line 41, and the voltage stabilizing circuit 10 is electrically connected to the power-off circuit 50 through the second signal line 51.

[0048] In this embodiment, the voltage stabilizing circuit 10 is connected to the power-on circuit 40 through the first signal line 41 extending from the left and right border areas or the upper border area of the display area AA, and the second signal line 51 is connected to the power-off circuit 50. The position of the voltage stabilizing circuit 10 can be flexibly designed through the first signal line 41 and the second signal line 51 to avoid the newly added voltage stabilizing circuit 10 interfering with other traces in the display panel and affecting the display.

[0049] In some embodiments, as Figure 4As shown, the voltage stabilizing circuit 10 includes a first switching circuit 200, a voltage stabilizing element 100, and a second switching circuit 300. Among them, the first switching circuit 200 has a first switching terminal 201, a second switching terminal 202, and a first control terminal 203. The first switching terminal 201 is connected to the power supply voltage line 60, and the first control terminal 203 is connected to the power-on circuit 40 for receiving the control signal output by the power-on circuit 40; the voltage stabilizing element 100 has a first voltage stabilizing terminal 101 and a second voltage stabilizing terminal 102. The first voltage stabilizing terminal 101 is connected to the second switching terminal 202; the second voltage stabilizing terminal 102 is connected to the ground terminal; the second switching circuit 300 has a third switching terminal 301, a fourth switching terminal 302, and a second control terminal 303. The third switching terminal 301 is connected to both the first voltage stabilizing terminal 101 of the voltage stabilizing element 100 and the second switching terminal 202 of the first switching circuit 200; the fourth switching terminal 302 is connected to both the second voltage stabilizing terminal 102 of the voltage stabilizing element 100 and the ground terminal; the second control terminal 303 is connected to the power-off circuit 50 for receiving the control signal output by the power-off circuit 50.

[0050] The voltage stabilizing circuit 10 in this embodiment is composed of a combination of multiple switching circuits and the voltage stabilizing element 100. By providing different control signals to the switching circuits, the voltage stabilizing element 100 can be charged and discharged, thereby stabilizing the voltage of the power supply voltage line 60, avoiding the coupling between the power supply voltage line 60 and the data line in the display panel, and preventing the crosstalk from causing the black screen phenomenon of the display panel, which can improve the display effect and display stability.

[0051] In some embodiments, the voltage stabilizing circuit 10 provided in this application further includes a third switching circuit, a fourth switching circuit, etc., which can be set according to actual needs by those skilled in the art and are not limited thereto.

[0052] In some embodiments, such as Figure 4 and Figure 5 As shown, when the power supply voltage line 60 is powered on at the first time point t1, a first control signal is provided to the power-off circuit 50 at the first time point t1 to raise the voltage of the power-off circuit 50, so that the second switching circuit 300 is disconnected; a second control signal is provided to the power-on circuit 40 at the second time point t2 to lower the voltage of the power-off circuit 50, so that the first switching circuit 200 is turned on; the voltage stabilizing element 100 is charged; wherein, the first time point t1 is earlier than the second time point t2.

[0053] In the specific control method of the voltage stabilizing circuit 10 in this embodiment, by delaying for a certain time to lower the Power on sync voltage of the power-on circuit 40 and simultaneously turning on the first switching circuit 200, the voltage stabilizing element 100 can be charged, thereby compensating for the voltage difference caused by the unstable voltage value of the power supply voltage line 60 due to crosstalk, and avoiding the abnormal black screen of the display screen.

[0054] In some embodiments, the difference between the first time point t1 and the second time point t2 is 1 to 3 milliseconds.

[0055] In some embodiments, as Figure 4 and Figure 5 shown, when the power supply voltage line 60 is powered off at the third time point t3, a third control signal is provided to the power-on circuit 40 at the third time point t3 to raise the voltage of the power-on circuit 40, so that the first switch circuit 200 is turned off; a fourth control signal is provided to the power-off circuit 50 at the fourth time point t4 to lower the voltage of the power-off circuit 50, so that the second switch circuit 300 is turned on; the voltage stabilizing element 100 is discharged; wherein, the third time point t3 is earlier than the fourth time point t4.

[0056] This embodiment is the same as the above embodiment. After the power supply voltage is powered off, it is not necessary to continue compensating the voltage stabilizing circuit 10. Therefore, by raising the power-on sync signal of the power-on circuit 40 to turn off the first switch circuit 200, and at the same time delaying for a certain time to lower the Power off sync voltage of the power-off circuit 50 to turn on the second switch circuit 300, the voltage stabilizing element 100 can be discharged to complete the entire control process.

[0057] In some embodiments, the difference between the third time point t3 and the fourth time point t4 is 1 to 5 milliseconds.

[0058] In some embodiments, as Figure 6 and Figure 7 shown, the first switch circuit 200 includes: at least one first N-type field effect transistor switch or at least one first P-type field effect transistor switch;

[0059] And / or, the second switch circuit 300 includes: at least one second N-type field effect transistor switch or at least one second P-type field effect transistor switch.

[0060] In some embodiments, as Figure 6 and Figure 7 shown, the voltage stabilizing element 100 is a voltage stabilizing capacitor.

[0061] In some embodiments, the number of the voltage stabilizing circuits 10 is determined by the capacitance-resistance simulation of the line where the pixel circuit 20 is located and the resolution of the display panel.

[0062] In some embodiments, as Figure 1As shown, the display panel further includes a power supply voltage line 60 (ELVDD) and a data line that are connected between the circuit board / driving chip and extend to the display area AA. The capacitor in the capacitance-resistance simulation is the coupling parasitic capacitance between the power supply voltage line 60 and the data line. In this embodiment, the data line is connected to the multiplexer MUX. Specifically, ①simulate and calculate the coupling parasitic capacitance value C between the data line (Data line) and the power supply voltage line 60 (ELVDD); ②calculate the coupling amount Q of ELVDD based on the maximum voltage change amount deltaV of the Data source; ③Q = C * delataV; ④the amount of electricity Q coupled by ELVDD is directly proportional to the capacitance of ELVDD and the number of compensation circuits; ⑤through simulation, experiment verification, and the amount of electricity Q coupled by ELVDD, calculate the number of circuits for stabilizing the voltage of ELVDD and the number of each voltage stabilizing capacitor.

[0063] In some embodiments, as Figure 8 shown, the pixel circuit 20 in the present application is a 7T1C circuit, and in actual design, it can also be a 3T1C circuit, a 4T1C circuit, or a 5T2C circuit. Those skilled in the art can set it according to the actual situation, and it is not limited thereto.

[0064] Based on the same inventive concept, an embodiment of the present application provides an electronic device. The electronic device includes the aforementioned display panel. Therefore, the electronic device has all the features and advantages of the previous display panel, which will not be elaborated herein.

[0065] It should be noted that the electronic device can be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image), and whether it is text or image. More specifically, the expected embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0066] The above embodiments of the present application can complement each other without conflict.

[0067] It should be noted that in the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or an intermediate layer may be present. Additionally, it is understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or more than one intermediate layer or element may be present. Further, it is understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or more than one intermediate layer or element may also be present. Like reference numerals throughout the specification indicate like elements.

[0068] The orientation or positional relationship indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0069] The terms "first" and "second" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0070] Those skilled in the art will readily conceive of other embodiments of the present application upon considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only to be regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims.

[0071] It should be understood that the present application is not limited to the exact structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area at least partially surrounding the display area, the display area includes a pixel circuit having a light-emitting element and a power supply voltage line connected to the pixel circuit, the non-display area includes a first non-display area and a second non-display area for binding with a circuit board / driving chip, and the display panel includes: a power-on circuit and a power-off circuit, connected to the pixel circuit, for controlling the power supply voltage of the light-emitting element; and A voltage stabilizing circuit is arranged in the first non-display area; the voltage stabilizing circuit is electrically connected to the power-on circuit, the power-off circuit and the power supply voltage line respectively.

2. The display panel according to claim 1, characterized in that: The display panel further includes a gate driving circuit electrically connected to the pixel circuit, the first non-display area includes a first sub-non-display area and a second sub-non-display area located on opposite sides of the display area, and a third sub-non-display area located on a side of the display area away from the second non-display area, the direction from the second non-display area to the display area is a first direction, the direction from the first sub-non-display area to the second sub-non-display area is a second direction, and the first direction intersects with the second direction; wherein, The gate driving circuit is arranged in the first sub-non-display area and / or the second sub-non-display area, the voltage stabilizing circuit is arranged in the first sub-non-display area and / or the second sub-non-display area and / or the third sub-non-display area, and the voltage stabilizing circuit is electrically connected to the gate driving circuit through a scanning line extending along the second direction.

3. The display panel according to claim 1, characterized in that: The direction from the second non-display area to the display area is a first direction. The display panel is also provided with a first signal line and a second signal line extending along the first direction. The voltage stabilizing circuit is electrically connected to the power-on circuit through the first signal line, and the voltage stabilizing circuit is electrically connected to the power-off circuit through the second signal line.

4. The display panel according to claim 1, characterized in that: The voltage stabilizing circuit comprises: A first switch circuit has a first switch terminal, a second switch terminal and a first control terminal, wherein the first switch terminal is connected to the power supply voltage line, and the first control terminal is connected to the power-on circuit for receiving a control signal output by the power-on circuit; A voltage stabilizing element having a first voltage stabilizing terminal and a second voltage stabilizing terminal, wherein the first voltage stabilizing terminal is connected to the second switch terminal; and the second voltage stabilizing terminal is connected to a ground terminal; The second switch circuit has a third switch terminal, a fourth switch terminal and a second control terminal. The third switch terminal is connected to the first voltage stabilizing terminal of the voltage stabilizing element and the second switch terminal of the first switch circuit; the fourth switch terminal is connected to the second voltage stabilizing terminal of the voltage stabilizing element and the ground terminal; the second control terminal is connected to the power-off circuit for receiving a control signal output by the power-off circuit.

5. The display panel according to claim 4, characterized in that: When the power supply voltage line is powered on at a first time point, a first control signal is provided to the power-down circuit at the first time point to increase the voltage of the power-down circuit and disconnect the second switch circuit; a second control signal is provided to the power-up circuit at a second time point to decrease the voltage of the power-down circuit and turn on the first switch circuit; and the voltage stabilizing element is charged; wherein the first time point is earlier than the second time point.

6. The display panel according to claim 5, characterized in that: The difference between the first time point and the second time point is 1 to 3 milliseconds.

7. The display panel according to claim 4, characterized in that: When the power supply voltage line is powered off at a third time point, a third control signal is provided to the power-on circuit at the third time point to increase the voltage of the power-on circuit and disconnect the first switch circuit; a fourth control signal is provided to the power-off circuit at a fourth time point to decrease the voltage of the power-off circuit and turn on the second switch circuit; and the voltage stabilizing element is discharged; wherein the third time point is earlier than the fourth time point.

8. The display panel according to claim 7, characterized in that: The difference between the third time point and the fourth time point is 1 to 5 milliseconds.

9. The display panel according to claim 4, characterized in that: The first switch circuit includes: at least one first N-type field effect transistor switch or at least one first P-type field effect transistor switch; And / or, the second switch circuit includes: at least one second N-type field effect transistor switch or at least one second P-type field effect transistor switch.

10. The display panel according to claim 4, characterized in that: The voltage stabilizing element is a voltage stabilizing capacitor.

11. The display panel according to claim 4, characterized in that: The number of the voltage stabilizing circuits is determined by the capacitance-resistance simulation of the circuit where the pixel circuit is located and the resolution of the display panel.

12. The display panel according to claim 11, characterized in that: The display panel also includes a power supply voltage line and a data line connected to the circuit board / driving chip and extending to the display area. The capacitor in the capacitor-resistance simulation is a coupling parasitic capacitor between the power supply voltage line and the data line.

13. An electronic device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 12.

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