Bonding structure of semiconductor wafer metal pressure welding area

Abstract

The utility model discloses a bonding structure of a semiconductor wafer metal pressure welding area. The bonding structure comprises a silicon dioxide layer and a metal pressure welding area arranged in a cavity defined by the silicon dioxide layer. The silicon dioxide layer comprises a silicon dioxide base layer arranged on the semiconductor wafer and a silicon dioxide extension layer which extends upwards from the silicon dioxide base layer and is positioned on the peripheral side of the metal pressure welding area; the silicon dioxide extension layer wraps the edge of the metal pressure welding area; a passivation metal layer is arranged above the metal pressure welding area, and metal in the passivation metal layer is a metal material which is not easy to oxidize; and a silicon nitride layer is arranged above the silicon dioxide layer. The metal pressure welding area is arranged on the silicon dioxide base layer, the silicon dioxide extension layer wraps the peripheral side and the edge of the upper end face of the metal pressure welding area, the silicon nitride layer is arranged on the silicon dioxide layer, and the passivation metal layer is arranged above the metal pressure welding area, so that water vapor, air and other impurities are prevented from being in contact with the metal pressure welding area; and the stability of the bonding structure of the metal pressure welding area is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a bonding structure for a metal bonding area of a semiconductor wafer. Background Art

[0002] The semiconductor wafers produced in a processing factory are all bare chips. The bonding pads on such bare chips are usually not directly applied to an actual circuit board. Since bare chips are extremely vulnerable to the influence of the external environment temperature, impurities, and physical forces and are easily damaged, the bonding pads must be led out with corresponding pins through packaging before they can be used as a basic component chip.

[0003] Generally, bonding wires are used to bind the bonding areas on the bare chip and the pins on the package. In the prior art, the bonding structure of the bonding area usually has a silicon dioxide layer provided on the semiconductor wafer. The silicon dioxide layer forms a cavity structure to cover the metal bonding area, and the end face of the metal bonding area is exposed, resulting in problems such as poor corrosion resistance of the metal bonding area, low reliability of bonding and welding points, and increased resistance.

[0004] Therefore, the prior art still needs to be improved and enhanced. Summary of the Utility Model

[0005] In view of the deficiencies of the above prior art, the purpose of the present utility model is to provide a bonding structure for a metal bonding area of a semiconductor wafer, aiming to solve the problem of poor bonding effect of the metal bonding area of the semiconductor wafer in the prior art.

[0006] To achieve the above purpose, the present utility model adopts the following technical solutions:

[0007] A bonding structure for a metal bonding area of a semiconductor wafer, comprising a silicon dioxide layer and a metal bonding area provided in a cavity defined by the silicon dioxide layer; the silicon dioxide layer includes a silicon dioxide base layer provided on the semiconductor wafer and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edges of the metal bonding area; a passivation metal layer is provided above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized; a silicon nitride layer is provided above the silicon dioxide layer.

[0008] A peripheral protection layer is provided above the silicon nitride layer, and the peripheral protection layer includes at least one of an organic planarization layer and a low-temperature oxide layer.

[0009] The upper end face of the silicon dioxide extension layer is higher than the upper end face of the passivation metal layer, and the side walls of the silicon dioxide layer and the silicon nitride layer are flush with the side walls of the passivation metal layer.

[0010] At least one of the organic planarization layer and the low-temperature oxide layer covers the edge of the silicon dioxide extension layer on the side close to the passivation metal layer.

[0011] The upper end surface of the silicon dioxide extension layer is lower than the upper end surface of the passivation metal layer.

[0012] At least one of the organic planarization layer and the low-temperature oxide layer covers the edge of the passivation metal layer.

[0013] The thickness of the passivation metal layer is 0.1 μm - 5 μm.

[0014] When an organic planarization layer and a low-temperature oxide layer are provided above the silicon nitride layer, the thickness of the organic planarization layer is greater than the thickness of the low-temperature oxide layer.

[0015] The thickness of the organic planarization layer is 0.1 μm - 0.5 μm, and the thickness of the low-temperature oxide layer is 0.01 μm - 0.5 μm.

[0016] A bonding structure for a metal bonding area of a semiconductor wafer, comprising a silicon dioxide layer and a metal bonding area provided in a cavity defined by the silicon dioxide layer; the silicon dioxide layer includes a silicon dioxide base layer provided on the semiconductor wafer and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edge of the metal bonding area; a passivation metal layer is provided above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized.

[0017] A peripheral protective layer is provided above the silicon dioxide extension layer, and the peripheral protective layer includes at least one of an organic planarization layer and a low-temperature oxide layer.

[0018] The upper end surface of the silicon dioxide extension layer is higher than the upper end surface of the passivation metal layer, and the side wall of the silicon dioxide extension layer is flush with the side wall of the passivation metal layer.

[0019] At least one of the organic planarization layer and the low-temperature oxide layer covers the edge of the silicon dioxide extension layer on the side close to the passivation metal layer.

[0020] At least one of the organic planarization layer and the low-temperature oxide layer covers the edge of the silicon dioxide extension layer on the side close to the passivation metal layer.

[0021] At least one of the organic planarization layer and the low-temperature oxide layer covers the edge of the passivation metal layer.

[0022] Compared with the prior art, a bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model includes a silicon dioxide layer and a metal bonding area disposed in a cavity defined by the silicon dioxide layer; the silicon dioxide layer includes a silicon dioxide base layer disposed on the semiconductor wafer and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edges of the metal bonding area; a passivation metal layer is disposed above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized; a silicon nitride layer is disposed above the silicon dioxide layer.

[0023] In this application, the metal bonding area is disposed on the silicon dioxide base layer, and the silicon dioxide extension layer covers the periphery and the edge of the upper end face of the metal bonding area. By disposing a silicon nitride layer on the silicon dioxide layer and a passivation metal layer above the metal bonding area, contact between impurities such as water vapor and air and the metal bonding area is avoided, thereby improving the stability of the bonding structure of the metal bonding area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. is a schematic structural diagram of a first alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0025] Figure 2 FIG. is a schematic structural diagram of a second alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0026] Figure 3 FIG. is a schematic structural diagram of a third alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0027] Figure 4 FIG. is a schematic structural diagram of a fourth alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0028] Figure 5 FIG. is a schematic structural diagram of a fifth alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0029] Figure 6 FIG. is a schematic structural diagram of a sixth alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0030] Figure 7 FIG. is a schematic structural diagram of a seventh alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0031] Figure 8 FIG. is a schematic structural diagram of an eighth alternative embodiment of the bonding structure for a metal bonding area of a semiconductor wafer provided by the present utility model.

[0032] Figure 9 Schematic diagram of the bonding structure of the ninth alternative embodiment of the metal bonding area of the semiconductor wafer provided by the present utility model.

[0033] Figure 10 Schematic diagram of the bonding structure of the tenth alternative embodiment of the metal bonding area of the semiconductor wafer provided by the present utility model.

[0034] Figure 11 Schematic diagram of the bonding structure of the eleventh alternative embodiment of the metal bonding area of the semiconductor wafer provided by the present utility model.

[0035] Figure 12 Schematic diagram of the bonding structure of the twelfth alternative embodiment of the metal bonding area of the semiconductor wafer provided by the present utility model.

[0036] Reference numerals in the drawings

[0037] Semiconductor wafer 100, silicon dioxide layer 1, silicon dioxide base layer 11, silicon dioxide extension layer 12, metal bonding area 2, passivation metal layer 3, silicon nitride layer 4, peripheral protection layer 5, organic planarization layer 51, low-temperature oxide layer 52, first bending portion 61, second bending portion 62, third bending portion 63, fourth bending portion 64, upper end surface A of the silicon dioxide extension layer, upper end surface B of the passivation metal layer, lower end surface C of the metal bonding area, upper end surface D of the metal bonding area. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and effects of the present utility model clearer and more definite, the following further describes the present utility model in detail with reference to the accompanying drawings and by way of examples. It should be understood that the specific examples described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0039] It should be noted that when a component is referred to as being "mounted on", "fixed to" or "disposed on" another component, it can be directly on the other component or there may be an intermediate component at the same time. When a component is referred to as being "connected to" another component, it can be directly connected to the other component or there may be an intermediate component at the same time.

[0040] It should also be noted that the terms of orientation such as left, right, up, and down in the embodiments of the present utility model are only relative concepts to each other or are referenced based on the normal use state of the product, and should not be considered as restrictive.

[0041] The semiconductor wafers produced in the processing factory are all bare chips. The bonding pads on such bare chips are usually not directly applied to the actual circuit board. Since bare chips are extremely vulnerable to the temperature, impurities, and physical forces of the external environment and are easily damaged, the bonding pads must be led out with corresponding pins through packaging before they can be used as a basic component chip.

[0042] Generally, bonding wires are used to bind the bonding areas on the bare chip and the pins on the package. In the prior art, the bonding structure of the bonding area usually has a silicon dioxide layer provided on the semiconductor wafer. The silicon dioxide layer forms a cavity structure to cover the metal bonding area, and the end face of the metal bonding area is exposed, resulting in problems such as poor corrosion resistance of the metal bonding area, low reliability of bonding and welding points, and increased resistance.

[0043] The bonding structure of the metal bonding area of the semiconductor wafer in this application is mainly applied to lidar chips (including laser receiving chips and laser emitting chips), and specifically solves the strict requirements of lidar chips for different packaging forms; the metal bonding area is covered by a silicon dioxide layer, and a passivation metal layer is added above the metal bonding area. At the same time, a silicon nitride layer and / or a peripheral protective layer are added on the silicon dioxide layer to further protect the metal bonding layer, the silicon dioxide layer, and the passivation metal layer, increase the physical path for external substances to contaminate the metal bonding layer, specifically isolate impurities such as external corrosive gases and liquids, and enhance the corrosion resistance of the metal bonding area of the chip. The protection effect of the bare chips of the existing lidar chips is not good. The setting of the peripheral protective layer proposed in this application has a better improvement in the reliability of bonding and welding of the metal bonding area, and enables the chip to be used in a non-hermetic environment.

[0044] The present utility model provides a bonding structure for a metal bonding area of a semiconductor wafer. Please refer to Figures 1-6 , which includes a silicon dioxide layer 1 and a metal bonding area 2 provided in a cavity (not marked in the figure) defined by the silicon dioxide layer 1; the silicon dioxide layer 1 includes a silicon dioxide base layer 11 provided on the semiconductor wafer 100 and a silicon dioxide extension layer 12 extending upward from the silicon dioxide base layer 11 and located on the periphery of the metal bonding area 2; the silicon dioxide extension layer 12 covers the edges of the metal bonding area 2; a passivation metal layer 3 is provided above the metal bonding area 2, and the metal in the passivation metal layer 3 is a metal material that is not easily oxidized; a silicon nitride layer 4 is provided above the silicon dioxide layer 1.

[0045] In this application, the metal pressure welding area 2 is arranged on the silicon dioxide base layer 11, and the silicon dioxide extension layer 12 is made to cover the circumferential side and the edges of the upper end face of the metal pressure welding area 2. By arranging a silicon nitride layer 4 on the silicon dioxide layer 1 and arranging a passivation metal layer 3 above the metal pressure welding area 2, it is possible to prevent impurities such as water vapor and air from contacting the metal pressure welding area 2, thereby improving the stability of the bonding structure of the metal pressure welding area 2. It should be noted that the metal pressure welding area 2 is also a structure with a fixed shape. In addition, through holes are provided on the silicon dioxide base layer 11 below the cavity, and connecting members (not marked in the figure) are arranged in the through holes to electrically connect the metal pressure welding area 2 and the internal circuit of the semiconductor wafer 100.

[0046] Please refer to Figures 1-12 , in the attached drawings of this application, A is the upper end face of the silicon dioxide extension layer 12, B is the upper end face of the passivation metal layer 3, C is the upper end face of the metal pressure welding area 2, and D is the lower end face of the metal pressure welding area 2; the part below the lower end face of the metal pressure welding area 2 is the silicon dioxide base layer 11, and the part of the silicon dioxide layer 1 above the lower end face of the metal pressure welding area 2 is the silicon dioxide extension layer 12; the attached drawings are all symmetric about the left and right.

[0047] Generally, copper bonding wires are used. Copper, as a metal with low resistivity and strong electromigration resistance, may diffuse into adjacent materials, resulting in performance degradation. The silicon nitride layer 4 plays a blocking role and can effectively block the diffusion of copper atoms, thereby indirectly improving the electromigration resistance of the entire structure; at the same time, silicon nitride has stronger antioxidant and anti-corrosion capabilities. Arranging the silicon nitride layer 4 above the silicon dioxide layer 1 can further protect the circumferential side of the metal pressure welding area 2 from being affected by impurities such as water vapor and air. The silicon dioxide layer 1, as an insulating layer, covers the circumferential side and the edges of the upper end face of the metal pressure welding area 2, which helps to improve the stability of the bonding structure of the metal pressure welding area 2 connected to the bonding wire. The passivation metal layer 3 can be made of metals that are not easily oxidized, such as nickel, palladium, gold, nickel-gold, nickel-palladium, etc. Arranging the passivation metal layer 3 above the metal pressure welding area 2 can prevent the upper end face of the metal pressure welding area 2 from being oxidized.

[0048] Please refer to Figure 1, in the first optional embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11. The silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the peripheral side and the edge of the upper end surface of the metal bonding area 2. The passivation metal layer 3 is disposed above the metal bonding area 2. The upper end surface of the silicon dioxide extension layer 12 is lower than the upper end surface of the passivation metal layer 3. The silicon dioxide base layer 11 outside the silicon dioxide extension layer 12 and the peripheral side of the silicon dioxide extension layer 12 are both provided with a silicon nitride layer 4. The passivation metal layer 3 partially covers the horizontal portion of the silicon nitride layer 4 above the silicon dioxide extension layer 12. In this embodiment, the silicon nitride layer 4 and the silicon dioxide layer protect the peripheral side and the edge of the upper end surface of the metal bonding area 2. The passivation metal layer 3 is in contact with the upper end surface of the metal bonding area 2 and completely covers the metal bonding area 2, effectively isolating external moisture, air and other impurities from the metal bonding area 2.

[0049] Please refer to Figure 2 , in the second optional embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11. The passivation metal layer 3 is disposed on the metal bonding area 2. The silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the peripheral side of the metal bonding area 2, the edge of the upper end surface of the metal bonding area 2 and the peripheral side of the passivation metal layer 3. The upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3. A silicon nitride layer 4 is horizontally disposed above the silicon dioxide extension layer 12. In the embodiment of the present application, on the basis of completely covering the metal bonding area 2, the peripheral side of the passivation metal layer 3 is further covered, reducing the contact surface between the passivation metal layer 3 and external impurities and improving the service life of the passivation metal layer 3.

[0050] Please refer to Figures 3-6 , a peripheral side protection layer 5 is disposed above the silicon nitride layer 4. The peripheral side protection layer 5 includes at least one of an organic planarization layer 51 and a low-temperature oxide layer 52.

[0051] In the embodiment of the present application, the peripheral side protection layer 5 can be an organic planarization layer 51, a low-temperature oxide layer 52, or a combined layer of an organic planarization layer 51 and a low-temperature oxide layer 52; the organic planarization layer 51 can be selected from organic glue or a material with similar functions; the low-temperature oxide layer 52 can be selected from silicon dioxide, silicon nitride or a material with similar functions produced in a low-temperature form. The peripheral side protection layer 5 is disposed above the silicon nitride layer 4, increasing the physical path for external impurities to contact the metal bonding area 2 and indirectly enhancing the protection ability for the metal bonding area 2.

[0052] It should be noted that in the embodiments of the present application, the reason why the silicon dioxide extension layer 12 and the silicon nitride layer 4 cannot cover the edges of the upper end surface of the passivation metal layer 3 is determined by the chip processing sequence; specifically, the reason is that the silicon dioxide layer 1, the silicon nitride layer 4, and the metal bonding pad area 2 are fabricated in a chip manufacturing factory, which belong to the pre-processing steps, and the passivation metal layer 3 and the peripheral protection layer 5 are fabricated by other manufacturers, which belong to the post-processing steps. After the pre-processing steps are completed, a space for accommodating the passivation metal layer 3 is opened in the silicon nitride layer 4 and the silicon dioxide layer 1 by etching or other means, and the upper end surface of the metal bonding pad area 2 is exposed. The passivation metal layer 3 is deposited on the surface of the metal bonding pad area 2 by sputtering, electroplating, or other means, which belongs to the post-processing steps; if there is a part covering the edges of the upper end surface of the passivation metal layer 3 in the space opened after the pre-processing steps are completed, it will affect the deposition and generation of the passivation metal layer 3 in the subsequent processing steps.

[0053] Please refer to Figure 3 and Figure 4 , the upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3, and the side walls of the silicon dioxide extension layer 12 and the silicon nitride layer 4 are flush with the side walls of the passivation metal layer 3, that is, the silicon dioxide extension layer 12 and the silicon nitride layer 4 do not cover the edges of the upper end surface of the passivation metal layer 3. In the embodiments of the present application, the upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3, that is, the silicon dioxide extension layer 12 covers the periphery of the metal bonding pad area 2, the edges of the upper end surface of the metal bonding pad area 2, and the periphery of the passivation metal layer 3. By protecting the periphery of the passivation metal layer 3 with the silicon dioxide extension layer 12, the corrosion resistance and weather resistance of the passivation metal layer 3 are improved, and thus the protection ability of the metal bonding pad area 2 is indirectly improved.

[0054] Furthermore, at least one of the organic planarization layer 51 and the low-temperature oxide layer 52 is in contact with the upper end surface of the passivation metal layer 3 and covers the edges of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3. At least one of the organic planarization layer 51 and the low-temperature oxide layer 52, that is, the organic planarization layer 51, or the low-temperature oxide layer 52, or a combined layer of the organic planarization layer 51 and the low-temperature oxide layer 52; at least one of the organic planarization layer 51 and the low-temperature oxide layer 52 extends towards the passivation metal layer 3 with a bent portion, and the lower end surface of the bent portion is in contact with the upper end surface of the passivation metal layer 3; the silicon nitride layer 4 is located above the silicon dioxide extension layer 12, and at least one of the organic planarization layer 51 and the low-temperature oxide layer 52 covers the edges of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3, that is, it also covers the edges of the silicon nitride layer 4 on the same side. The advantage of the above structure is that it can effectively prevent impurities such as water vapor and air from entering the contact part between the silicon dioxide extension layer 12 and the passivation metal layer 3, and improves the reliability of the protection of the metal bonding pad area 2.

[0055] Please refer to Figure 3 , in the third optional embodiment of the present application, the metal pressure welding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed on the metal pressure welding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal pressure welding area 2 covers the periphery of the metal pressure welding area 2, the edge of the upper end face of the metal pressure welding area 2, and the periphery of the passivation metal layer 3. The upper end face of the silicon dioxide extension layer 12 is higher than the upper end face of the passivation metal layer 3. A silicon nitride layer 4 is horizontally disposed above the silicon dioxide extension layer 12, and a low-temperature oxide layer 52 is disposed above the silicon nitride layer 4. The low-temperature oxide layer 52 extends toward the passivation metal layer 3 with a first bending portion 61. The low-temperature oxide layer 52 covers the edge of the silicon nitride layer 4 and the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3, and the lower end face of the first bending portion 61 of the low-temperature oxide layer 52 is in contact with the upper end face of the passivation metal layer 3. The setting of the low-temperature oxide layer 52 prevents the upper end face of the silicon nitride layer 4, the edge of the upper end face of the silicon nitride layer 4 on the side close to the passivation metal layer 3, and the edge of the upper end face of the silicon dioxide extension layer 12 from being oxidized, avoids impurities such as water vapor and air from entering the metal pressure welding area 2 from the contact portion between the silicon dioxide extension layer 12 and the passivation metal layer 3, and achieves good isolation between the metal pressure welding area 2 and the outside world, enhancing the oxidation resistance and corrosion resistance of the metal oxidation area. Of course, the low-temperature oxide layer 52 in this embodiment can also be replaced by an organic planarization layer 51, and the structure is similar to that of the above embodiment, which will not be elaborated herein.

[0056] Please refer to Figure 4, in the fourth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed on the metal bonding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the periphery of the metal bonding area 2, the edge of the upper end face of the metal bonding area 2, and the periphery of the passivation metal layer 3. The upper end face of the silicon dioxide extension layer 12 is higher than the upper end face of the passivation metal layer 3. A silicon nitride layer 4 is horizontally disposed above the silicon dioxide extension layer 12. An organic planarization layer 51 is disposed above the silicon nitride layer 4. The organic planarization layer 51 extends toward the passivation metal layer 3 with a second bending portion 62. The organic planarization layer 51 covers the edges of the silicon nitride layer 4 and the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3, and the lower end face of the second bending portion 62 of the organic planarization layer 51 is in contact with the upper end face of the passivation metal layer 3. A low-temperature oxide layer 52 is horizontally disposed above the organic planarization layer 51. In this embodiment, the organic planarization layer 51 and the low-temperature oxide layer 52 are sequentially added on the silicon nitride layer 4. While increasing the physical path for external impurities to contact the metal bonding area 2, the edges of the silicon nitride layer 4 and the silicon dioxide layer 1 are also protected, preventing impurities from entering the contact portion between the silicon dioxide extension layer 12 and the passivation metal layer 3, improving the protection ability of the passivation metal layer 3 and the silicon dioxide extension layer 12, and increasing the reliability of the protection of the metal bonding area 2. Of course, in this embodiment, the organic planarization layer 51 can also be disposed above the low-temperature oxide layer 52, and its structure is similar to that of the above embodiment, which will not be elaborated herein.

[0057] Please refer to FIGS. 5 and Figure 6 , the upper end face of the silicon dioxide extension layer 12 is lower than the upper end face of the passivation metal layer 3. At least one of the organic planarization layer 51 and the low-temperature oxide layer 52 covers the edge of the passivation metal layer 3.

[0058] Please refer to Figure 5 , in the fifth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed above the metal bonding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the periphery of the metal bonding area 2 and the edge of the upper end face. The silicon nitride layer 4 is horizontally disposed on the silicon dioxide extension layer 12. The passivation metal layer 3 partially covers the silicon nitride layer 4. An organic planarization layer 51 is disposed above the silicon nitride layer 4. The upper end face of the organic planarization layer 51 is higher than the upper end face of the passivation metal layer 3, and the organic planarization layer 51 covers the periphery and the edge of the upper end face of the passivation metal layer 3. A low-temperature oxide layer 52 is horizontally disposed above the organic planarization layer 51.

[0059] Please refer to Figure 6, in the sixth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11. The silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the peripheral side and the edge of the upper end face of the metal bonding area 2, and the upper end face of the silicon dioxide extension layer 12 is lower than the upper end face of the passivation metal layer 3. The silicon nitride layer 4 is horizontally disposed on the silicon dioxide extension layer 12. The passivation metal layer 3 is disposed above the metal bonding area 2, and the passivation metal layer 3 partially covers the silicon nitride layer 4. A low-temperature oxide layer 52 is disposed above the silicon nitride layer 4, and the low-temperature oxide layer 52 covers the peripheral side and the edge of the upper end face of the passivation metal layer 3.

[0060] Please refer to Figures 1-12 , the thickness of the passivation metal layer 3 is 0.1 μm - 5 μm. When an organic planarization layer 51 and a low-temperature oxide layer 52 are disposed above the silicon nitride layer 4, the thickness of the organic planarization layer 51 is greater than the thickness of the low-temperature oxide layer 52. The thickness of the organic planarization layer 51 is 0.1 μm - 0.5 μm, and the thickness of the low-temperature oxide layer 52 is 0.01 μm - 0.2 μm. The thickness of the silicon dioxide base layer 11 outside the silicon dioxide extension layer 12 is 0.1 μm - 5 μm.

[0061] In the embodiment of the present application, due to process limitations and performance and cost considerations, the low-temperature oxide layer 52 and the silicon nitride layer 4 can only be made very thin, while the silicon dioxide layer 1, the organic planarization layer 51, and the passivation metal layer 3 can be made thick; preferably, the thickness of the passivation metal layer 3 is 0.3 μm; the thickness of the low-temperature oxide layer 52 is 0.1 μm. In the first to sixth alternative embodiments, a passivation metal layer 3 is disposed above the metal bonding area 2, and a silicon nitride layer 4 and a peripheral protection layer 5 are sequentially disposed above the silicon dioxide layer 1; various bonding structures of the metal bonding area 2 can be formed by adjusting the thickness of the silicon dioxide layer 1, selecting the peripheral protection layer 5, and adjusting the thickness of the organic planarization layer 51 when selecting the organic planarization layer 51 to protect the metal bonding area 2; it should be noted that on the basis of the first to sixth alternative embodiments, due to the adjustable thickness of the silicon dioxide layer 1 and the adjustable thickness of the organic planarization layer 51 when selecting the organic planarization layer 51, other forms of bonding structures of the metal bonding area 2 can also be formed, and the transformation is foreseeable and still falls within the protection scope of the present application. The seventh to twelfth alternative embodiments correspond to the first to sixth alternative embodiments in sequence, except that the silicon nitride layer 4 is not disposed above the silicon dioxide extension portion. The structures of the seventh to twelfth alternative embodiments will also form various bonding structures due to the adjustable thickness of the silicon dioxide layer 1 and the adjustable thickness of the organic planarization layer 51 when selecting the organic planarization layer 51, and the transformation is foreseeable and still falls within the protection scope of the present application.

[0062] The present application also correspondingly provides another bonding structure for the metal bonding area 2 of a semiconductor wafer. Please refer toFigures 7-12 , including a silicon dioxide layer 1 and a metal bonding area 2 disposed in a cavity defined by the silicon dioxide layer 1; the silicon dioxide layer 1 includes a silicon dioxide base layer 11 disposed on a semiconductor wafer 100 and a silicon dioxide extension layer 12 extending upward from the silicon dioxide base layer 11 and located on the periphery of the metal bonding area 2; the silicon dioxide extension layer 12 covers the edges of the metal bonding area 2; a passivation metal layer 3 is disposed above the metal bonding area 2, and the metal in the passivation metal layer 3 is a metal material that is not easily oxidized.

[0063] Please refer to Figure 7 , in the seventh alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the periphery and the edge of the upper end face of the metal bonding area 2. The passivation metal layer 3 is disposed above the metal bonding area 2, the upper end face of the silicon dioxide extension layer 12 is lower than the upper end face of the passivation metal layer 3, and the passivation metal layer 3 partially covers the horizontal part of the silicon dioxide extension layer 12.

[0064] Please refer to Figure 8 , in the eighth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed on the metal bonding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding area 2 covers the periphery of the metal bonding area 2, the edge of the upper end face of the metal bonding area 2, and the periphery of the passivation metal layer 3. The upper end face of the silicon dioxide extension layer 12 is higher than the upper end face of the passivation metal layer 3. Of course, alternatively, since the height of the silicon dioxide extension layer 12 is adjustable, the upper end face of the silicon dioxide extension layer 12 may also be lower than the upper end face of the passivation metal layer 3, but the upper end face of the silicon dioxide extension layer 12 needs to be higher than the upper end face of the metal bonding area 2 to achieve covering the edge of the upper end face of the metal bonding area 2.

[0065] Please refer to Figures 9-12 , a peripheral protective layer 5 is disposed above the silicon dioxide extension layer 12, and the peripheral protective layer 5 includes at least one of an organic planarization layer 51 and a low-temperature oxide layer 52.

[0066] In the embodiment of the present application, the peripheral protective layer 5 may be an organic planarization layer 51, a low-temperature oxide layer 52, or a combined layer of the organic planarization layer 51 and the low-temperature oxide layer 52; the organic planarization layer 51 may be selected from organic glue or a material with similar functions; the low-temperature oxide layer 52 may be selected from silicon dioxide, silicon nitride or a material with similar functions made in a low-temperature form. The reason why the silicon dioxide extension layer 12 cannot cover the edge of the upper end face of the passivation metal layer 3 has been described above and will not be elaborated here.

[0067] Please refer to Figure 9 andFigure 10 The upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3, and the side wall of the silicon dioxide extension layer 12 is flush with the side wall of the passivation metal layer 3, that is, the silicon dioxide extension layer 12 does not cover the edge of the upper end surface of the passivation metal layer 3. At least one of the organic planarization layer 51 and the low-temperature oxide layer 52 covers the edge of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3.

[0068] Please refer to Figure 9 In the ninth alternative embodiment of the present application, the metal bonding pad area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed on the metal bonding pad area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the side wall of the metal bonding pad area 2 covers the periphery of the metal bonding pad area 2, the edge of the upper end surface of the metal bonding pad area 2, and the periphery of the passivation metal layer 3. The upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3. A low-temperature oxide layer 52 is disposed above the silicon dioxide extension layer 12. The low-temperature oxide layer 52 extends toward the passivation metal layer 3 with a third bending portion 63. The low-temperature oxide layer 52 covers the edge of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3, and the lower end surface of the third bending portion 63 of the low-temperature oxide layer 52 contacts the upper end surface of the passivation metal layer 3. The setting of the low-temperature oxide layer 52 prevents the upper end surface of the silicon dioxide extension layer 12 and the edge of the upper end surface of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3 from being oxidized, and avoids impurities such as water vapor and air from entering the metal bonding pad area 2 from the contact portion between the silicon dioxide extension layer 12 and the passivation metal layer 3, so that the metal bonding pad area 2 is well isolated from the outside, enhancing the oxidation resistance and corrosion resistance of the metal bonding pad area 2. Of course, in this embodiment, the low-temperature oxide layer 52 can also be replaced by the organic planarization layer 51, and the structure is similar to the above embodiment, which will not be elaborated herein.

[0069] Please refer to Figure 10, in the tenth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed on the metal bonding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the sidewall of the metal bonding area 2 covers the periphery of the metal bonding area 2, the edges of the upper end surface of the metal bonding area 2, and the periphery of the passivation metal layer 3. The upper end surface of the silicon dioxide extension layer 12 is higher than the upper end surface of the passivation metal layer 3. An organic planarization layer 51 is disposed above the silicon dioxide extension layer 12. The organic planarization layer 51 extends toward the passivation metal layer 3 with a fourth bending portion 64. The organic planarization layer 51 covers the edges of the silicon dioxide extension layer 12 on the side close to the passivation metal layer 3, and the lower end surface of the fourth bending portion 64 of the organic planarization layer 51 is in contact with the upper end surface of the passivation metal layer 3. A low-temperature oxide layer 52 is horizontally disposed above the organic platform layer. Of course, in this embodiment, the organic planarization layer 51 may also be disposed above the low-temperature oxide, and its structure is similar to that of the above embodiment, which will not be elaborated herein.

[0070] Please refer to Figure 11 and Figure 12 , the upper end surface of the silicon dioxide extension layer 12 is lower than the upper end surface of the passivation metal layer 3. At least one of the organic planarization layer 51 and the low-temperature oxide layer 52 covers the edges of the passivation metal layer 3.

[0071] Please refer to Figure 11 , in the eleventh alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, the passivation metal layer 3 is disposed above the metal bonding area 2, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the sidewall of the metal bonding area 2 covers the periphery of the metal bonding area 2 and the edges of the upper end surface. The passivation metal layer 3 partially covers the horizontal portion of the silicon dioxide extension layer 12. An organic planarization layer 51 is disposed above the silicon dioxide layer 1. The organic planarization layer 51 covers the side edges and the edges of the upper end surface of the passivation metal layer 3. A low-temperature oxide layer 52 is horizontally disposed above the organic planarization layer 51.

[0072] Please refer to Figure 12 , in the twelfth alternative embodiment of the present application, the metal bonding area 2 is disposed on the silicon dioxide base layer 11, and the silicon dioxide extension layer 12 formed by the silicon dioxide base layer 11 extending upward along the sidewall of the metal bonding area 2 covers the periphery of the metal bonding area 2 and the edges of the upper end surface, and the upper end surface of the silicon dioxide extension layer 12 is lower than the upper end surface of the passivation metal layer 3. The passivation metal layer 3 is disposed above the metal bonding area 2, and the passivation metal layer 3 partially covers the horizontal portion of the silicon dioxide extension layer 12. A low-temperature oxide layer 52 is disposed above the silicon dioxide extension layer 12, and the low-temperature oxide layer 52 covers the periphery of the passivation metal layer 3 and the edges of the upper end surface.

[0073] In the seventh to twelfth embodiments, a passivation metal layer 3 is disposed above the metal bonding area 2, and a peripheral protective layer 5 is disposed above the silicon dioxide layer 1; various bonding structures of the metal bonding area 2 can be formed by adjusting the thickness of the silicon dioxide layer 1, selecting the peripheral protective layer 5, and adjusting the thickness of the organic planarization layer 51 when selecting it to protect the metal bonding area 2; it should be noted that based on the seventh to twelfth embodiments, due to the adjustable thickness of the silicon dioxide layer 1 and the adjustable thickness of the organic planarization layer 51 when selecting it, other forms of bonding structures of the metal bonding area 2 can also be formed, and its transformation is predictable and still falls within the protection scope of this application.

[0074] Adopting the bonding structure of the metal bonding area 2 of this application to protect the metal bonding area 2, the beneficial effects are as follows: 1. Corrosion resistance and weather resistance: The metal bonding area 2 of the chip is completely coated by the silicon dioxide layer 1 and the passivation metal layer 3, improving the corrosion resistance of the metal bonding area 2 of the chip, enabling the chip to be used in a more severe environment after welding; 2. Bonding and welding reliability: By improving the reliability of the bonding and welding at the metal bonding area 2 of the chip, the bonding at the bonding and welding positions on the metal bonding area 2 is better, making the resistance value of the bonding and welding positions smaller, ensuring the stability of the parameters during the use of the chip; 3. Electromigration resistance: The silicon nitride layer 4 above the silicon dioxide layer 1 can play a blocking role when the bonding wire is connected to the bonding structure of the metal bonding area 2, effectively blocking the diffusion of copper atoms. At the same time, the silicon nitride has good chemical stability and can resist the erosion of various chemical substances, helping to maintain the integrity and reliability of the structure, thereby indirectly improving the electromigration resistance of the entire structure.

[0075] In summary, a bonding structure of a semiconductor wafer metal bonding area provided by the present utility model includes a silicon dioxide layer and a metal bonding area disposed in a cavity defined by the silicon dioxide layer; the silicon dioxide layer includes a silicon dioxide base layer disposed on the semiconductor wafer and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edges of the metal bonding area; a passivation metal layer is disposed above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized; a silicon nitride layer is disposed above the silicon dioxide layer.

[0076] In this application, the metal bonding area is disposed on the silicon dioxide base layer, and the silicon dioxide extension layer covers the periphery and the edge of the upper end surface of the metal bonding area. By disposing a silicon nitride layer on the silicon dioxide layer and a passivation metal layer above the metal bonding area, it is possible to prevent impurities such as water vapor and air from contacting the metal bonding area, thereby improving the stability of the bonding structure of the metal bonding area.

[0077] It is understandable that for those of ordinary skill in the art, equivalent substitutions or modifications can be made according to the technical solution of the present utility model and its inventive concept, and all such modifications or substitutions should fall within the protection scope of the claims appended to the present utility model.

Claims

1. A bonding structure of a metal bonding area of ​​a semiconductor wafer, characterized in that: It comprises a silicon dioxide layer and a metal bonding area arranged in a cavity defined by the silicon dioxide layer; the silicon dioxide layer comprises a silicon dioxide base layer arranged on a semiconductor wafer, and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edges of the metal bonding area; a passivation metal layer is arranged above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized; a silicon nitride layer is arranged above the silicon dioxide layer.

2. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 1, characterized in that: A peripheral protective layer is disposed above the silicon nitride layer, and the peripheral protective layer includes at least one of an organic planarization layer and a low temperature oxide layer.

3. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 2, characterized in that: The upper end surface of the silicon dioxide extension layer is higher than the upper end surface of the passivation metal layer, and the side walls of the silicon dioxide layer and the silicon nitride layer are flush with the side walls of the passivation metal layer.

4. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 3, characterized in that: At least one of the organic planarization layer and the low temperature oxide layer covers an edge of the silicon dioxide extension layer close to a side of the passivation metal layer.

5. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 2, characterized in that: The upper end surface of the silicon dioxide extension layer is lower than the upper end surface of the passivation metal layer.

6. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 5, characterized in that: At least one of the organic planarization layer and the low temperature oxide layer covers the edge of the passivation metal layer.

7. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 1, characterized in that: The thickness of the passivation metal layer is 0.1 μm-5 μm.

8. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 2, characterized in that: When an organic planarization layer and a low temperature oxide layer are disposed above the silicon nitride layer, the thickness of the organic planarization layer is greater than the thickness of the low temperature oxide layer.

9. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 2, characterized in that: The thickness of the organic planar layer is 0.1 μm-0.5 μm, and the thickness of the low-temperature oxide layer is 0.01 μm-0.5 μm.

10. A bonding structure of a metal bonding area of ​​a semiconductor wafer, characterized in that: It includes a silicon dioxide layer and a metal bonding area arranged in a cavity defined by the silicon dioxide layer; the silicon dioxide layer includes a silicon dioxide base layer arranged on a semiconductor wafer, and a silicon dioxide extension layer extending upward from the silicon dioxide base layer and located on the periphery of the metal bonding area; the silicon dioxide extension layer covers the edges of the metal bonding area; a passivation metal layer is arranged above the metal bonding area, and the metal in the passivation metal layer is a metal material that is not easily oxidized.

11. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 10, characterized in that: A peripheral protective layer is disposed above the silicon dioxide extension layer, and the peripheral protective layer includes at least one of an organic flat layer and a low temperature oxide layer.

12. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 11, characterized in that: The upper end surface of the silicon dioxide extension layer is higher than the upper end surface of the passivation metal layer, and the side wall of the silicon dioxide extension layer is flush with the side wall of the passivation metal layer.

13. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 12, characterized in that: At least one of the organic planarization layer and the low temperature oxide layer covers the edge of the silicon dioxide extension layer close to the passivation metal layer.

14. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 11, characterized in that: The upper end surface of the silicon dioxide extension layer is lower than the upper end surface of the passivation metal layer.

15. The bonding structure of the metal bonding area of ​​the semiconductor wafer according to claim 14, characterized in that: At least one of the organic planarization layer and the low temperature oxide layer covers the edge of the passivation metal layer.

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