Low-stray agile frequency source module

Abstract

The utility model discloses a low stray agile frequency source module, which comprises an FPGA control circuit board, a clock circuit module, a power divider circuit module, a phase-locked loop circuit module, an amplification filter circuit module and a storage circuit module, the storage circuit module is integrated in the FPGA control circuit board, the FPGA control circuit board is provided with a radio frequency circuit shielding box body, and the FPGA control circuit board is provided with a radio frequency circuit shielding box body. The clock circuit module, the power divider circuit module, the phase-locked loop circuit module and the amplification filter circuit module are arranged in the radio frequency circuit shielding box body; the FPGA control circuit board is further provided with a power supply socket and a serial port socket. The periphery of the FPGA control circuit board is also provided with a frequency source shielding box body, and the top end and the bottom end of the frequency source shielding box body are of an open structure. According to the utility model, the frequency source locking time is greatly reduced, the electromagnetic shielding and filtering effects of the frequency source module are good, the disassembly and assembly are convenient, the structure is compact, and the occupied space is small; and the power supply has the advantages of good grounding, effective heat dissipation and the like.

Description

Technical Field

[0001] The utility model relates to the technical field of frequency sources, and particularly relates to a low-spurious agile frequency source module. Background Technique

[0002] Frequency hopping communication refers to a method of using a pseudo-random code sequence for frequency shift keying to continuously hop the carrier frequency and expand the spectrum. In a frequency hopping communication system, the frequency source provides the local oscillator signal for the transceiver channel and generates the carrier frequency, which is the core part of the system. The phase-locked loop frequency synthesizer, as a frequency source, has the advantages of a wide frequency range, good spurious suppression, and low phase noise, and is widely used. The locking time of the phase-locked loop frequency synthesizer is a key index of the frequency hopping communication system, which directly determines the frequency hopping rate and further determines the anti-interference ability of the system;

[0003] Facing the complex electromagnetic environment, the frequency hopping rate of modern data link frequency hopping communication is getting higher and higher, and the electromagnetic environment is getting more and more complex. This requires the frequency source to be able to lock more quickly, and the electromagnetic shielding and spurious suppression to be better; Patent Publication No. CN115940941A discloses a frequency source for data link frequency hopping communication, which solves the problem of long locking time of the frequency source for data link frequency hopping communication by using domestic hardware, but there are problems such as poor electromagnetic shielding and filtering effects. Content of the Utility Model

[0004] The technical problem to be solved by the utility model is to overcome the existing defects, and provide a low-spurious agile frequency source module, which greatly reduces the locking time of the frequency source, has good electromagnetic shielding and filtering effects for the frequency source module, has a simple connection structure, is firmly fixed, is convenient to disassemble and assemble, is compact in structure and small in occupied space; and has good grounding and effective heat dissipation, and can effectively solve the problems in the background technique.

[0005] To achieve the above object, the utility model provides the following technical solution: A low-spurious agile frequency source module, including an FPGA control circuit board, a clock circuit module, a power splitter circuit module, a phase-locked loop circuit module, an amplification and filtering circuit module, and a storage circuit module. The storage circuit module is integrated in the FPGA control circuit board. There is a radio frequency circuit shielding box body on the FPGA control circuit board. The radio frequency circuit shielding box body has two independent radio frequency circuit shielding cavities, and the clock circuit module and the power splitter circuit module are arranged in one of the radio frequency circuit shielding cavities, and the phase-locked loop circuit module and the amplification and filtering circuit module are arranged in the other radio frequency circuit shielding cavity; There is also a power supply socket and a serial port socket on the FPGA control circuit board; The periphery of the FPGA control circuit board is also provided with a frequency source shielding box body. The FPGA control circuit board is arranged in the frequency source shielding cavity of the frequency source shielding box body, and the top and bottom of the frequency source shielding box body are both open structures.

[0006] Furthermore, a plurality of fixed ear plates are provided along the outer edge at the bottom of the outer wall of the radio frequency circuit shielding box body. Fixing holes are formed at positions on the FPGA control circuit board corresponding to the fixed ear plates. The radio frequency circuit shielding box body is fixedly connected to the FPGA control circuit board through screws passing through the connection holes 1 on the fixed ear plates and the fixing holes.

[0007] Furthermore, the clock circuit module is integrated in the power splitter circuit module, and the amplification and filtering circuit module is integrated in the phase-locked loop circuit module; a radio frequency connector is provided on the partition between the radio frequency circuit shielding cavities, and the power splitter circuit module and the phase-locked loop circuit module are connected through the radio frequency connector. A radio frequency output socket is provided on an outer wall of the radio frequency circuit shielding box body corresponding to the phase-locked loop circuit module; a plurality of feedthrough capacitor terminals are further provided on the outer wall of the radio frequency circuit shielding box body, and the power splitter circuit module and the phase-locked loop circuit module are connected to the FPGA control circuit board through the feedthrough capacitor terminals.

[0008] Furthermore, connection ear plates are provided at the corners at the bottom end of the radio frequency circuit shielding cavity in the radio frequency circuit shielding box body. The power splitter circuit module and the phase-locked loop circuit module respectively abut against the connection ear plates in the corresponding radio frequency circuit shielding cavities, and connection studs are connected to the connection ear plates; a threaded convex shaft is provided at the bottom of the connection stud, and the threaded convex shaft is threadedly connected to the connection ear plate. The threaded convex shafts respectively penetrate through the corresponding power splitter circuit module and phase-locked loop circuit module, and the shoulder of the connection stud abuts against the upper end surfaces of the corresponding power splitter circuit module and phase-locked loop circuit module; a threaded blind hole is formed in the axial direction at the top end of the connection stud, a cover plate is provided at the top of the radio frequency circuit shielding box body, connection holes 2 are formed at positions on the cover plate corresponding to the connection studs, and the cover plate is fixed on the connection studs through screws passing through the connection holes 2 and the threaded blind holes, and the bottom surface of the cover plate abuts against the top surface of the radio frequency circuit shielding box body.

[0009] Furthermore, the bottom of the radio frequency circuit shielding box body is of a hollow structure, and signal ground copper plating is provided on the FPGA control circuit board at a position corresponding to the radio frequency circuit shielding box body.

[0010] Compared with the prior art, the beneficial effects of the present utility model are as follows: for this low-spurious frequency agile source module, the FPGA control circuit board extracts the VCO segment code value corresponding to the frequency from the storage circuit module through the IC bus interface. When configuring the frequency information for the phase-locked loop circuit module, it writes to the register regh of the VCO, thus quickly finding the sub-segment of the VCO, eliminating the time for VCO automatic calibration, and greatly reducing the locking time of the phase-locked loop circuit module; through the radio frequency circuit shielding box body and its provided radio frequency connector, radio frequency output socket, and through the secondary electromagnetic shielding and filtering effects provided by the frequency source shielding box body, the electromagnetic shielding and filtering effects of the frequency source are further increased; the connection structure between the radio frequency circuit and the radio frequency circuit shielding box body and between the radio frequency circuit shielding box bodies is simple, fixedly reliable, convenient for disassembly and assembly, with a compact structure and small occupied space; the frequency source has advantages such as good grounding and effective heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic structural diagram of the present utility model;

[0012] Figure 2 is a top view of the present utility model;

[0013] Figure 3 is a schematic connection structure diagram of the FPGA control circuit module and the radio frequency circuit shielding box body of the present utility model;

[0014] Figure 4 is an exploded view of the present utility model;

[0015] Figure 5 is a schematic connection stud structure diagram of the present utility model;

[0016] Figure 6 is a schematic structure diagram of the radio frequency circuit shielding box body of the present utility model;

[0017] Figure 7 is a circuit connection diagram of the present utility model.

[0018] In the figure: 1. FPGA control circuit board; 101. Signal ground copper cladding; 102. Fixing hole; 2. Clock circuit module; 3. Power splitter circuit module; 4. Phase-locked loop circuit module; 5. Amplification and filtering circuit module; 6. Radio frequency circuit shielding box body; 61. Radio frequency circuit shielding cavity; 62. Fixed ear plate; 63. Feedthrough capacitor terminal; 64. Radio frequency connector; 65. Radio frequency output socket; 66. Connection ear plate; 67. Cover plate; 7. FPGA control circuit chip; 8. Frequency source shielding box body; 81. Frequency source shielding cavity; 9. Connection stud; 91. Threaded convex shaft; 92. Threaded blind hole; 10. Power supply socket; 11. Serial port socket; 12. Storage circuit module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Embodiment

[0020] Please refer to Figure 1-7 , the present invention provides a technical solution: a low-spurious agile frequency source module, including an FPGA control circuit board 1, a clock circuit module 2, a power splitter circuit module 3, a phase-locked loop circuit module 4, an amplification and filtering circuit module 5, and a storage circuit module 12. An FPGA control circuit chip 7 is provided on the FPGA control circuit board 1. The storage circuit module 12 is integrated in the FPGA control circuit board 1. A radio frequency circuit shielding box body 6 is provided on the FPGA control circuit board 1. The radio frequency circuit shielding box body 6 has two independent radio frequency circuit shielding cavities 61. The clock circuit module 2 and the power splitter circuit module 3 are arranged in one of the radio frequency circuit shielding cavities 61, and the phase-locked loop circuit module 4 and the amplification and filtering circuit module 5 are arranged in the other radio frequency circuit shielding cavity 61. The clock circuit module 2 is integrated in the power splitter circuit module 3, and the amplification and filtering circuit module 5 is integrated in the phase-locked loop circuit module 4. A radio frequency connector 64 is provided on the partition between the radio frequency circuit shielding cavities 61. The power splitter circuit module 3 and the phase-locked loop circuit module 4 are connected through the radio frequency connector 64. A radio frequency output socket 65 is provided on an outer wall of the radio frequency circuit shielding box body 6 corresponding to the phase-locked loop circuit module 4. A plurality of feedthrough capacitor terminals 63 are further provided on the outer wall of the radio frequency circuit shielding box body 6. The power splitter circuit module 3 and the phase-locked loop circuit module 4 are connected to the FPGA control circuit board 1 through the feedthrough capacitor terminals 63. A power supply socket 10 and a serial port socket 11 are further provided on the FPGA control circuit board 1. The radio frequency connector 64 in this embodiment is an SMP radio frequency connector, and the radio frequency output socket 65 is an SMP radio frequency output socket 65.

[0021] A frequency source shielding box body 8 is further provided on the periphery of the FPGA control circuit board 1. The FPGA control circuit board 1 is arranged in a frequency source shielding cavity 81 of the frequency source shielding box body 8, and both the top and bottom of the frequency source shielding box body 8 are of open structures.

[0022] In this embodiment, the clock circuit module 2 selects a 50MHz oven-controlled crystal oscillator from Guangzhou Dapu Communication; the power splitter circuit module 3 selects BSBTC-2-10L from Zhuzhou Hongda; the phase-locked loop circuit module 4 selects the phase-locked loop chip X214 from Chongqing Southwest Integration; the amplifier and filter circuit module 5 selects the RF amplifier XA506 from Beijing Xinyueda and the low-pass filter BLF1700-3216 from Zhuzhou Hongda; the storage circuit module 12 selects the FM24C512DSO storage chip from Fudan Microelectronics; the FPGA control circuit chip 7 selects the FPGA chip JFM7K325T from Fudan Microelectronics; all devices of the frequency source select domestic devices to meet the requirements of domestic design;

[0023] The output end of the clock circuit module 2 is connected to the Com end of the power splitter circuit module 3; the Out1 and Out2 ends of the power splitter circuit module 3 are respectively connected to the Ref ends of the phase-locked loop circuit module 4 and the FPGA control circuit chip 7; the Rfout end of the phase-locked loop circuit module 4 is connected to the In end of the amplifier and filter circuit module 5; the SPI interface of the FPGA control circuit chip 7 is connected to the sck, sda, sen, and ld of the phase-locked loop of the phase-locked loop circuit module 4;

[0024] The clock circuit module 2 is composed of a 51.2MHz high-precision temperature-compensated crystal oscillator that provides a reference clock for the phase-locked loop circuit module 4 and the FPGA control circuit board 1; the power splitter circuit module 3 evenly divides the input 51.2MHz clock power into two reference clocks; the output frequency range of the phase-locked loop circuit module 4 is 25MHz to 6000MHz, and the frequency step can reach 3Hz, with the performance of low spurious and low phase noise; the amplifier and filter circuit module 5 is composed of an RF amplifier and a low-pass filter, mainly for amplifying and filtering the frequency and outputting a pure frequency signal; the storage circuit module 12 mainly completes the storage function of the VCO frequency segment code value; the FPGA control circuit board 1 mainly configures frequency information for the phase-locked loop circuit module 4 and communicates with the storage circuit module 12FM24C512DSO through the I 2 C bus interface to read the VCO frequency segment code value;

[0025] Working principle:

[0026] An external computer loads configuration information into the FPGA control circuit board 1 through the serial port socket 11. The FPGA control circuit board 1 initializes and configures the phase-locked loop circuit module 4 through the high-speed SPI interface. First, it is configured in the automatic VCO calibration mode, and a 1-MHz step frequency sweep is performed on the required local oscillator output frequency. The status bit of the lock detection ld is read. If ld is 1, it indicates that the phase-locked loop circuit module 4 has been locked. The VCO segment code values corresponding to each frequency during automatic phase locking are read through the reg10h register (reg10h<8:1> is the segment code value of the VCO), and are stored in the storage circuit module 12; a mapping table of the corresponding local oscillator output frequency and the VCO segment code is established; then it is initialized and configured in the manual VCO calibration mode. The FPGA control circuit board 1 extracts the VCO segment code value corresponding to this frequency from the storage circuit module 12 through the I 2 2C bus interface. When configuring the frequency information for the phase-locked loop circuit module 4, it writes to the register reg05h of the VCO, thereby quickly finding the sub-segment of the VCO, saving the time of VCO automatic calibration, and reducing the locking time to within 50 us;

[0027] The radio frequency circuit shielding box body 6 provides good electromagnetic shielding performance and filtering effect for the radio frequency circuit formed by the clock circuit module 2, the power divider circuit module 3, the phase-locked loop circuit module 4, and the amplifier and filter circuit module 5. The radio frequency circuit is connected through the radio frequency connector 64 and the radio frequency output socket 65. The secondary electromagnetic shielding and filtering effects provided by the frequency source shielding box body 8 further increase the electromagnetic shielding and filtering effects of the frequency source, making the spurious suppression reach more than 80 Db.

[0028] Further, a plurality of fixed ear plates 62 are provided along the outer edge at the bottom of the outer wall of the radio frequency circuit shielding box body 6. Fixing holes 102 are formed at positions on the FPGA control circuit board 1 corresponding to the fixed ear plates 62. The radio frequency circuit shielding box body 6 is fixedly connected to the FPGA control circuit board 1 by screws passing through the first connection holes on the fixed ear plates 62 and the fixing holes 102. Connection ear plates 66 are provided at the corners at the bottom end of the radio frequency circuit shielding cavity 61 inside the radio frequency circuit shielding box body 6. The power divider circuit module 3 and the phase-locked loop circuit module 4 are respectively abutted against the connection ear plates 66 in the corresponding radio frequency circuit shielding cavity 61, and connection studs 9 are connected to the connection ear plates 66. A threaded convex shaft 91 is provided at the bottom of the connection stud 9. The threaded convex shaft 91 is threadedly connected to the connection ear plate 66, and the threaded convex shaft 91 penetrates through the corresponding power divider circuit module 3 and phase-locked loop circuit module 4. The shoulder of the connection stud 9 abuts against the upper end surfaces of the corresponding power divider circuit module 3 and phase-locked loop circuit module 4. A threaded blind hole 92 is formed in the top end of the connection stud 9 along its axial direction. A cover plate 67 is provided at the top of the radio frequency circuit shielding box body 6. Second connection holes are formed at positions on the cover plate 67 corresponding to the connection studs 9. The cover plate 67 is fixed to the connection studs 9 by screws passing through the second connection holes and the threaded blind holes 92, and the bottom surface of the cover plate 67 abuts against the top surface of the radio frequency circuit shielding box body 6. The connection structure between the radio frequency circuit and the radio frequency circuit shielding box body 6 and between the radio frequency circuit shielding box bodies 6 is simple, firmly fixed, convenient to disassemble and assemble, compact in structure and small in occupied space.

[0029] Further, the bottom of the radio frequency circuit shielding box body 6 is of a hollow structure, and a signal ground copper plating 101 is provided on the FPGA control circuit board 1 at a position corresponding to the radio frequency circuit shielding box body 6, ensuring good grounding and effective heat dissipation of the frequency source.

[0030] In the low spurious agile frequency source module disclosed in this embodiment, the FPGA control circuit board 1 extracts the VCO segment code value corresponding to the frequency from the storage circuit module 12 through the I 2 C bus interface. When configuring the frequency information for the phase-locked loop circuit module 4, it writes to the register reg05h of the VCO, thereby quickly finding the sub-segment of the VCO, saving the time for VCO automatic calibration and greatly reducing the locking time of the phase-locked loop circuit module 4; through the radio frequency circuit shielding box body 6 and its provided radio frequency connector 64 and radio frequency output socket 65, and through the secondary electromagnetic shielding and filtering effects provided by the frequency source shielding box body 8, the electromagnetic shielding and filtering effects of the frequency source are further increased; the connection structure between the radio frequency circuit and the radio frequency circuit shielding box body 6 and between the radio frequency circuit shielding box bodies 6 is simple, firmly fixed, convenient to disassemble and assemble, compact in structure and small in occupied space; the frequency source has the advantages of good grounding and effective heat dissipation.

[0031] Although embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A low-spurious agile frequency source module, comprising an FPGA control circuit board, a clock circuit module, a power divider circuit module, a phase-locked loop circuit module, an amplification and filtering circuit module and a storage circuit module, characterized in that: The storage circuit module is integrated in the FPGA control circuit board. The FPGA control circuit board is provided with a radio frequency circuit shielding box body. The radio frequency circuit shielding box body is provided with two independent radio frequency circuit shielding cavities, and the clock circuit module and the power divider circuit module are arranged in one of the radio frequency circuit shielding cavities, and the phase-locked loop circuit module and the amplification and filtering circuit module are arranged in the other radio frequency circuit shielding cavity; the FPGA control circuit board is also provided with a power supply socket and a serial port socket; the periphery of the FPGA control circuit board is also provided with a frequency source shielding box body, the FPGA control circuit board is arranged in the frequency source shielding cavity of the frequency source shielding box body, and the top and bottom ends of the frequency source shielding box body are both open structures.

2. A low-spurious agile frequency source module according to claim 1, characterized in that: The bottom of the outer wall of the RF circuit shielding box body is provided with a plurality of fixing ear plates along its outer edge, and fixing holes are provided on the FPGA control circuit board at positions corresponding to the fixing ear plates, and the RF circuit shielding box body is fixedly connected to the FPGA control circuit board by screws penetrating the connection hole 1 and the fixing hole on the fixing ear plate.

3. The low-spurious agile frequency source module according to claim 1, characterized in that: The clock circuit module is integrated in the power divider circuit module, and the amplification and filtering circuit module is integrated in the phase-locked loop circuit module; an RF connector is provided on the partition between the RF circuit shielding cavities, the power divider circuit module and the phase-locked loop circuit module are connected through the RF connector, and an RF output socket is provided on an outer wall of the RF circuit shielding box corresponding to the phase-locked loop circuit module; a plurality of through-hole capacitor terminals are also provided on the outer wall of the RF circuit shielding box, and the power divider circuit module and the phase-locked loop circuit module are connected to the FPGA control circuit board through the through-hole capacitor terminals.

4. The low-spurious agile frequency source module according to claim 3, characterized in that: The RF circuit shielding box is provided with connecting ear plates at the corners at the bottom end of the RF circuit shielding cavity, the power divider circuit module and the phase-locked loop circuit module are respectively abutted on the connecting ear plates in the corresponding RF circuit shielding cavity, and connecting studs are connected to the connecting ear plates; the bottom of the connecting stud is provided with a threaded convex shaft, the threaded convex shaft is threadedly connected to the connecting ear plate, and the threaded convex shaft penetrates the corresponding power divider circuit module and phase-locked loop circuit module, and the shoulder of the connecting stud abuts on the upper end surface of the corresponding power divider circuit module and phase-locked loop circuit module; the top of the connecting stud is provided with a threaded blind hole along its axial direction, and the top of the RF circuit shielding box is provided with a cover plate, and the cover plate is provided with connecting hole 2 at the position corresponding to the connecting stud, the cover plate is fixed to the connecting stud by screws penetrating the connecting hole 2 and the threaded blind hole, and the bottom surface of the cover plate abuts against the top surface of the RF circuit shielding box.

5. The low-spurious agile frequency source module according to claim 1, characterized in that: The bottom of the radio frequency circuit shielding box body is a hollow structure, and a signal ground copper is provided on the FPGA control circuit board at a position corresponding to the radio frequency circuit shielding box body.

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