Zipper type signal shielding layout structure

Abstract

The utility model provides a zipper type signal shielding layout structure, which comprises a first metal wire and a second metal wire which are respectively grounded and positioned on the same metal layer, an analog signal wire positioned between the first metal wire and the second metal wire, and an upper metal layer connected above the first metal wire, the second metal wire and the analog signal wire, the silicon layer is connected below the first metal wire, the second metal wire and the analog signal wire, the through holes are formed between the upper metal layer and the first metal wire and between the upper metal layer and the second metal wire, and the contact holes are formed between the first metal wire and the silicon layer and between the second metal wire and the silicon layer. The zipper type signal shielding layout structure is formed by the upper metal layer, the silicon layer, the through hole, the contact hole, the first metal wire, the second metal wire and the analog signal wire, interference of the substrate sub on the signal wire is reduced, interference of the metal wire on the signal wire is also reduced, the circuit performance is improved, and the cost is reduced. And the performance of the actually produced chip is more consistent with that of the simulated chip.

Description

Technical Field

[0001] The utility model relates to the technical field of electrical components, and particularly relates to a zipper-type signal shielding layout structure. Background Art

[0002] Noise interference is a very common problem in integrated circuits. Most of the currently designed chips are mixed-signal chips. Due to various calculations, control logics, frequent switching, etc. in some digital modules, the area around the digital modules will become noisy. Especially for the CLOCK clock signal line, it may be jumping from the circuit startup to shutdown. At this time, if an analog module signal line happens to pass by, the analog signal will be greatly interfered, seriously affecting the circuit performance. Therefore, when arranging the layout and wiring, such modules and special signal lines should be separated as much as possible, and the farther the better. However, sometimes a very sensitive analog signal line needs to travel a relatively long distance in the layout and passes through many modules. A little noise interference may have a great impact on it. At this time, it is necessary to shield this signal line to protect this very sensitive analog signal.

[0003] The usual shielding of analog signal lines is to add metal lines of the same layer with the same width on both sides during the path that this signal line passes through, such as Figure 1 ., and connect these two metal lines to gnd. Although this shields the signal to a certain extent, it may still not be enough, and there are the following several disadvantages:

[0004] 1. This signal line may be interfered by the substrate sub (when passing by a module with frequent voltage jumps)

[0005] 2. This signal line may be interfered by the signals of the lower-layer metal and the upper-layer metal.

[0006] Therefore, a layout structure with good shielding effect is needed. Summary of the Invention

[0007] The utility model is to solve the problem of signal interference, and provides a zipper-type signal shielding layout structure. Through the upper metal layer above, the silicon layer below, through holes, contact holes, the first metal line, the second metal line, and the analog signal line form a zipper-type signal shielding layout structure, reducing the interference of the substrate sub on the signal line, and also reducing the interference of the metal line on the signal line, improving the circuit performance, and making the performance of the actually produced chip more consistent with the simulated performance.

[0008] The present utility model provides a zipper - type signal shielding layout structure, which includes a first metal wire and a second metal wire that are respectively grounded and located in the same metal layer, an analog signal wire located between the first metal wire and the second metal wire, an upper - layer metal layer connected above the first metal wire, the second metal wire, and the analog signal wire, a silicon layer connected below the first metal wire, the second metal wire, and the analog signal wire, vias provided between the upper - layer metal layer and the first metal wire and between the upper - layer metal layer and the second metal wire, and contact holes provided between the first metal wire and the silicon layer and between the second metal wire and the silicon layer.

[0009] In a preferred embodiment, the zipper - type signal shielding layout structure of the present utility model further includes a power supply VDD and an N - well surrounding the passing area of the first metal wire, the second metal wire, and the analog signal wire. The N - well is connected to the power supply VDD after surrounding the first metal wire, the second metal wire, and the analog signal wire.

[0010] In a preferred embodiment, the vias of the zipper - type signal shielding layout structure of the present utility model are arranged evenly.

[0011] In a preferred embodiment, the contact holes of the zipper - type signal shielding layout structure of the present utility model are arranged evenly.

[0012] In a preferred embodiment, the first metal wire, the second metal wire, and the analog signal wire are all located in the first metal layer, and the upper - layer metal layer is located in the second metal layer.

[0013] In a preferred embodiment, the widths of the first metal wire and the second metal wire are the same.

[0014] In a preferred embodiment, the distance between the first metal wire and the analog signal wire is the same as the distance between the second metal wire and the analog signal wire.

[0015] In a preferred embodiment, the widths of the upper - layer metal layer and the silicon layer are the same.

[0016] The present utility model reduces the interference of the substrate sub on the signal wire and also reduces the interference of the metal wire on the signal wire through the zipper - type signal shielding layout structure.

[0017] The present utility model has the following advantages:

[0018] The present utility model greatly reduces the influence of noise on the key sensitive analog signal wires, improves the circuit performance, and makes the performance of the actually produced chip more consistent with the simulated performance. Description of the Drawings

[0019] Figure 1 Signal shielding diagram for the prior art

[0020] Figure 2 Top view of a zipper - type signal shielding layout structure

[0021] Figure 3 Front - view sectional view of a zipper - type signal shielding layout structure

[0022] Reference numerals in the drawings:

[0023] 1. First metal line; 2. Second metal line; 3. Analog signal line; 4. Upper metal layer; 5. Silicon layer; 6. Through - hole; 7. Contact hole; 8. Power supply VDD; 9. N - well Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments.

[0025] Embodiment 1

[0026] As shown in Figure 2 、 Figure 3 , a zipper - type signal shielding layout structure. A and C are two MET1 (1, 2) with their potentials connected to GND, B is an analog signal line 3 which is the MET1 to be protected. In the area where the two lines A and C pass, the entire area covers POLY5 and MET2 (i.e., the upper metal layer 4). Thus, the three lines A, B, and C are MET1. Physically, the lower layer of them covers the entire POLY layer, and the upper layer covers the entire MET2 layer. Then, in the overlapping part of the two MET1 of A and C with POLY and MET2, a row of CONT7 and a row of VIA6 are added. In this way, the analog signal line is completely wrapped between POLY5 and MET2. CONT and VIA1 holes are drilled on both A and C, just like a zipper, enclosing the analog signal line, playing a very good shielding role. In order to reduce the interference of the substrate sub on the analog signal line B, the area where these three lines pass is surrounded by NWELL9 and then connected to VDD8. Because the NWELL used is deeper, it can very effectively prevent the jump of the substrate sub potential from interfering with the analog signal line B.

[0027] In this embodiment, the widths of the first metal line 1, the second metal line 2, and the analog signal line 3 are all 0.6 μm, and the spacing is also 0.6 μm. The contact hole 7 is a square hole with a size of 0.22 * 0.22 μm, and the through - hole 6 is a square hole with a size of 0.25 * 0.25 μm.

[0028] The above are only the preferred specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model, according to the technical solution and the inventive concept of the present utility model, makes equivalent substitutions or changes, and should be covered by the protection scope of the present utility model.

Claims

1. A zipper-type signal shielding layout structure, characterized in that: The invention comprises a first metal wire (1) and a second metal wire (2) which are respectively grounded and located in the same metal layer, an analog signal wire (3) located between the first metal wire (1) and the second metal wire (2), an upper metal layer (4) connected above the first metal wire (1), the second metal wire (2) and the analog signal wire (3), a silicon layer (5) connected below the first metal wire (1), the second metal wire (2) and the analog signal wire (3), a through hole (6) arranged between the upper metal layer (4) and the first metal wire (1), and between the upper metal layer (4) and the second metal wire (2), and a contact hole (7) arranged between the first metal wire (1) and the silicon layer (5), and between the second metal wire (2) and the silicon layer (5).

2. A zipper-type signal shielding layout structure according to claim 1, characterized in that: It also includes a power supply VDD (8) and an N-well (9) surrounding the area where the first metal line (1), the second metal line (2) and the analog signal line (3) pass through, and the N-well (9) surrounds the first metal line (1), the second metal line (2) and the analog signal line (3) and is connected to the power supply VDD (8).

3. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The through holes (6) are evenly arranged.

4. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The contact holes (7) are evenly arranged.

5. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The first metal line (1), the second metal line (2), and the analog signal line (3) are all located in a first metal layer, and the upper metal layer (4) is located in a second metal layer.

6. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The first metal line (1) and the second metal line (2) have the same width.

7. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The spacing between the first metal line (1) and the analog signal line (3) is the same as the spacing between the second metal line (2) and the analog signal line (3).

8. The zipper-type signal shielding layout structure according to claim 1, characterized in that: The upper metal layer (4) and the silicon layer (5) have the same width.

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