Optical device

Abstract

The utility model discloses an optical device. In an embodiment, an optical device is provided that includes an optical package having a first surface and a second surface opposite the first surface. The optical device includes a laser die package having a third surface and a fourth surface opposite the third surface. The first surface and the third surface are coplanar, and the second surface and the fourth surface are coplanar. The optical device includes a first silicon support attached to both the second surface and the fourth surface. The optical device also includes an interposer attached to both the first surface and the third surface. The interposer does not contain the silicon substrate.

Description

Technical Field

[0001] Embodiments of the present utility model relate to integrated circuit devices, and particularly to optical devices. Background Art

[0002] The transmission and processing of electronic signals are a kind of technology for signal transmission and processing. In recent years, the transmission and processing of optical signals have been used in more and more applications, especially in applications related to optical fibers for signal transmission.

[0003] The transmission and processing of optical signals are usually combined with the transmission and processing of electronic signals to provide full-fledged applications. For example, optical fibers can be used for long-distance signal transmission, while electronic signals can be used for short-distance signal transmission and processing and control. Therefore, devices integrating long-distance optical components and short-distance electronic components are formed for the conversion between optical signals and electronic signals and the processing of optical signals and electronic signals. Thus, the package can include an optical (photonic) die containing an optical device and an electronic die containing an electronic device. Summary of the Utility Model

[0004] Embodiments of the present utility model provide an optical device, comprising: an optical package having a first surface and a second surface opposite the first surface; a laser die package having a third surface and a fourth surface opposite the third surface, wherein the first surface is aligned with the third surface, and the second surface is aligned with the fourth surface; a first silicon support attached to both the second surface and the fourth surface; and an interposer attached to both the first surface and the third surface, wherein the interposer does not contain a silicon substrate.

[0005] In some embodiments, the first surface and the third surface are coplanar, and the second surface and the fourth surface are coplanar.

[0006] In some embodiments, the optical device further includes: a first insulating material encapsulating both the optical package and the laser die package, wherein the first insulating material spans from the interposer to the first silicon support.

[0007] In some embodiments, the laser die package includes: a laser diode; and

[0008] a second silicon support above the laser diode and opposite the interposer, wherein the second silicon support has the fourth surface.

[0009] In some embodiments, the optical package includes: an optical interposer, attached to the interposer; an electronic integrated circuit (EIC), bonded to the optical interposer and opposite to the interposer; a third silicon support above the electronic integrated circuit, wherein the third silicon support has the fourth surface; and a second insulating material encapsulating the electronic integrated circuit, wherein the second insulating material spans from the optical interposer to the third silicon support. In some embodiments, the optical package includes an electronic integrated circuit, wherein the electronic integrated circuit has the same width as the optical package.

[0010] In some embodiments, the first silicon support has a thickness ranging from 700 millimeters to 1500 millimeters.

[0011] In some embodiments, the interposer has a thickness ranging from 10 micrometers to 150 micrometers. In some embodiments, the optical device further includes: a plurality of microbumps disposed on the interposer.

[0012] In some embodiments, the first silicon support includes a lens.

[0013] At least one embodiment of the present utility model has the following advantages or technical effects:

[0014] In the above embodiments, the use of the second silicon support allows for the removal of bulk silicon from the interposer, thereby improving the proximity to the electrical connection of the optical device and allowing the laser die to pass through the interposer from the package substrate. By supporting the optical package from above with the second silicon support, the interposer can be thinned without the need for long via metal routing through the interposer, thus greatly reducing the electrical losses and the impact of parasitic capacitance caused by through-silicon vias passing through bulk silicon in a typical interposer. In addition, these reduced negative impacts and the improved proximity of the electronic components to the functional devices facilitate improved high-speed operation and higher data transfer rates. Similarly, by eliminating the need for through-silicon vias through the interposer, the risk of damage caused by forming these vias into the interposer is eliminated. In addition, the use of the support allows for the individual optimization of the optical device and the laser die before integration onto the interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments of the present utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present utility model.

[0016] Figures 1 to 9 According to some embodiments, the formation of a first optical device including an electronic integrated circuit singulated above a photonic integrated circuit is illustrated.

[0017] Figure 10 According to some embodiments, the formation of a second optical device including an electronic integrated circuit and a photonic integrated circuit that are wafer-scale bonded and singulated to form individual optical devices is illustrated.

[0018] Figure 11 According to some embodiments, the formation of a first redistribution structure of an optical package interposer is illustrated.

[0019] Figures 12 to 14 According to some embodiments, the formation of a first optical package including a top support structure and a thinned optical package interposer is illustrated.

[0020] Figure 15 According to some embodiments, an example of a first optical package including a top support structure and a thinned optical package interposer is illustrated, which is an optical device for forming the first optical package using a wafer forming process.

[0021] Figure 16 According to some embodiments, an example of a first optical package including a top support structure and a thinned optical package interposer is illustrated, which has an additional support structure above the optical device within the first optical package.

[0022] Wherein the reference numerals are described as follows:

[0023] 100: Optical interposer

[0024] 101: First substrate

[0025] 103: First insulator layer

[0026] 105: Material layer

[0027] 201: First active layer

[0028] 203: First optical element

[0029] 301: Semiconductor material

[0030] 401: Second insulating layer

[0031] 501: First metallization layer

[0032] 503: Second optical element

[0033] 505: First bonding layer

[0034] 507: First bonding pad

[0035] 509: First dielectric material

[0036] 511: Third optical element

[0037] 601: First semiconductor device

[0038] 603: First semiconductor substrate

[0039] 605: First active device layer

[0040] 607: First interconnect structure

[0041] 609: Second bonding layer

[0042] 611: Second bonding pad

[0043] 701: First gap-fill material

[0044] 750: First planarization process

[0045] 800: Second active layer

[0046] 801: Second substrate

[0047] 803: Fourth optical element

[0048] 900: Third bonding layer

[0049] 901: Third bonding pad

[0050] 903: Through-device via

[0051] 950: First optical device

[0052] 1001: Second semiconductor device

[0053] 1025: Singulation process

[0054] 1050: Second optical device

[0055] 1100: First redistribution structure

[0056] 1101: Third substrate

[0057] 1125: Third metallization layer

[0058] 1150: Fourth bonding layer

[0059] 1151: Fourth bonding pad

[0060] 1175: Fifth optical element

[0061] 1200: Laser die

[0062] 1201: Laser diode

[0063] 1203: Fifth bonding pad

[0064] 1205: First support substrate

[0065] 1250: Second gap filling material

[0066] 1275: Second planarization process

[0067] 1300: Second support substrate

[0068] 1350: Third planarization process

[0069] 1400: Second redistribution structure

[0070] 1401: Fourth metallization layer

[0071] 1403: First under-bump metallization layer

[0072] 1405: First external connector

[0073] 1425: First interposer

[0074] 1450: Package substrate

[0075] 1451: Second external connector

[0076] 1475: Coupling lens

[0077] 1477: Optical fiber

[0078] 1479: Optical adhesive

[0079] 1501: Underfill material

[0080] TH1: First thickness

[0081] TH2: Second thickness. Detailed implementation manners

[0082] Numerous embodiments or examples are provided below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is described that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, or it may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed.

[0083] Furthermore, spatially relative terms may be used, such as "beneath", "below", "lower", "above", "upper", etc. These are used to facilitate the description of the relationship between one (or some) components or features and another (or some) components or features in the drawings. Spatially relative terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

[0084] The present disclosure will now discuss certain embodiments in which at least one laser die and an optical engine are bonded to a thinned interposer and supported on opposite sides by a silicon support structure. The silicon support structure has multiple functions, including allowing the removal of silicon from a typical interposer structure used in a COUPE device. However, the embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the embodiments beyond the precise descriptions discussed. On the contrary, the discussed embodiments can be incorporated into various different embodiments, and all of these embodiments are intended to be fully included within the scope of the embodiments of the present disclosure.

[0085] Now refer to Figure 1 , according to some embodiments, an initial structure of an optical interposer 100 (see Figure 5 ) is illustrated. In the Figure 1 specific embodiment illustrated, the optical interposer 100 is a photonic integrated circuit (PIC), and at this stage includes a first substrate 101, a first insulator layer 103, and a first optical element 203 (not separately illustrated in Figure 1 but see below Figure 2The material layer 105 of the first active layer 201 (to be further illustrated and discussed). In an embodiment, at the beginning of the manufacturing process of the optical mediator 100, the first substrate 101, the first insulator layer 103, and the material layer 105 of the first active layer 201 for the first optical element 203 can jointly form part of a silicon-on-insulator (SOI) substrate. First, referring to the first substrate 101, the first substrate 101 can be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that allows for structural support of the overlying device.

[0086] The first insulator layer 103 can be a dielectric layer that separates the first substrate 101 from the overlying first active layer 201, and in some embodiments, as part of the cladding material, it surrounds the first optical element 203 (to be further discussed below) manufactured subsequently. In an embodiment, the first insulator layer 103 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination of the above, or the like, and is formed using methods such as implantation (e.g., to form a buried oxide (BOX)), or can also be deposited onto the first substrate 101 using deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a combination of the above, or similar deposition methods. However, any suitable material and manufacturing method can also be used.

[0087] The material layer 105 for the first active layer 201 is initially (before patterning) a conformal layer of the material for the first active layer 201 that is to be used to start fabricating the first optical element 203. In an embodiment, the material layer 105 for the first active layer 201 can be a translucent material that can be used as the core material for the desired first optical element 203, such as a semiconductor material, for example, silicon, germanium, silicon-germanium, a combination of the foregoing, or the like, while in other embodiments, the material layer 105 for the first active layer 201 can be a dielectric material such as silicon nitride or the like, although in other embodiments, the material layer 105 for the first active layer 201 can be a III-V material, a lithium niobate material, or a polymer. In embodiments where the material layer 105 for the first active layer 201 is deposited, methods such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the foregoing, or similar methods can be used to deposit the material layer 105 for the first active layer 201. In other embodiments where an implantation method is used to form the first insulating layer 103, the material layer 105 for the first active layer 201 can initially be part of the first substrate 101 before the implantation process for forming the first insulating layer 103 is performed. However, any suitable material and fabrication method can be utilized to form the material layer 105 for the first active layer 201.

[0088] Figure 2 Illustrated is that once the material layer 105 for the first active layer 201 is ready, the material layer 105 for the first active layer 201 is used to fabricate the first active layer 201 for the first optical element 203. In an embodiment, the first active layer 201 of the first optical element 203 can include, for example, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers, which are narrow waveguides having a width in the range of about 1 nm to about 200 nm), directional couplers, optical modulators (e.g., Mach-Zehnder silicon-photonic switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexors, demultiplexors, optoelectronic converters (e.g., PN junctions), electro-optic converters, lasers, a combination of the foregoing, or similar elements. However, any suitable first optical element 203 can also be used.

[0089] To form the first active layer 201 of the first optical element 203 from an initial material, a material layer 105 for the first active layer 201 can be patterned into the desired shape of the first active layer 201 of the first optical element 203. In an embodiment, the material layer 105 for the first active layer 201 can be patterned using, for example, one or more optical lithography masks and an etching process. However, any suitable method can also be utilized to pattern the material layer 105 for the first active layer 201. For some first optical elements 203, such as waveguides or edge couplers, the patterning process can be all or at least most of the manufacturing process for forming these first optical elements 203.

[0090] Figure 3 Illustrated for those elements that utilize further manufacturing processes, such as a Mach-Zehnder silicon-photonic switch that utilizes a resistive heating element, additional processes can be performed before or after the patterning of the material layer for the first active layer 201. For example, an implantation process, additional depositions for different materials (e.g., a resistive heating element, III-V materials for a converter), and patterning processes, combinations of all of the above processes, or similar processes can be utilized to aid in the further manufacture of various desired first optical elements 203. In a particular embodiment, and as Figure 3 specifically illustrated, in some embodiments, epitaxial deposition of a semiconductor material 301, such as germanium, can be performed on the patterned portion of the material layer 105 of the first active layer 201 (e.g., for electro / optical signal modulation and conversion). In such an embodiment, the semiconductor material 301 can be grown epitaxially to aid in the manufacture of, for example, a photodiode for an optoelectronic converter. All of these manufacturing processes and all suitable first optical elements 203 can be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments of the present disclosure.

[0091] Figure 4Illustrated is that once the first active layer 201 of each first optical element 203 is formed, a second insulating layer 401 can be deposited to cover the first optical element 203 and provide additional cladding material. In an embodiment, the second insulator layer 401 can be a dielectric layer that separates the respective elements of the first active layer 201 from each other and from the covered structure, and can additionally serve as another part of the cladding material around the first optical element 203. In an embodiment, the second insulator layer 401 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination of the foregoing, or the like, and is formed using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the foregoing, or a similar deposition method. Once the material of the second insulating layer 401 has been deposited, a process such as chemical mechanical polishing (CMP) can be used to planarize the material so as to planarize the top surface of the second insulating layer 401 (in an embodiment the second insulating layer 401 is intended to completely cover the first optical element 203) or to planarize the second insulating layer 401 with the top surface of the first optical element 203. However, any suitable material and manufacturing method can also be used.

[0092] Figure 5 Illustrated is that once the first active layer 201 of the first optical element 203 has been fabricated and the second insulating layer 401 has been formed, a first metallization layer 501 is formed to electrically connect the first active layer 201 of the first optical element 203 to a control circuit, to the first active layers 201 to each other, and to subsequently attached devices. In an embodiment, the first metallization layer 501 is formed of alternating layers of a dielectric material and a conductive material, and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In a particular embodiment, there can be multiple metallization layers for interconnecting the respective first optical elements 203, but the exact number of the first metallization layer 501 depends on the design of the optical intermediary 100.

[0093] In addition, during the fabrication of the first metallization layer 501, one or more second optical elements 503 can be formed as part of the first metallization layer 501. In some embodiments, the second optical elements 503 of the first metallization layer 501 can include elements such as couplers for connecting to external signals (e.g., edge couplers, grating couplers, etc.), optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (e.g., Mach-Zehnder silicon-photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, optoelectronic converters (e.g., PN junctions), electro-optic converters, lasers, a combination of the foregoing, or similar elements. However, any suitable optical element can also be used for the one or more second optical elements 503.

[0094] In an embodiment, one or more second optical elements 503 may be formed by first depositing a material for the one or more second optical elements 503. In an embodiment, the material for the one or more second optical elements 503 may be a dielectric material such as silicon nitride, silicon oxide, a combination of the foregoing, or the like, or may be a semiconductor material such as silicon, and may be deposited using deposition methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the foregoing, or similar deposition methods. However, any suitable material and any suitable deposition method may be utilized.

[0095] Once the material for the one or more second optical elements 503 has been deposited or otherwise formed, this material may be patterned into the desired shape of the one or more second optical elements 503. In an embodiment, the material of the one or more second optical elements 503 may be patterned using, for example, one or more optical lithography masks and an etching process. However, any suitable method may also be utilized to pattern the material for the one or more second optical elements 503.

[0096] For some of the one or more second optical elements 503, such as waveguides or edge couplers, the patterning process may be all or at least most of the manufacturing process for forming these elements. In addition, for those elements that utilize further manufacturing processes, such as Mach-Zehnder silicon-photonic switches that utilize resistive heating elements, additional processes may be performed before or after the patterning of the material for the one or more second optical elements 503. For example, implantation processes, additional depositions for different materials and patterning processes, combinations of all the foregoing processes, or similar processes may be used to assist in further manufacturing the various desired one or more second optical elements 503. All of these manufacturing processes and all suitable one or more second optical elements 503 may be fabricated, and all of these combinations are fully intended to be included within the scope of the embodiments of the present disclosure.

[0097] Once one or more second optical elements 503 of the first metallization layer 501 have been fabricated, a first bonding layer 505 is formed over the first metallization layer 501. In an embodiment, the first bonding layer 505 can be used for dielectric-to-dielectric and metal-to-metal bonding. According to some embodiments, the first bonding layer 505 is formed of a first dielectric material 509 such as silicon oxide, silicon nitride, or the like. Any suitable method can be used to deposit the first dielectric material 509, such as chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or similar processes. However, any suitable materials and deposition processes can also be utilized.

[0098] Once the first dielectric material 509 has been formed, a first opening is formed in the first dielectric material 509 to expose the conductive portion of the underlying film layer, in preparation for forming first bonding pads 507 within the first bonding layer 505. Once the first opening has been formed within the first dielectric material 509, the first opening can be filled with a seed layer and a plated metal to form the first bonding pads 507 within the first dielectric material 509. The seed layer can be deposited in a blanket fashion over the top surface of the first dielectric material 509, the exposed conductive portion of the underlying film layer, and the sidewalls of the opening and the second opening. The seed layer can comprise a copper layer. The seed layer can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or similar processes, depending on the desired material. The plated metal can be deposited over the seed layer by an electroplating process such as electroplating or electroless plating. The plated metal can comprise copper, a copper alloy, or the like. The plated metal can be the filling material. Prior to forming the seed layer, a barrier layer (not shown separately) can be deposited in a blanket fashion over the top surface of the first dielectric material 509 and the sidewalls of the opening and the second opening. The barrier layer can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0099] After filling the first opening, a planarization process such as CMP is performed to remove the excess portions of the seed layer and the plated metal and to form the first bonding pads 507 within the first bonding layer 505. In some embodiments, via holes for bonding pads (not shown separately) can also be used to connect the first bonding pads 507 to the underlying conductive portion and to connect the first bonding pads 507 to the first metallization layer 501 through the underlying conductive portion.

[0100] In addition, the first bonding layer 505 may also include one or more third optical elements 511 incorporated within the first bonding layer 505. In such an embodiment, prior to depositing the first dielectric material 509, the one or more third optical elements 511 may be fabricated using a method and materials similar to those of the one or more second optical elements 503 (as described above), such as waveguides and other structures formed at least in part by deposition and patterning processes. However, any suitable structures, materials, and any suitable fabrication methods may be utilized.

[0101] Figure 6 Illustrated is that once the optical interposer 100 is formed, the first semiconductor device 601 may also be bonded to the optical interposer 100. In some embodiments, the first semiconductor device 601 is an electronic integrated circuit (EIC, e.g., a device without optical devices) and may have a first semiconductor substrate 603, a first active device layer 605, an overlying first interconnect structure 607, a second bonding layer 609, and associated second bonding pads 611. In an embodiment, the first semiconductor substrate 603 may be similar to the first substrate 101 (e.g., a semiconductor material such as silicon or silicon germanium), the first active elements 605 may be transistors, capacitors, resistors, and the like formed above the first semiconductor substrate 603, the first interconnect structure 607 may be similar to the first metallization layer 501 (without optical elements), the second bonding layer 609 may be similar to the first bonding layer 505, and the second bonding pads 611 may be similar to the first bonding pads 507. However, any suitable devices may also be utilized.

[0102] In an embodiment, the first semiconductor device 601 may be configured to work with the optical interposer 100 to achieve the desired functions. In some embodiments, the first semiconductor device 601 may be a high bandwidth memory (HBM) module, a processing unit (xPU), a logic die, a three-dimensional integrated circuit (3DIC) die, a central processing unit (CPU), a graphic processing unit (GPU), a system-on-a-chip (SoC) die, a micro-electro-mechanical system (MEMS) die, a combination of the foregoing, or the like. Any suitable device having any suitable function may be used, and all such devices are fully intended to be included within the scope of the embodiments of the present disclosure.

[0103] Once the first semiconductor device 601 is ready, the first semiconductor device 601 may be bonded to the optical interposer 100. In an embodiment, the first semiconductor device 601 may be bonded to the optical interposer 100 using, for example, a dielectric-to-dielectric and metal-to-metal bonding process. In such an embodiment, the first semiconductor device 601 is bonded to the first bonding layer 505 of the optical interposer 100 by both bonding the first bonding pad 507 to the second bonding pad 611 and bonding the dielectric within the first bonding layer 505 to the dielectric within the second bonding layer 609. In this embodiment, as an example, the top surfaces of the first semiconductor device 601 and the optical interposer 100 may be first treated, for example, by dry processing, wet processing, plasma processing, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, or a combination of the foregoing. However, any suitable activation process may be used.

[0104] After the activation process, the first semiconductor device 601 and the optical mediator 100 can be cleaned using, for example, chemical rinsing, and then the first semiconductor device 601 is aligned and placed in physical contact with the optical mediator 100. Then, heat treatment and contact pressure are applied to the first semiconductor device 601 and the optical mediator 100 to bond the first semiconductor device 601 and the optical mediator 100. For example, a pressure of about 200 kPa or less can be applied to the first semiconductor device 601 and the optical mediator 100, and a temperature in the range of about 25°C to about 250°C can be applied to weld the first semiconductor device 601 and the optical mediator 100. Then, the first semiconductor device 601 and the optical mediator 100 can be subjected to a temperature equal to or higher than the eutectic point of the material of the first bonding pad 507, such as in the range of about 150°C to about 650°C, to weld the metal bonding pads. In this way, the welding of the first semiconductor device 601 and the optical mediator 100 forms a bonding device. In some embodiments, the bonded die is baked, annealed, pressed, or otherwise processed to strengthen or complete the bond.

[0105] In addition, although dielectric-to-dielectric and metal-to-metal bonding processes have been described above, this is for illustrative purposes only and is not intended to be limiting. In still other embodiments, the optical mediator 100 can be bonded to the first semiconductor device 601 by a metal-to-metal bonding or another bonding process. For example, the first semiconductor device 601 and the optical mediator 100 can be bonded by a metal-to-metal bonding achieved by fusing conductive elements. Any suitable bonding process can be used, and all such methods are fully intended to be included within the scope of the embodiments of the present disclosure.

[0106] Figure 7 It is shown that once the first semiconductor device 601 has been attached to the optical mediator 100, a first gap filling material 701 (also referred to as an insulating material) can be deposited to fill and overfill the space around the first semiconductor device 601 and provide additional support. In an embodiment, the first gap filling material 701 can be a material such as silicon oxide, silicon nitride, silicon oxynitride, a combination of the above, or a similar material. However, any suitable material and deposition method can also be utilized.

[0107] Once the first gap-fill material 701 has been deposited, the first gap-fill material 701 can be planarized by a first planarization process 750 to expose the first semiconductor device 601. Once planarized, the top surfaces of the first semiconductor device 601 and the first gap-fill material 701 are substantially coplanar within process variations after the first planarization process 750. In an embodiment, the first planarization process 750 can be a CMP process, a grinding process, or a similar process. However, any suitable planarization process can also be utilized.

[0108] Figure 8 Illustrated is that once the top surfaces of the first semiconductor device 601 and the first gap-fill material 701 have been planarized, the second substrate 801 can be attached to the top surfaces of the first semiconductor device 601 and the first substrate 101, and the first insulating layer 103 can be removed. In an embodiment, the second substrate 801 supports the removed first substrate 101 and the first insulating layer 103, and supports subsequent structures formed above the currently exposed first active layer 201. In an embodiment, the second substrate 801 can comprise silicon, such as bulk silicon, and can be attached using a bonding process or a separate adhesive. Additionally, a planarization process (e.g., CMP) or one or more etching processes can be used to remove the first substrate 101 and the first insulating layer 103. Any suitable method can also be used to attach the second substrate 801 and remove the first substrate 101 and the first insulating layer 103.

[0109] Figure 8 Further illustrated is that once the first substrate 101 and the first insulating layer 103 have been removed, a second active layer 800 having a fourth optical element 803 can be formed above the first active layer 201. In an embodiment, the second active layer 800 can be formed in an approximate manner and from similar materials as those discussed above with respect to the second optical element 503 of the upper first metallization layer 501. In an embodiment, the fourth optical element 803 can be formed in an approximate manner and from approximate materials as those discussed above with respect to the second optical element 503. However, any suitable method or materials can also be used to form the second active layer 800 and the fourth optical element 803.

[0110] Figure 9Once the second active layer 800 has been formed, a third bonding layer 900 having a third bonding pad 901 can be formed, and first through device vias (TDVs) 903 can be formed (the resulting structure can be referred to as the first optical device 950). In an embodiment, the first TDVs 903 extend through the second active layer 800 and the first active layer 201 to provide a fast path for power, data, and ground through the optical interposer 100. In an embodiment, the first TDVs 903 can be formed by first forming openings of the through device vias in the optical interposer 100. The openings of the through device vias can be formed by applying and developing a suitable photoresist (not shown) and removing multiple portions exposed in the second active layer 800 and the optical interposer 100.

[0111] Once the openings of the through device vias have been formed in the optical interposer 100, the openings of the through device vias can be lined with a liner. The liner can be, for example, an oxide or silicon nitride formed from tetraethylorthosilicate (TEOS), but any suitable dielectric material can alternatively be used. The liner can be formed using a plasma enhanced chemical vapor deposition (PECVD) process, but other suitable processes, such as physical vapor deposition or thermal processes, can alternatively be used.

[0112] Once the liner has been formed along the sidewalls and bottom of the openings of the through device vias, a barrier layer (also not shown separately) can be formed, and the remaining portion of the openings of the through device vias can be filled with a first conductive material. The first conductive material can include copper, but other suitable materials, such as aluminum, alloys, doped polysilicon, combinations of the above, and the like, can alternatively be used. The first conductive material can be formed by electroplating copper onto a seed layer (not shown), filling, and overfilling the openings of the through device vias. Once the openings of the through device vias have been filled, the excess liner, barrier layer, seed layer, and first conductive material outside the openings of the through device vias can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can also be used.

[0113] Optionally, in some embodiments, once the first TDVs 903 have been formed, a second metallization layer (not shown separately in Figure 9In an embodiment, the second metallization layer may be formed in a manner similar to that discussed above for the first metallization layer 501, such as an alternating layer of dielectric and conductive materials formed using a damascene process, a dual damascene process, or a similar process. In other embodiments, the second metallization layer may be formed using an electroplating process, where a conductive material is shaped and then covered with a dielectric material. However, any suitable structure and manufacturing method may also be utilized.

[0114] Figure 9 Further illustrated is the formation of a third bonding layer 900 having a third bonding pad 901. In an embodiment, the third bonding layer 900 may be formed in a manner similar to that discussed above for the first bonding layer 505 and from similar materials. In an embodiment, the third bonding pad 901 may be formed in a manner similar to that discussed above for the first bonding pad 507, the second bonding pad 611, etc. and from similar materials. However, the formation of the third bonding layer 900 and the third bonding pad 901 may also utilize any suitable method or material. Additionally, in an embodiment, the third bonding pad 901 may be electrically connected to the first TDVs 903 and the second metallization layer to provide an electrical connection to and from the first optical device 950.

[0115] Figure 10 Illustrated is an embodiment in which the optical element is formed from a wafer. In this embodiment, one or more second semiconductor devices 1001 are formed in a manner similar to the first semiconductor device 601 and from similar materials, and are formed as part of a first wafer (only a portion thereof is shown), and the optical interposer 100 is formed in a manner similar to that discussed above and from similar materials, and is formed as part of a second wafer (not shown separately). In this embodiment, the first wafer may be bonded to the second wafer in a manner similar to that discussed above for bonding the first bonding layer 505 to the second bonding layer 609. After bonding the first wafer to the second wafer, a singulation process 1025 may be performed to form individual optical devices (which may be referred to as second optical devices 1050) from the bonded wafers. In an embodiment, the singulation process 1025 may be a sawing process. However, any suitable singulation process may also be utilized. After the singulation process 1025, the sidewalls of the second optical device 1050 may be substantially coplanar within process variations. In this embodiment, the second active layer 800, the third bonding layer 900, and the first TDVs 903 may be formed from the wafer or formed after the singulation process 1025.

[0116] Figure 11Illustrates the formation of a first redistribution structure 1100, to which various optical devices (e.g., a first optical device 950, a second optical device 1050, etc., see respectively Figure 12 and Figure 15 ) can be subsequently attached, as well as to a laser die 1200 (see Figure 12 ). In an embodiment, the first redistribution structure 1100 can be formed over a third substrate 1101, which can provide support for subsequent processing steps. In an embodiment, the first redistribution structure 1100 can include a third metallization layer 1125 and a fourth bonding layer 1150. The third metallization layer 1125 can be formed in an approximate manner and from approximate materials as discussed above with respect to the first metallization layer 501. Additionally, the fourth bonding layer 1150 can be formed in an approximate manner and from approximate materials as discussed above with respect to the first bonding layer 505. Further, in an embodiment, the fourth bonding layer 1150 also includes a fourth bonding pad 1151, which can be formed in an approximate manner and from approximate materials as discussed above with respect to the first bonding pad 507. In an embodiment, the first redistribution structure 1100 can also include a fifth optical element 1175, which can be formed in an approximate manner and from approximate materials as discussed above with respect to the second optical element 503.

[0117] In an embodiment, the first redistribution structure 1100 is formed to electrically connect optical devices (e.g., a first optical device 950, a second optical device 1050) to the laser die 1200, to a control circuit, to the first redistribution structure 1100 to each other, and to subsequently attached structures. Additionally, in an embodiment, the fifth optical element 1175 can be used for optical connection between the optical devices and the laser die 1200, or can provide other signal-related functions.

[0118] Figure 12 Illustrates that after the first redistribution structure 1100 is formed, the first optical device 950 and the laser die 1200 can be attached to the first redistribution structure 1100. In an embodiment, the laser die 1200 is bonded to the first redistribution structure 1100 to provide power to the first optical device 950. In some embodiments, the laser die 1200 can include a light generating structure, such as one or more laser diodes 1201 surrounded by a dielectric and / or a cladding material above a first support substrate 1205. In an embodiment, the first support substrate 1205 can include a silicon material, such as bulk silicon. In a particular embodiment, the laser diode can be a Fabry - Perot diode and can be based on III - V materials, II - VI materials, or any other suitable material set.

[0119] In certain embodiments, one or more laser diodes 1201 may include a first contact, a first buffer layer, a first active diode layer including a plurality of quantum wells (MQWs), a second buffer layer, and a second contact (only some of the components are shown for clarity, such as Figure 12 as shown), to generate the desired light. Additionally, the generated light may be output from the laser die 1200 through, for example, the first contact and an associated waveguide. However, any suitable structure may be utilized to form one or more laser diodes 1201 and generate the desired light.

[0120] Furthermore, the laser die 1200 may also include a fifth bonding pad 1203. In an embodiment, the fifth bonding pad 1203 may be similar to the first bonding pad 507. In an embodiment, the fifth bonding pad 1203 may be a cushion layer for the contact. However, any suitable material and connection shape may also be used for the fifth bonding pad 1203.

[0121] Once the laser die 1200 has been formed and / or otherwise received, the laser die 1200 may be bonded to the first redistribution structure 1100. In an embodiment, the laser die 1200 may be bonded to the first redistribution structure 1100 using dielectric-to-dielectric and metal-to-metal bonding, similar to the method described above with respect to the first bonding layer 505 and the second bonding layer 609. However, any suitable bonding process may also be utilized.

[0122] In an embodiment, the desired light is generated by the laser die 1200 and coupled into the first redistribution structure 1100. The first redistribution structure 1100 receives the light and routes the light through the fifth optical element 1175 to the first optical device 950.

[0123] Figure 12 Also shown is attaching the first optical device 950 to the first redistribution structure 1100. In an embodiment, the first optical device 950 may be attached to the first redistribution structure 1100 before attaching the laser die 1200 to the first redistribution structure 1100, simultaneously with attaching the laser die 1200 to the first redistribution structure 1100, or after attaching the laser die 1200 to the first redistribution structure 1100. In an embodiment, the first optical device 950 is attached to the first redistribution structure 1100 by bonding a third bonding layer 900 to a fourth bonding layer 1150 in a manner similar to that discussed above with respect to bonding the first bonding layer 505 to the second bonding layer 609. However, any suitable bonding or attaching method may also be used to attach the first optical device 950 to the first redistribution structure 1100.

[0124] After attaching the laser die 1200 and the first optical device 950 to the first redistribution structure 1100, a second gap-fill material 1250 can be deposited to fill and overfill the space around the first optical device 950 and the laser die 1200 and to provide additional support. In an embodiment, the second gap-fill material 1250 can be deposited and formed in a manner similar to and from a material similar to the first gap-fill material 701. However, any suitable deposition material and method can be utilized to deposit the second gap-fill material 1250. After depositing the second gap-fill material 1250, a second planarization process 1275 can be performed to remove the excess portion of the second gap-fill material 1250. In an embodiment, the second substrate 801 can be removed by the second planarization process 1275. In this embodiment, the top surfaces of the first semiconductor device 601, the first gap-fill material 701, the second gap-fill material 1250, and the first support substrate 1205 are substantially coplanar within process variations after the second planarization process 1275, where these top surfaces can be collectively referred to as the first planar top surface. In an embodiment, the second planarization process 1275 can be a CMP process, a grinding process, or a similar process. However, any suitable planarization process can be utilized.

[0125] Figure 13 Illustrated is that after the second planarization process 1275, a second support substrate 1300 can be attached to the first planar top surface. In an embodiment, the second support substrate 1300 can comprise silicon, such as bulk silicon. Additionally, in an embodiment, the second support substrate 1300 can be attached to the first planar top surface by a process such as a direct bonding process (e.g., a bonding process between the silicon of the first support substrate 1205, the semiconductor material of the first semiconductor substrate 603, and the second support substrate 1300), by a fusion bonding process (e.g., a fusion bonding process between the silicon of the second support substrate 1300 and the oxide or nitride of the first gap-fill material 701 and the second gap-fill material 1250), a similar process, or a combination of the above. In an embodiment, the first bonding process can comprise the step of activating the bonding surfaces of the first planar top surface and the second support substrate 1300. The first planar top surface can be activated by, for example, a dry process, a wet process, a plasma process, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, or a combination of the above. However, any suitable activation process can be utilized.

[0126] After the activation process, the first flat top surface and the second support substrate 1300 can be cleaned using, for example, chemical rinsing, and then the second support substrate 1300 is aligned and placed in physical contact with the first flat top surface. Then, heat treatment and contact pressure are applied to the first flat top surface and the second support substrate 1300 to bond the second support substrate 1300 to the laser die 1200 and the first optical device 950. For example, a pressure of about 200 kPa or less can be applied to the second support substrate 1300 and the first flat top surface, and a temperature in the range of about 25 °C to about 250 °C can be applied to weld the second support substrate 1300 to the first flat top surface. In this way, the second support substrate 1300, the laser die 1200, and the first optical device 950 form a bonding device. In some embodiments, the bonded structure is baked, annealed, pressed, or otherwise treated to strengthen or complete the bond.

[0127] In an embodiment, the second support substrate 1300 can be formed to a first thickness TH1, where the first thickness TH1 ranges from 700 millimeters (mm) to 1500 mm. If the thickness of the second support substrate 1300 is less than the first thickness TH1, the second support substrate 1300 may be too thin to be properly bonded for mechanical processing in subsequent processes and may also be too thin to properly support the long-term stability of the final optical package structure. If the thickness of the second support substrate 1300 is greater than the first thickness TH1, the second support substrate 1300 may be too thick to be properly bonded for mechanical processing in subsequent processes and may also be too thick for the function required for light transmission through the second support substrate 1300 in the final optical package structure.

[0128] Figure 13 Further illustrated is that after the attachment of the second support substrate 1300, the third substrate 1101 can be removed from the first redistribution structure 1100. In an embodiment, the third substrate 1101 can be removed by a third planarization process 1350. In an embodiment, the third planarization process 1350 can be a CMP process, a grinding process, or a similar process, or a combination of the above. In one embodiment, a first portion of the third substrate 1101 (e.g., a bulk portion of the third substrate 1101 material) is removed by a grinding process, and a second portion of the third substrate 1101 (e.g., a more controlled removal) is removed by a CMP process. However, any suitable planarization process can also be utilized. In an embodiment, after the third planarization process 1350, the conductive material of the first redistribution structure 1100 is exposed.

[0129] Figure 14It is shown that after removing the third substrate 1101, a second redistribution structure 1400 can be formed over the exposed first redistribution structure 1100 and electrically coupled to the first redistribution structure 1100 with a conductive material. In an embodiment, the second redistribution structure 1400 includes a fourth metallization layer 1401 having first under-bump metallizations (UBMs) 1403. In an embodiment, a first external connector 1405 can be formed on the second redistribution structure 1400 over the first UBMs 1403.

[0130] In an embodiment, the fourth metallization layer 1401 can be formed in a manner similar to and from materials similar to the first metallization layer 501. In an embodiment, the first external connector 1405 can be placed on the first UBMs 1403 and electrically connected to the first redistribution structure 1100, and can be, for example, a ball grid array (BGA) that includes a eutectic material such as solder, but any suitable material can also be used. In an embodiment where the first external connector 1405 is a solder bump or micro-bumps, the first external connector 1405 can be formed using a ball drop method (such as a direct ball drop process). In another embodiment, the solder bump or micro-bumps can be formed by first forming a tin layer by any suitable method, such as evaporation, electroplating, printing, solder transfer, and then performing reflow to shape the material into the desired bump shape. Once the first external connector 1405 is formed, tests can be performed to ensure that the structure is suitable for further processing. The combined structure of the first redistribution structure 1100 and the second redistribution structure 1400 can be referred to as a first interposer 1425. In an embodiment, the first interposer 1425 can be free of bulk silicon (e.g., without a silicon substrate) and can additionally be free of through silicon vias (e.g., without vias extending through bulk silicon).

[0131] In an embodiment, the first interposer 1425 can be formed to a second thickness TH2, where the second thickness TH2 ranges from 10 micrometers (μm) to 150 μm. If the thickness of the first interposer 1425 is less than the second thickness TH2, the first interposer 1425 may be too thin to properly support the structures bonded to the first interposer 1425 and may not have sufficient structural reliability. If the thickness of the first interposer 1425 is greater than the second thickness TH2, the first interposer 1425 may experience inappropriate electrical losses, inappropriate parasitic capacitance, and inappropriate data transfer rates.

[0132] Figure 14Further illustrated is that after the first external connector 1405 is formed, the first interposer 1425 that supports the first optical device 950 and the laser die 1200 can be joined to the package substrate 1450 by, for example, the first external connector 1405. In an embodiment, the package substrate 1450 can be a package substrate, which can be a printed circuit board (PCB) or the like. The package substrate 1450 can include one or more dielectric layers and electrical conductive components, such as wires and vias. In some embodiments, the package substrate 1450 can include through vias, active devices, passive devices, and the like. The package substrate 1450 can also include conductive pads formed on the upper and lower surfaces of the package substrate 1450.

[0133] The first external connector 1405 can be aligned with a corresponding conductive connection on the package substrate 1450. Once aligned, the first external connector 1405 can be reflow soldered to join the package substrate 1450 to the first interposer 1425. However, any suitable joining process can be used to connect the first interposer 1425 to the package substrate 1450. In some embodiments, an underfill material 1501 (not shown in Figure 14 but shown in Figure 15 ) can be deposited between the first external connector 1405 and the package substrate 1450 to provide joint support around the first external connector 1405.

[0134] In addition, the package substrate 1450 can be prepared for further placement by forming a second external connector 1451 on the side of the package substrate 1450 opposite the first interposer 1425. In an embodiment, the second external connector 1451 can be formed using a process and materials similar to those of the first external connector 1405. However, any suitable materials and processes can also be utilized.

[0135] In an embodiment, Figure 14 Further illustrated is that the second support substrate 1300 includes a coupling lens 1475, which is positioned to facilitate movement from the optical fiber 1477 into a grating coupler of, for example, a second optical element 503 such as the first optical element 203, the first metallization layer 501, or a third optical element 511. In an embodiment, the coupling lens 1475 can be formed by shaping the material (e.g., silicon) of the second support substrate 1300 using a mask and etching process. However, any suitable process can also be utilized. The optical fiber 1477 can be maintained in position using, for example, an optical adhesive 1479. In some embodiments, the optical adhesive 1479 includes a polymeric material such as epoxy - acrylate oligomers and can have a refractive index in the range of about 1 to about 3. However, any suitable material can also be utilized.

[0136] In addition, although the optical fiber 1477 is illustrated as being attached at this point in the manufacturing process, this is for illustrative purposes only and is not intended to be limiting. Instead, the optical fiber 1477 can be attached at any suitable point in the process, such as at a point in time after subsequent packaging (which will be further described below). Any suitable attachment point in time can be utilized, and all such attachments at any point in the process are fully intended to be included within the scope of the embodiments of the present disclosure.

[0137] Figure 15 is illustrated Figure 14 an alternative embodiment of the final structure illustrated in, differing in that instead of bonding the first optical device 950 to the first mediator 1425, the second optical device 1050 is bonded to the first mediator 1425. In this embodiment, the second planarization process 1275 planarizes the top surfaces of the second semiconductor element 1001, the second gap-fill material 1250, and the first support substrate 1205, where after the second planarization process 1275, these top surfaces are substantially coplanar within process variations and can be collectively referred to as the second planar top surface. In this embodiment, the second support substrate 1300 can be bonded to the second planar top surface in an approximate manner as discussed above with respect to bonding the second support substrate 1300 to the first planar top surface. In this embodiment, all other structures and the methods of forming these structures are performed in an approximate or identical manner as forming Figure 14 the structure illustrated in.

[0138] Figure 15 is illustrated an optional underfill material 1501 deposited between the first external connector 1405 and the package substrate 1450. The underfill material 1501 can reduce stress and protect the joints created by the reflow soldering of the first external connector 1405. The underfill material 1501 can be formed by a capillary flow process after attaching the first mediator 1425 and the package substrate 1450.

[0139] Figure 16 is illustrated Figure 14Another embodiment of the final structure shown, where after the first optical device 950 is bonded to the first redistribution structure 1100, the second planarization process 1275 does not remove the second substrate 801. In this embodiment, the second planarization process 1275 planarizes the top surfaces of the second substrate 801, the second gap-fill material 1250, and the first support substrate 1205, where after the second planarization process 1275, these top surfaces are substantially coplanar within process variations and can be collectively referred to as a third planar top surface. In this embodiment, the second support substrate 1300 can be bonded to the third planar top surface in a manner similar to that discussed above with respect to bonding the second support substrate 1300 to the first planar top surface. Additionally, in this embodiment, the second substrate 801 can serve as and be referred to as a third support substrate. In this embodiment, all other structures and methods of forming these structures are performed in a manner similar or identical to that discussed for forming Figure 14 the structure shown.

[0140] The embodiments discussed in this disclosure achieve several benefits. In the above embodiment, the use of the second support substrate 1300 allows for the removal of the bulk silicon from the first interposer 1425, thereby improving the proximity of the electrical connections to the optical devices (e.g., the first optical device 950 and the second optical device 1050), and allowing the laser die 1200 to pass through the first interposer 1425 from the encapsulation substrate 1450. By supporting the optical package from above with the second support substrate 1300, the first interposer 1425 can be thinned without the need for long via metal routing through the first interposer 1425, thereby greatly reducing the electrical losses and the effects of parasitic capacitance caused by through-silicon vias passing through the bulk silicon in a typical interposer. Additionally, these reduced negative impacts and the improved proximity of the electronic components to the functional devices facilitate improved high-speed operation and higher data transfer rates. Similarly, by eliminating the need for through-silicon vias through the first interposer 1425, the risk of damage caused by forming these vias into the first interposer 1425 is eliminated. Additionally, the use of support substrates (e.g., the first support substrate 1305 and the second substrate 801 serving as the third support substrate) allows for the individual optimization of the optical devices and the laser die before integration onto the first interposer 1425. Additionally, by positioning the functional devices (e.g., the laser die 1200 and the optical devices) between the first interposer 1425 and the second support substrate 1300 and using the second gap-fill material 1250 to provide support, the need for a structural molding compound is eliminated, and a more uniform package structure is provided.

[0141] According to an embodiment, a method of manufacturing an integrated circuit device includes forming a first redistribution structure over a first silicon substrate, bonding an optical engine to the first redistribution structure; attaching a second silicon substrate to a top surface of the optical engine, and removing the first silicon substrate. In an embodiment, the step of removing the first silicon substrate includes removing a first portion of the first silicon substrate by a grinding process, and removing a second portion of the first silicon substrate by a chemical mechanical polishing process. In an embodiment, it further includes forming a plurality of conductive connectors coupled to the first redistribution structure, and attaching the conductive connectors to a substrate. In an embodiment, it further includes bonding a laser device to the first redistribution structure, and during the step of attaching the second silicon substrate to the optical engine, attaching the second silicon substrate to the laser device. In an embodiment, the first redistribution structure optically couples the laser device to the optical engine. In an embodiment, it further includes encapsulating the optical engine in an insulating material, wherein after the step of attaching the second silicon substrate, the insulating material is disposed between the first redistribution structure and the second silicon substrate. In an embodiment, it further includes forming a lens within the second silicon substrate, the lens being located above the optical engine.

[0142] According to an embodiment, an optical device includes an optical package having a first surface and a second surface opposite the first surface, a laser die package having a third surface and a fourth surface opposite the third surface, wherein the first surface is aligned with the third surface, and the second surface is aligned with the fourth surface, a first silicon support attached to both the second surface and the fourth surface, and an interposer attached to both the first surface and the third surface, wherein the interposer does not include a silicon substrate. In an embodiment, the first surface and the third surface are coplanar, and the second surface and the fourth surface are coplanar. In an embodiment, it further includes a first insulating material encapsulating both the optical package and the laser die package, wherein the first insulating material spans from the interposer to the first silicon support. In an embodiment, the laser die package includes a laser diode, and a second silicon support above the laser diode and opposite the interposer, wherein the second silicon support has a fourth surface. In an embodiment, the optical package includes an optical interposer attached to the interposer, an electronic integrated circuit bonded to the optical interposer and opposite the interposer, a third silicon support above the electronic integrated circuit, wherein the third silicon support has a fourth surface, and a second insulating material encapsulating the electronic integrated circuit, wherein the second insulating material spans from the optical interposer to the third silicon support. In an embodiment, the optical package includes an electronic integrated circuit, wherein the electronic integrated circuit has the same width as the optical package. In an embodiment, the first silicon support has a thickness in the range of 700 millimeters to 1500 millimeters.

[0143] According to an embodiment, a method of manufacturing an integrated circuit device includes forming a first redistribution structure over a first silicon substrate, bonding an optical package to the first redistribution structure, bonding a laser die to the first redistribution structure, encapsulating the optical package and the laser die in an insulating material, planarizing the insulating material, the optical package, and the laser die and forming a planar surface, attaching a second silicon substrate to the planar surface, and removing the first silicon substrate. In an embodiment, the step of removing the first silicon substrate includes removing a first portion of the first silicon substrate by a grinding process and removing a second portion of the first silicon substrate by a chemical mechanical polishing process. In an embodiment, it further includes forming an optical lens within the second silicon substrate over the optical package and attaching an optical fiber adjacent to the optical lens. In an embodiment, it further includes forming a second redistribution structure over the first redistribution structure after removing the first silicon substrate. In an embodiment, both the first redistribution structure and the second redistribution structure do not include a silicon substrate. In an embodiment, it further includes forming a plurality of microbumps on a plurality of conductive components of the second redistribution structure, bonding the microbumps to a substrate, and forming external connectors on an opposite side of the substrate opposite to the microbumps.

[0144] The foregoing outlines features of several embodiments so that those of ordinary skill in the art to which the present disclosure pertains can more readily understand the aspects of the embodiments of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should understand that they can readily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as those introduced herein. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure and can be made various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined by the appended claims.

Claims

1. An optical device, characterized in that: include: An optical package having a first surface and a second surface opposite to the first surface; A laser die package having a third surface and a fourth surface opposite to the third surface, wherein the first surface is aligned with the third surface, and the second surface is aligned with the fourth surface; a first silicon support attached to both the second surface and the fourth surface; and An interposer is attached to both the first surface and the third surface, wherein the interposer does not contain a silicon substrate.

2. The optical device according to claim 1, characterized in that The first surface is coplanar with the third surface, and the second surface is coplanar with the fourth surface.

3. The optical device according to claim 1, wherein: Also includes: A first insulating material encapsulates both the optical package and the laser die package, wherein the first insulating material spans from the interposer to the first silicon support.

4. The optical device according to claim 3, characterized in that The laser chip package includes: a laser diode; and A second silicon support is above the laser diode and opposite to the interposer, wherein the second silicon support has the fourth surface.

5. The optical device according to claim 4, characterized in that The optical package comprises: an optical medium attached to the medium; an electronic integrated circuit bonded to and opposite to the optical medium; a third silicon support member, above the electronic integrated circuit, wherein the third silicon support member has the fourth surface; and A second insulating material encapsulates the electronic integrated circuit, wherein the second insulating material spans from the optical medium to the third silicon support.

6. The optical device according to claim 1, wherein: The optical package includes an electronic integrated circuit, wherein the electronic integrated circuit and the optical package have the same width.

7. The optical device according to claim 1, wherein: The first silicon support has a thickness ranging from 700 mm to 1500 mm.

8. The optical device according to claim 1, wherein: The interposer has a thickness ranging from 10 micrometers to 150 micrometers.

9. The optical device according to claim 1, wherein: Also includes: A plurality of micro bumps are disposed on the intermediary.

10. The optical device according to claim 1, wherein: The first silicon support member includes a lens.

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