Display panel and display device

Abstract

The utility model provides a display panel and a display device, and the display panel is provided with a level transmission module and an output control module, controls an output signal of an output signal end through an output control transistor and an output control line, and controls an output signal of a level transmission signal output end through the level transmission module. The stage transmission signal and the output signal of the output signal end are output separately, so that when the normal transmission of the stage transmission signal is maintained, the display frequencies of the output control line in each area of the display panel are the same, and high potential is output when the display frequencies are the maximum frequency; alternating high potentials and low potentials are output when the display frequencies of at least two areas of the display panel are different, so that the display panel can display at the same frequency on the whole surface or display at different frequencies in different areas, high-frequency display is achieved in a watching area of a user, and low-frequency display is achieved in a non-watching area of the user. The power consumption is reduced while the visual effect is not affected, and the visual effect and low power consumption are both considered.

Description

Technical Field

[0001] The utility model relates to the technical field of display, in particular to a display panel and a display device. Background Art

[0002] Liquid crystal display devices can display information at high speed, high brightness and high contrast due to their thin thickness and excellent picture quality, and are widely used in display systems. With the development of display technology, users' requirements for display experience are getting higher, which makes the refresh rate of display devices higher and higher. However, the increase in the refresh rate of display devices will lead to an increase in the power consumption of the display panel, and then lead to a shorter battery life of the display device. Reducing the refresh rate to reduce power consumption will result in a worse visual effect.

[0003] Therefore, there is a technical problem that the existing display devices cannot balance visual effect and low power consumption. Summary of the Utility Model

[0004] Embodiments of the utility model provide a display panel and a display device to solve the technical problem that the existing display devices cannot balance visual effect and low power consumption.

[0005] Embodiments of the utility model provide a display panel, which includes a display part and a gate driving circuit located on at least one side of the display part. The gate driving circuit includes a plurality of cascaded gate driving units. The gate driving unit includes:

[0006] An input pull-up module;

[0007] A stage transmission module connected to the input pull-up module. The stage transmission module includes a stage transmission signal output end, and is configured to control the output signal of the stage transmission signal output end according to the output signal of the input pull-up module;

[0008] An output control module electrically connected to the stage transmission module. The output control module includes an output signal end, an output control line and an output control transistor. The output signal end and the output control line are respectively connected to two electrodes of the output control transistor;

[0009] Wherein, the display panel further includes a start signal line. The input pull-up module of the first-stage gate driving unit is connected to the start signal line. The input pull-up module of the nth-stage gate driving unit is connected to the stage transmission signal output end of the (n - 1)th-stage gate driving unit. The output control line is configured to output a high potential when the display frequencies of all regions of the display panel are the same and are the maximum display frequency. The output control line is configured to output alternating high and low potentials when the display frequencies of at least two regions of the display panel are different. n is greater than or equal to 2 and is a positive integer.

[0010] In some embodiments, the input pull-up module includes an input pull-up transistor. The gate of the input pull-up transistor of the first stage of the gate driving unit is connected to the start signal line, and the gate of the input pull-up transistor of the nth stage of the gate driving unit is connected to the stage transmission signal output terminal of the (n - 1)th stage of the gate driving unit. The first electrode of the input pull-up transistor is connected to the high-potential signal terminal, and the second electrode of the input pull-up transistor is connected to the stage transmission module.

[0011] In some embodiments, the stage transmission module includes:

[0012] A stage transmission pull-up module, which includes a first stage transmission transistor, a second stage transmission transistor, and a first capacitor. The gate of the first stage transmission transistor is connected to the high-potential signal terminal. The first electrode of the first stage transmission transistor and one plate of the first capacitor are connected to the second electrode of the input pull-up transistor. The second electrode of the first stage transmission transistor is connected to the gate of the second stage transmission transistor. The first electrode of the second stage transmission transistor is connected to the clock signal line of this stage. The second electrode of the second stage transmission transistor is connected to the stage transmission signal output terminal. The second plate of the first capacitor is connected to the low-potential signal terminal;

[0013] A stage transmission pull-down module, which includes a third stage transmission transistor, a fourth stage transmission transistor, a fifth stage transmission transistor, and a second capacitor. The gate of the third stage transmission transistor is connected to the second electrode of the input pull-up transistor. The first electrode of the third stage transmission transistor is connected to the low-potential signal terminal. The second electrode of the third stage transmission transistor, the gate of the fourth stage transmission transistor, the gate of the fifth stage transmission transistor, and one plate of the second capacitor are connected. The first electrodes of the fourth stage transmission transistor, the fifth stage transmission transistor, and the other plate of the second capacitor are connected to the low-potential signal terminal. The second electrode of the fourth stage transmission transistor is connected to the second electrode of the input pull-up transistor. The second electrode of the fifth stage transmission transistor is connected to the stage transmission signal output terminal.

[0014] In some embodiments, the gate of the output control transistor is connected to the stage transmission signal output terminal.

[0015] In some embodiments, the gate driving unit further includes an output pull-up module, which includes an output pull-up transistor. The gate of the output pull-up transistor is connected to the second electrode of the first stage transmission transistor. The first electrode of the output pull-up transistor is connected to the clock signal line of this stage. The second electrode of the output pull-up transistor is connected to the gate of the output control transistor.

[0016] In some embodiments, the gate driving unit further includes an output pull-down module, and the output pull-down module includes an output pull-down transistor. The gate of the output pull-down transistor is connected to the second electrode of the third-stage transfer transistor. The first electrode of the output pull-down transistor is connected to the low-potential signal terminal. The second electrode of the output pull-down transistor is connected to the output signal terminal.

[0017] In some embodiments, the gate driving unit further includes a pull-down control module, and the pull-down control module includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor. The gate of the first pull-down transistor is connected to the high-potential signal terminal. The first electrode of the first pull-down transistor is connected to the next-stage clock signal line. The second electrode of the first pull-down transistor, the second electrode of the second pull-down transistor, and the gate of the third pull-down transistor are connected. The gate of the second pull-down transistor and the first electrode of the fourth pull-down transistor are connected to the low-potential signal line. The first electrode of the second pull-down transistor is connected to the previous-stage clock signal line. The first electrode of the third pull-down transistor is connected to the high-potential signal terminal. The second electrode of the third pull-down transistor is connected to the gate of the fourth-stage transfer transistor. The gate of the fourth pull-down transistor is connected to the output signal terminal of the next-stage gate driving unit. The second electrode of the fourth pull-down transistor is connected to the second electrode of the input pull-up transistor.

[0018] In some embodiments, the display panel includes a display area, and the display area includes a first sub-display area, a second sub-display area, and a third sub-display area. The display frequencies of any two of the first sub-display area, the second sub-display area, and the third sub-display area are different.

[0019] In some embodiments, within the first time period of a cycle, the output control line outputs a high potential during the working time of the first-stage to the nth-stage gate driving units. Within the second time period of a cycle, the output control line outputs a low potential during the working time of the first-stage to the (k - 1)th-stage gate driving units, outputs a high potential during the working time of the kth-stage to the (k + m)th-stage gate driving units, and outputs a low potential during the working time of the (k + m + 1)th-stage to the nth-stage gate driving units. Within the third time period of a cycle, the output control line outputs a low potential during the working time of the first-stage to the (k - 1)th-stage gate driving units and outputs a high potential during the working time of the kth-stage to the nth-stage gate driving units, where k is greater than or equal to 2 and less than or equal to n, m is greater than or equal to 1 and less than or equal to n, and both k and m are positive integers.

[0020] Meanwhile, an embodiment of the present invention provides a display device, and the display device includes the display panel as described in any one of the above embodiments.

[0021] Beneficial effects: The present utility model provides a display panel and a display device. By providing a stage transmission module and an output control module, the display panel controls the output signal of the output signal terminal through an output control transistor and an output control line, and controls the output signal of the stage transmission signal output terminal through the stage transmission module, realizing the separate output of the stage transmission signal and the output signal of the output signal terminal. Thus, when maintaining the normal transmission of the stage transmission signal, the output control line can output a high potential when the display frequencies in each area of the display panel are the same and at the maximum frequency, and output alternating high and low potentials when the display frequencies in at least two areas of the display panel are different, so as to enable the display panel to display at the same frequency across the entire surface or display at different frequencies in different areas, thereby achieving high-frequency display in the user's fixation area and low-frequency display in the user's non-fixation area, reducing power consumption while not affecting the visual effect, and taking into account both visual effect and low power consumption. Description of the Drawings

[0022] The following, in conjunction with the drawings, through a detailed description of the specific embodiments of the present utility model, will make the technical solutions and other beneficial effects of the present utility model obvious.

[0023] Figure 1 It is the circuit diagram of the comparative gate driving circuit provided by the embodiment of the present utility model.

[0024] Figure 2 is Figure 1 the timing diagram of the comparative gate driving circuit in

[0025] Figure 3 It is the schematic diagram of the display panel provided by the embodiment of the present utility model.

[0026] Figure 4 It is the stage transmission schematic diagram of the gate driving circuit provided by the embodiment of the present utility model.

[0027] Figure 5 It is the module diagram of the gate driving unit provided by the embodiment of the present utility model.

[0028] Figure 6 It is the first circuit diagram of the gate driving unit provided by the embodiment of the present utility model.

[0029] Figure 7 It is the second circuit diagram of the gate driving unit provided by the embodiment of the present utility model.

[0030] Figure 8 It is the partition schematic diagram of the display panel provided by the embodiment of the present utility model.

[0031] Figure 9 It is the timing diagram of the gate driving circuit corresponding to when the display panel provided by the embodiment of the present utility model is configured such that the display frequencies in each area are the maximum display frequency.

[0032] Figure 10 The timing diagram of the gate driving circuit corresponding to the display panel provided by the embodiment of the present utility model when the display frequencies of each area are different. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present utility model.

[0034] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.

[0035] In the description of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a communication with each other; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0036] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "under" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of the present utility model. To simplify the disclosure of the present utility model, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present utility model. In addition, the present utility model may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present utility model provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0038] Figure 1 The circuit diagram of the comparative gate drive circuit provided for the embodiment of the present utility model. Figure 2 is Figure 1 the timing diagram of the comparative gate drive circuit in

[0039] As an introduction to the embodiment of the present utility model, some comparative gate drive circuits are provided to illustrate the principle of the technical problem to be solved by the embodiment of the present utility model. As Figure 1As shown, the comparison gate driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first storage capacitor C01 and a second storage capacitor C02. The gate of the first transistor T1 of the first-stage comparison gate driving circuit is connected to the initial signal line STV0, and the gates of the first transistors T1 of other-stage comparison gate driving circuits are connected to the output terminal G0(n - 2) of the upper two-stage comparison gate driving circuits. The first electrode of the first transistor T1 is connected to the high potential terminal VGH0, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 and one plate of the first storage capacitor C01. The other plate of the first storage capacitor C01 is connected to the low potential terminal VGL0. The gate of the second transistor T2 is connected to the gate of the high potential terminal VGH0, and the second electrode of the second transistor T2 is connected to the gate of the third transistor T3. The first electrode of the third transistor T3 is connected to the clock line CK0(n) of this stage, and the second electrode of the third transistor T3 is connected to the output terminal G0(n) of this-stage comparison gate driving circuit. The gate of the fourth transistor T4 is connected to the second electrode of the first transistor T1, the first electrode of the fourth transistor T4 is connected to the low potential terminal VGL0, and the second electrode of the fourth transistor T4, the gate of the fifth transistor T5, one plate of the second storage capacitor C02 and the gate of the sixth transistor T6 are connected. The first electrodes of the fifth transistor T5, the other plate of the second storage capacitor C02 and the first electrode of the sixth transistor T6 are connected to the low potential terminal VGL0. The second electrode of the fifth transistor T5 is connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 is connected to the output terminal G0(n). The gate of the seventh transistor T7 is connected to the high potential terminal VGH0, the first electrode of the seventh transistor T7 is connected to the clock lines CK0(n + 2) of the lower two stages, and the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8 and the gate of the ninth transistor T9 are connected. The gate of the eighth transistor T8 is connected to the low potential terminal, the first electrode of the eighth transistor T8 is connected to the clock signal lines CK0(n - 2) of the upper two stages, the first electrode of the ninth transistor T9 is connected to the high potential terminal VGH0, and the second electrode of the ninth transistor T9 is connected to the second electrode of the fourth transistor T4. The gate of the tenth transistor T10 is connected to the output terminal G0(n + 2) of the lower two-stage comparison gate driving circuits, the first electrode of the tenth transistor T10 is connected to the low potential terminal VGL0, and the second electrode of the tenth transistor T10 is connected to the gate of the fourth transistor T4. Among them, four clock lines are multiplexed in the comparison gate driving circuit, that is, the first to fourth-stage comparison gate driving circuits use four clock lines in sequence, and the fifth to eighth-stage comparison gate driving circuits reuse the four clock lines.

[0040] As Figure 2As shown Figure 2 shows Figure 1 the timing diagrams of the respective signal lines of the comparison gate driving circuit in Figure 2 It can be seen from

[0041] In view of the above technical problems, the embodiments of the present invention provide a display panel and a display device to solve the above technical problems.

[0042] Figure 3 It is a schematic diagram of the display panel provided by the embodiment of the present invention. Figure 4 It is a schematic diagram of the stage transmission of the gate driving circuit provided by the embodiment of the present invention. Figure 5 It is a module diagram of the gate driving unit provided by the embodiment of the present invention. Figure 6 It is the first circuit diagram of the gate driving unit provided by the embodiment of the present invention. Figure 7 It is the second circuit diagram of the gate driving unit provided by the embodiment of the present invention. Figure 8 It is a partition diagram of the display panel provided by the embodiment of the present invention. Figure 9 It is the timing diagram of the gate driving circuit corresponding to when the display panel provided by the embodiment of the present invention is configured such that the display frequency of each area is the maximum display frequency. Figure 10 It is the timing diagram of the gate driving circuit corresponding to when the display panel provided by the embodiment of the present invention is configured such that the display frequencies of each area are different.

[0043] As in Figures 3 to 10As shown in the figure, an embodiment of the present invention provides a display panel 1, which includes a display portion 11 and a gate driving circuit 12 located on at least one side of the display portion 11. The gate driving circuit 12 includes a plurality of cascaded gate driving units 120. The gate driving unit 120 includes an input pull-up module 10, a stage transmission module 20, and an output control module 30. The stage transmission module 20 is connected to the input pull-up module 10. The stage transmission module 20 includes a stage transmission signal output terminal Carry(n). The stage transmission module 20 is configured to control the output signal of the stage transmission signal output terminal Carry(n) according to the output signal of the input pull-up module 10. The output control module 30 is electrically connected to the stage transmission module 20. The output control module 30 includes an output signal terminal G(n), an output control line SW, and an output control transistor NT13. The output signal terminal G(n) and the output control line SW are respectively connected to two electrodes of the output control transistor NT13.

[0044] Among them, the display panel 1 further includes a start signal line STV. The input pull-up module 10 of the first-stage gate driving unit 120 is connected to the start signal line STV. The input pull-up module 10 of the nth-stage gate driving unit is connected to the stage transmission signal output terminal Carry(n - 1) of the (n - 1)th-stage gate driving unit 120. The output control line SW is configured to output a high potential when the display frequencies of all regions of the display panel 1 are the same and are the maximum display frequency, and output alternating high and low potentials when the display frequencies of at least two regions of the display panel 1 are different. n is greater than or equal to 2, and n is a positive integer.

[0045] An embodiment of the present invention provides a display panel. By setting a stage transmission module and an output control module, the output signal of the output signal terminal is controlled by an output control transistor and an output control line, and the output signal of the stage transmission signal output terminal is controlled by the stage transmission module, so that the stage transmission signal and the output signal of the output signal terminal are output separately. Thus, when the normal transmission of the stage transmission signal is maintained, the output control line can output a high potential when the display frequencies of all regions of the display panel are the same and are the maximum frequency, and output alternating high and low potentials when the display frequencies of at least two regions of the display panel are different, so as to enable the display panel to display at the same frequency across the entire surface or display at different frequencies in different regions, so as to display at a high frequency in the user's gaze area and at a low frequency in the user's non-gaze area, reducing power consumption while not affecting the visual effect, and taking into account both the visual effect and low power consumption.

[0046] Specifically, as Figure 3 shown, the display panel 1 includes a display area AA and a non-display area NA. The display portion 11 is disposed in the display area AA, the gate driving circuit 12 is disposed in the non-display area NA, and the display panel 1 further includes a terminal portion 13.

[0047] Specifically, as Figure 4 shown, each gate driving unit 120 includes an input end Input, an output end Out, and a stage transmission end Carry. The input end Input of the first-stage gate driving unit 120 is connected to the initial signal line STV, and the input ends Input of other-stage gate driving units 120 are connected to the stage transmission end Carry of the previous-stage gate driving unit 120. For example, the input end Input of the second-stage gate driving unit 120 is connected to the first-stage transmission signal output end Carry1 of the first-stage gate driving unit 120, the input end Input of the third-stage gate driving unit 120 is connected to the second-stage transmission signal output end Carry2 of the second-stage gate driving unit 120, the input end Input of the k-th stage gate driving unit 120 is connected to the (k - 1)-th stage transmission signal output end Carry(k - 1) of the (k - 1)-th stage gate driving unit 120, the input end Input of the (k + 2)-th stage gate driving unit is connected to the (k + 1)-th stage transmission signal output end Carry(k + 1) of the (k + 1)-th stage gate driving unit 120, the input end Input of the (n - 1)-th stage gate driving unit 120 is connected to the (n - 2)-th stage transmission signal output end Carry(n - 1) of the (n - 2)-th stage gate driving unit 120, the input end Input of the n-th stage gate driving unit 120 is connected to the (n - 1)-th stage transmission signal output end Carry(n - 1) of the (n - 1)-th stage gate driving unit 120, and the connection position of the n-th stage transmission signal output end Carry(n) of the n-th stage gate driving unit 120 is not limited. Thus, the stage transmission of the gate driving circuit can be completed with only one initial signal line STV, reducing the number of signal lines.

[0048] Meanwhile, in the embodiment of the present utility model, an output control module 30 is provided, so that the output control modules 30 of each gate driving unit can control the signals output to each output signal terminal. For example Figure 4 in, the signal of the first output signal terminal G(1) is controlled by the output control module 30 in the first-stage gate driving unit, the signal of the second output signal terminal G(2) is controlled by the output control module 30 in the second-stage gate driving unit, the signal of the k-th output signal terminal G(k) is controlled by the output control module 30 in the k-th stage gate driving unit, the signal of the (k + 1)-th output signal terminal G(k + 1) is controlled by the output control module 30 in the (k + 1)-th stage gate driving unit, the signal of the (n - 1)-th output signal terminal G(n - 1) is controlled by the output control module 30 in the (n - 1)-th stage gate driving unit, and the signal of the n-th output signal terminal G(n) is controlled by the output control module 30 in the n-th stage gate driving unit. Thus, the signals of the stage transmission signal output terminal and the output signal terminal are independently controlled, and correspondingly, the output signals of the output signal terminals in different regions can be different, enabling the display panel to display in different frequencies in different regions.

[0049] Specifically, it can be understood that the input end Input in the above embodiments can be the input end of the input pull-up module in the following embodiments, specifically the signal end connected to the gate of the input pull-up transistor. The output end Out can be the input end of the output control module, specifically the signal end connected to the gate of the output control transistor. The carry end Carry can be the carry signal output end in the following embodiments.

[0050] Specifically, in the comparison gate driving circuit, the output signal end and the carry signal output end are multiplexed. Therefore, each gate driving unit will output signals to the scanning line simultaneously during carry transmission, making the frequencies of the signals on the entire display panel the same. In the present invention, the output signal end and the carry signal output end are separately provided, and an output control module is provided to control the output signal of the output signal end. When the carry signal output end normally outputs the carry signal, the output signals of some output signal ends can be different from those of other output signal ends. Thus, the input signals of different scanning lines can be different, the refresh frequencies of each row of pixel units can be different, and the display frequencies of different regions can be different, reducing power consumption. Moreover, high-frequency display can be achieved in the user's gaze area and low-frequency display in the non-gaze area of the user, without affecting the visual effect.

[0051] In some embodiments, as Figure 5 、 Figure 6 shown, the input pull-up module 10 includes an input pull-up transistor NT1. The gate of the input pull-up transistor NT1 of the first-stage gate driving unit 120 is connected to the start signal line STV. The gate of the input pull-up transistor NT1 of the nth-stage gate driving unit 120 is connected to the carry signal output end Carry(n - 1) of the (n - 1)th-stage gate driving unit 120. The first electrode of the input pull-up transistor NT1 is connected to the high-potential signal terminal VGH, and the second electrode of the input pull-up transistor NT1 is connected to the carry module 20. By connecting the gate of the input pull-up transistor of the first-stage gate driving unit to the start signal line, when the gate driving circuit operates, the first-stage gate driving unit can be turned on through the start signal line. At the same time, the gates of the input pull-up transistors of the subsequent gate driving units are connected to the carry signal output ends of the previous-stage gate driving units, and signal carry can be achieved through the outputs of each gate driving unit. There is no need to set multiple start signal lines, reducing the number of signal lines, minimizing the space occupied by the gate driving circuit, and increasing the screen-to-body ratio of the display panel.

[0052] Specifically, as Figure 6 、 Figure 7As shown, it can be seen that the signal line connected to the gate of the input pull-up transistor NT1 is labeled with the start signal line STV and the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage of the gate driving unit 120. It can be understood that in the first-stage gate driving unit, the signal line connected to the gate of the input pull-up transistor NT1 is the start signal line STV, and in other-stage gate driving units, the signal line connected to the gate of the input pull-up transistor NT1 is the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage of the gate driving unit 120.

[0053] Specifically, it can be understood that the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage of the gate driving unit 120 is the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage. Since the value of n can be selected as a positive integer between 2 and the number of stages of the gate driving unit + 1, the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage of the gate driving unit 120 can refer to the stage transfer signal output terminal of any one of all the gate driving units. For example, when n = 2, the stage transfer signal output terminal Carry(n - 1) of the (n - 1)-th stage of the gate driving unit 120 is the stage transfer signal output terminal of the first-stage gate driving unit, that is, the first-stage transfer signal output terminal Carry1. Similarly, the stage transfer signal output terminals of other-stage gate driving units can be referred to the above description and will not be elaborated in the following embodiments.

[0054] In some embodiments, as Figure 6 、 Figure 7 shown, the stage transfer module 20 includes:

[0055] A stage transfer pull-up module 201, the stage transfer pull-up module 201 includes a first stage transfer transistor NT7, a second stage transfer transistor NT9, and a first capacitor C1. The gate of the first stage transfer transistor NT7 is connected to the high potential signal terminal VGH. The first electrode of the first stage transfer transistor NT7 and one plate of the first capacitor C1 are connected to the second electrode of the input pull-up transistor NT1. The second electrode of the first stage transfer transistor NT7 is connected to the gate of the second stage transfer transistor NT9. The first electrode of the second stage transfer transistor NT9 is connected to the local clock signal line CK(n). The second electrode of the second stage transfer transistor NT9 is connected to the stage transfer signal output terminal Carry(n). The second plate of the first capacitor C1 is connected to the low potential signal terminal VGL;

[0056] Level transfer pull-down module 202, the level transfer pull-down module 202 includes a third-level transfer transistor NT6, a fourth-level transfer transistor NT5, a fifth-level transfer transistor NT10 and a second capacitor C2. The gate of the third-level transfer transistor NT6 is connected to the second electrode of the input pull-up transistor NT1. The first electrode of the third-level transfer transistor NT6 is connected to the low-potential signal terminal VGL. The second electrode of the third-level transfer transistor NT6, the gate of the fourth-level transfer transistor NT5, the gate of the fifth-level transfer transistor NT10 and one plate of the second capacitor C2 are connected. The first electrodes of the fourth-level transfer transistor NT5, the fifth-level transfer transistor NT10 and the other plate of the second capacitor C2 are connected to the low-potential signal terminal VGL. The second electrode of the fourth-level transfer transistor NT5 is connected to the second electrode of the input pull-up transistor NT1. The second electrode of the fifth-level transfer transistor NT10 is connected to the level transfer signal output terminal Carry(n). By providing a level transfer pull-up module and a level transfer pull-down module, the level transfer signal output terminal can be pulled up or pulled down, so that each gate driving unit can output a level transfer signal and the gate driving circuit can work properly.

[0057] In some embodiments, as Figure 7 shown, the gate of the output control transistor NT13 is connected to the level transfer signal output terminal Carry(n). By connecting the gate of the output control transistor to the level transfer signal output terminal, the number of transistors can be reduced, the occupied space of the gate driving unit can be reduced, the border of the display panel can be reduced, and the screen-to-body ratio of the display panel can be increased.

[0058] In some embodiments, as Figure 5 、 Figure 6 shown, the gate driving unit 120 further includes an output pull-up module 40. The output pull-up module 40 includes an output pull-up transistor NT11. The gate of the output pull-up transistor NT11 is connected to the second electrode of the first-level transfer transistor NT7. The first electrode of the output pull-up transistor NT11 is connected to the local clock signal line CK(n). The second electrode of the output pull-up transistor NT11 is connected to the gate of the output control transistor NT13. By providing that the gate driving unit further includes an output pull-up module, the output pull-up module includes an output pull-up transistor, the gate of the output pull-up transistor is connected to the second electrode of the first-level transfer transistor, the first electrode of the output pull-up transistor is connected to the local clock signal line, and the second electrode of the output pull-up transistor is connected to the gate of the output control transistor, the output control transistor can be controlled by the clock signal line and the level transfer pull-up module, and the output signal of the output signal terminal can be controlled by the output control line, so that different signals are output by the output control line in different display modes, and the power consumption can be reduced without affecting the visual effect.

[0059] In some embodiments, as Figures 5 to 7 shown, the gate driving unit 120 further includes an output pull-down module 50. The output pull-down module 50 includes an output pull-down transistor NT12. The gate of the output pull-down transistor NT12 is connected to the second electrode of the third-level transfer transistor NT6. The first electrode of the output pull-down transistor NT12 is connected to the low-potential signal terminal VGL. The second electrode of the output pull-down transistor NT12 is connected to the output signal terminal G(n). By providing the output pull-down module, with the first electrode of the output pull-down module connected to the low-potential signal terminal and the second electrode of the output pull-down module connected to the output signal terminal, after the current-stage gate driving unit normally outputs a signal, the output signal of the output signal terminal G(n) can be pulled down, preventing the scan line from being at a high potential for a long time and causing the pixel unit to be turned on for a long time, so that the display panel can display normally.

[0060] In some embodiments, as Figures 5 to 7 shown, the gate driving unit 120 further includes a pull-down control module 60. The pull-down control module 60 includes a first pull-down transistor NT3, a second pull-down transistor NT4, a third pull-down transistor NT8, and a fourth pull-down transistor NT2. The gate of the first pull-down transistor NT3 is connected to the high-potential signal terminal VGH. The first electrode of the first pull-down transistor NT3 is connected to the next-stage clock signal line CK(n + 1). The second electrode of the first pull-down transistor NT3, the second electrode of the second pull-down transistor NT4, and the gate of the third pull-down transistor NT8 are connected. The gate of the second pull-down transistor NT4 and the first electrode of the fourth pull-down transistor NT2 are connected to the low-potential signal line VGL. The first electrode of the second pull-down transistor NT4 is connected to the previous-stage clock signal line CK(n - 1). The first electrode of the third pull-down transistor NT8 is connected to the high-potential signal terminal VGH. The second electrode of the third pull-down transistor NT8 is connected to the gate of the fourth-level transfer transistor NT5. The gate of the fourth pull-down transistor NT2 is connected to the output signal terminal G(n + 1) of the next-stage gate driving unit 120. The second electrode of the fourth pull-down transistor NT2 is connected to the second electrode of the input pull-up transistor NT1. By providing the pull-down control module, after the current-stage gate driving unit normally outputs a signal, the output signals of the stage transfer signal terminal Carry(n) and the output signal terminal G(n) can be pulled down, preventing the stage transfer signal terminal from outputting a high potential for a long time and causing other gate driving units to be unable to be turned off, and preventing the scan line from being at a high potential for a long time and causing the pixel unit to be turned on for a long time, so that the display panel can display normally.

[0061] Specifically, the display panel may include four clock signal lines. Taking the display panel including a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4 as an example, every four-level gate driving units are used as a repeating unit to multiplex the four clock signal lines. For example, the local clock signal lines in the first-level to fourth-level gate driving units are the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4 respectively, and the local clock signal lines in the fifth-level to eighth-level gate driving units are the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4 respectively. The previous-level clock signal line in the second-level gate driving unit is CK1, the local clock signal line in the second-level gate driving unit is the second clock signal line CK2, and the next-level clock signal line in the second-level gate driving unit is CK3. Similarly, the local clock signal line, the previous-level clock signal line, and the next-level clock signal line in other-level gate driving units can be determined.

[0062] In some embodiments, as Figure 8 shown, the display panel 1 includes multiple sub-display areas, and the display frequencies of the sub-display areas are different. By making the display panel include multiple sub-display areas with different display frequencies, the power consumption can be reduced, and high-frequency display is adopted for the user's gaze area without affecting the visual effect.

[0063] Specifically, as Figure 8 shown, the display area AA of the display panel may include a first sub-display area, a second sub-display area,..., an Nth sub-display area. The display area AA can be divided into multiple areas with different display frequencies, thereby reducing the power consumption.

[0064] Specifically, the display area includes a first sub-display area, a second sub-display area, and a third sub-display area, and the display frequencies of any two of the first sub-display area, the second sub-display area, and the third sub-display area are different.

[0065] In some embodiments, as Figure 8 、 Figure 9As shown, when the display panel 1 is configured such that the display frequencies of multiple regions are different, within the first time period t1 of one cycle t0, the output control line SW outputs a high potential during the working time of the first to the nth gate driving units. Within the second time period t2 of one cycle t0, the output control line SW outputs a low potential during the working time of the first to the (k - 1)th gate driving units 120, outputs a high potential during the working time of the kth to the (k + m)th gate driving units 120, and outputs a low potential during the working time of the (k + m + 1)th to the nth gate driving units 120. Within the third time period t3 of one cycle t0, the output control line outputs a low potential during the working time of the first to the (k - 1)th gate driving units 120 and outputs a high potential during the working time of the kth to the nth gate driving units 120, where k is greater than or equal to 2 and less than or equal to n, m is greater than or equal to 1 and less than or equal to n, and both k and m are positive integers. By making the output control line output different signals in different time periods of one cycle, the refresh rates of different regions of the display panel are different within one cycle, thereby reducing power consumption and enabling the control that the region where the user is gazing has a high refresh rate and the region where the user is not gazing has a low refresh rate, thus not affecting the visual effect.

[0066] Specifically, one cycle t0 can be 1 second.

[0067] Specifically, taking the example where the display frequencies of three regions of the display panel are different, specifically, the first sub-display region, the second sub-display region, and the third sub-display region display at 60 Hz, 120 Hz, and 90 Hz respectively, and the first sub-display region, the second sub-display region, and the third sub-display region are arranged in sequence longitudinally. Correspondingly, the scan lines of the first sub-display region, the second sub-display region, and the third sub-display region are respectively connected to the output signal terminals of the first to the (k - 1)th gate driving units, the output signal terminals of the kth to the (k + m)th gate driving units, and the output signal terminals of the (k + m + 1)th to the nth gate driving units.

[0068] From Figures 8 to 10 it can be seen that when the display panel is configured such that the display frequencies of each region are different, the first time period t1 is 0.5 seconds, the second time period t2 is 0.25 seconds, and the third time period t3 is 0.25 seconds. Within one cycle, the first clock line CK1, the second clock line CK2, the third clock line CK3, and the fourth clock line CK4 output high potentials in sequence, causing the first signal output terminal Carry to the nth signal output terminal Carry(n) to output high potentials in sequence, and the gate driving units perform normal signal transfer within one cycle.

[0069] In the first time period t1, after the start signal line STV outputs a high potential, the output control line SW is at a high potential, so that the output signal terminals of all gate driving units output normally, the scanning lines in each display area can turn on the transistors, and 60 refreshes can be performed in each display area.

[0070] In the second time period t2, after the start signal line STV outputs a high potential, the output control line SW outputs a low potential during the working time of the first-stage to (k - 1)-stage gate driving units 120, so that the first output signal terminal G(1) of the first-stage gate driving unit to the (k - 1)th output signal terminal G(k - 1) of the (k - 1)-stage gate driving unit output low potentials, and the scanning lines in the first sub-display area cannot turn on the transistors, that is, the first sub-display area does not refresh in the second time period t2. The output control line SW outputs a high potential during the working time of the kth to (k + m)-stage gate driving units 120, so that the kth output signal terminal G(k) of the kth gate driving unit to the (k + m)th output signal terminal G(k + m) of the (k + m)-stage gate driving unit output high potentials, and the scanning lines in the second sub-display area can turn on the transistors, that is, the second sub-display area refreshes 30 times in the second time period t2. The output control line SW outputs a low potential during the working time of the (k + m + 1)th to nth gate driving units 120, so that the (k + m + 1)th output signal terminal G(k + m + 1) of the (k + m + 1)-stage gate driving unit to the nth output signal terminal G(n) of the nth gate driving unit output low potentials, and the scanning lines in the third sub-display area cannot turn on the transistors, that is, the third sub-display area does not refresh in the second time period t2.

[0071] In the third time period t3, after the start signal line STV outputs a high potential, the output control line SW outputs a low potential during the working time of the first-stage to (k - 1)-stage gate driving units 120, so that the first output signal terminal G(1) of the first-stage gate driving unit to the (k - 1)th output signal terminal G(k - 1) of the (k - 1)-stage gate driving unit output low potentials, and the scanning lines in the first sub-display area cannot turn on the transistors, that is, the first sub-display area does not refresh in the third time period t3. The output control line SW outputs a high potential during the working time of the kth to nth gate driving units 120, so that the kth output signal terminal G(k) of the kth gate driving unit to the nth output signal terminal G(n) of the nth gate driving unit output high potentials, and the scanning lines in the second sub-display area and the third sub-display area can turn on the transistors, that is, the second sub-display area and the third sub-display area refresh 30 times in the third time period t3. Thus, it realizes that the first sub-display area refreshes 60 times, the second sub-display area refreshes 120 times, and the third sub-display area refreshes 90 times. The display frequency of the first sub-display area is 60 Hz, the display frequency of the second sub-display area is 120 Hz, and the refresh frequency of the third sub-display area is 90 Hz, achieving different refresh frequencies in different areas.

[0072] Specifically, in the above embodiments, the first sub-display area, the second sub-display area, and the third sub-display area are respectively used as examples with display frequencies of 60 Hz, 120 Hz, and 90 Hz. However, the embodiments of the present invention are not limited thereto. It can be understood that when the display panel is configured such that the display frequencies of multiple regions are different, the display area can be divided into two, three, four, or more sub-display areas, and the display frequencies of each sub-display area can be different.

[0073] Specifically, it can be understood that the embodiments of the present invention do not limit the maximum display frequency of the display panel. For example, the maximum display frequency of the display panel can be 120 Hz, 240 Hz, 480 Hz. Correspondingly, the display frequencies of each sub-display area can be any frequency not exceeding the maximum display frequency. For example, when the maximum display frequency of the display panel is 120 Hz, the display frequency of a sub-display area can be 30 Hz, 60 Hz, 90 Hz, or 120 Hz.

[0074] Specifically, as Figures 8 to 10 shown, when the display panel is configured such that each area displays at the maximum display frequency, the output control line SW is maintained at a high potential, so that within one cycle t0, the refresh frequencies of the first sub-display area, the second sub-display area, and the third sub-display area are the same.

[0075] Specifically, it can be understood that when the entire display panel has the same display frequency, the display frequency of the display panel is not limited to the maximum display frequency. For example, when the maximum display frequency of the display panel is 120 Hz, the entire display frequency of the display panel can be 90 Hz. At this time, the timing of the output control line can be adjusted accordingly.

[0076] Specifically, it can be understood that when a user views the display panel, there will be a fixation area and a non-fixation area. The embodiments of the present invention can make the refresh frequency of the display area corresponding to the user's fixation area in the display panel maintain a high refresh rate, and the refresh frequency of the display area corresponding to the user's non-fixation area in the display panel becomes a low refresh rate, thereby reducing power consumption while not requiring the user to view the effect.

[0077] Meanwhile, the embodiments of the present invention provide a display device, and the display device includes the display panel as described in any one of the above embodiments.

[0078] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0079] The above has introduced in detail a display panel and a display device provided by an embodiment of the present utility model. Specific examples are used herein to elaborate on the principle and implementation manner of the present utility model. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present utility model; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present utility model.

Claims

1. A display panel, characterized in that: The invention comprises a display part and a gate driving circuit located at at least one side of the display part, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving unit comprises: Input pull-up module; A level transmission module connected to the input pull-up module, the level transmission module comprising a level transmission signal output terminal, the level transmission module being configured to control an output signal of the level transmission signal output terminal according to an output signal of the input pull-up module; An output control module, the output control module is electrically connected to the stage transmission module, the output control module comprises an output signal terminal, an output control line and an output control transistor, the output signal terminal and the output control line are respectively connected to two electrodes of the output control transistor; Wherein, the display panel also includes a start signal line, an input pull-up module of the first-level gate driving unit is connected to the start signal line, an input pull-up module of the n-th-level gate driving unit is connected to the stage transmission signal output terminal of the n-1-th-level gate driving unit, the output control line is configured to output a high potential when the display frequencies of various areas of the display panel are the same and are the maximum display frequency, and the output control line is configured to output alternating high potentials and low potentials when the display frequencies of at least two areas of the display panel are different, n is greater than or equal to 2, and n is a positive integer.

2. The display panel according to claim 1, wherein: The input pull-up module includes an input pull-up transistor, the gate of the input pull-up transistor of the first-level gate driving unit is connected to the start signal line, the gate of the input pull-up transistor of the n-th-level gate driving unit is connected to the level transmission signal output end of the n-1-th-level gate driving unit, the first electrode of the input pull-up transistor is connected to the high-potential signal end, and the second electrode of the input pull-up transistor is connected to the level transmission module.

3. The display panel according to claim 2, wherein: The level transmission module comprises: A level transmission pull-up module, the level transmission pull-up module comprising a first level transmission transistor, a second level transmission transistor and a first capacitor, the gate of the first level transmission transistor is connected to the high potential signal end, the first electrode of the first level transmission transistor and a plate of the first capacitor are connected to the second electrode of the input pull-up transistor, the second electrode of the first level transmission transistor is connected to the gate of the second level transmission transistor, the first electrode of the second level transmission transistor is connected to the clock signal line of the current stage, the second electrode of the second level transmission transistor is connected to the level transmission signal output end, and the second plate of the first capacitor is connected to the low potential signal end; A level-transmission pull-down module, the level-transmission pull-down module includes a third-level transmission transistor, a fourth-level transmission transistor, a fifth-level transmission transistor and a second capacitor, the gate of the third-level transmission transistor is connected to the second electrode of the input pull-up transistor, the first electrode of the third-level transmission transistor is connected to the low-potential signal end, the second electrode of the third-level transmission transistor, the gate of the fourth-level transmission transistor, the gate of the fifth-level transmission transistor and one plate of the second capacitor are connected, the first electrode of the fourth-level transmission transistor, the first electrode of the fifth-level transmission transistor and the other plate of the second capacitor are connected to the low-potential signal end, the second electrode of the fourth-level transmission transistor is connected to the second electrode of the input pull-up transistor, and the second electrode of the fifth-level transmission transistor is connected to the level-transmission signal output end.

4. The display panel according to claim 3, wherein: The gate of the output control transistor is connected to the stage transmission signal output terminal.

5. The display panel according to claim 3, wherein: The gate driving unit also includes an output pull-up module, which includes an output pull-up transistor, the gate of the output pull-up transistor is connected to the second electrode of the first-stage pass transistor, the first electrode of the output pull-up transistor is connected to the clock signal line of the current stage, and the second electrode of the output pull-up transistor is connected to the gate of the output control transistor.

6. The display panel according to claim 4 or 5, characterized in that: The gate driving unit also includes an output pull-down module, which includes an output pull-down transistor, a gate of the output pull-down transistor is connected to the second electrode of the third-stage pass transistor, a first electrode of the output pull-down transistor is connected to the low-potential signal terminal, and a second electrode of the output pull-down transistor is connected to the output signal terminal.

7. The display panel according to claim 6, wherein: The gate driving unit also includes a pull-down control module, which includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor, wherein the gate of the first pull-down transistor is connected to a high potential signal terminal, the first electrode of the first pull-down transistor is connected to a clock signal line of a next stage, the second electrode of the first pull-down transistor, the second electrode of the second pull-down transistor and the gate of the third pull-down transistor are connected, the gate of the second pull-down transistor and the first electrode of the fourth pull-down transistor are connected to a low potential signal line, the first electrode of the second pull-down transistor is connected to a clock signal line of an upper stage, the first electrode of the third pull-down transistor is connected to a high potential signal terminal, the second electrode of the third pull-down transistor is connected to the gate of a fourth stage transistor, the gate of the fourth pull-down transistor is connected to an output signal terminal of the gate driving unit of the next stage, and the second electrode of the fourth pull-down transistor is connected to the second electrode of the input pull-up transistor.

8. The display panel according to claim 1, wherein: The display panel includes a display area, the display area includes a first sub-display area, a second sub-display area and a third sub-display area, and display frequencies of any two of the first sub-display area, the second sub-display area and the third sub-display area are different.

9. The display panel according to claim 8, wherein: In a first time period of a cycle, the output control line outputs a high potential during the working time of the first to n-th gate driving units; in a second time period of a cycle, the output control line outputs a low potential during the working time of the first to k-1-th gate driving units, outputs a high potential during the working time of the k-th to k+m-th gate driving units, and outputs a low potential during the working time of the k+m+1-th to n-th gate driving units; in a third time period of a cycle, the output control line outputs a low potential during the working time of the first to k-1-th gate driving units, and outputs a high potential during the working time of the k-th to n-th gate driving units, k is greater than or equal to 2 and less than or equal to n, m is greater than or equal to 1 and less than or equal to n, and k and m are both positive integers.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

Images