Semiconductor device

Abstract

A semiconductor device includes a substrate having one or more semiconductor devices. In some embodiments, the device also includes a first passivation layer disposed over the one or more semiconductor devices and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor technology, and in particular to semiconductor devices. Background Art

[0002] The electronics industry has an ever-increasing demand for smaller, faster semiconductor devices that can simultaneously support a large number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to fabricate low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down the size of semiconductor ICs (e.g., the minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, such scaling also increases the complexity of semiconductor manufacturing processes. Therefore, achieving continuous progress in semiconductor integrated circuits and devices requires synchronous progress in semiconductor manufacturing processes and technologies.

[0003] For example, as IC devices continue to scale down, passive devices that require a large surface area can be fabricated as part of the back end of line (BEOL) process. An example of a passive device that can be formed as part of the BEOL process is a metal-insulator-metal (MIM) capacitor. Generally, an MIM capacitor includes multiple conductor plate layers that are separated from each other by dielectric layers. In some examples, an MIM capacitor can be formed on a semiconductor substrate that includes a device layer (e.g., transistors, etc.) and a multi-layer interconnect (MLI) structure that provides interconnections between various microelectronic components within the substrate. In some embodiments, a passivation layer can be formed over the MIM capacitor, and contact vias can be formed to electrically couple a lower contact component to an upper contact component, such as a contact pad, for connection to an external circuit. In some cases, the dielectric layer of the MIM capacitor may degrade during subsequent processing. For example, a high-pressure anneal (HPA) can be performed after the MIM capacitor is formed to improve the performance of the front-end-of-line (FEOL) devices. However, such a process may also reduce the reliability of the dielectric layer of the MIM capacitor (e.g., by introducing oxygen vacancies at the dielectric layer interface).

[0004] Therefore, the prior art has not proven to be entirely satisfactory in all respects. Summary of the Invention

[0005] The present disclosure provides a semiconductor device, comprising: a substrate including one or more semiconductor devices; a first passivation layer disposed over the one or more semiconductor devices; and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer, wherein the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer, and wherein the insulator layer includes a metal oxide sandwich structure.

[0006] In one embodiment, a second passivation layer is further disposed over the metal-insulator-metal capacitor structure.

[0007] In one embodiment, the metal oxide sandwich structure includes a bottom insulator layer, an intermediate insulator layer over the bottom insulator layer, and a top insulator layer over the intermediate insulator layer, and wherein the bottom insulator layer and the top insulator layer are made of the same material.

[0008] In one embodiment, the intermediate insulator layer is composed of a stack of two types of interleaved insulator layers having different material compositions, and wherein one type of insulator layer in the stack of the two types of interleaved insulator layers has the same material composition as the bottom insulator layer and the top insulator layer.

[0009] In one embodiment, a first thickness of the intermediate insulator layer is at least ten times greater than a second thickness of the bottom insulator layer or the top insulator layer.

[0010] In one embodiment, it further includes:

[0011] a multi-layer interconnect structure at least partially disposed within the substrate, wherein the first passivation layer is disposed over the multi-layer interconnect structure.

[0012] In one embodiment, it further includes:

[0013] a contact component disposed over the second passivation layer, wherein the contact component is electrically coupled to the multi-layer interconnect structure.

[0014] The present disclosure provides a semiconductor device, comprising: a first passivation layer disposed over a substrate including active semiconductor devices; and a metal-insulator-metal (MIM) structure formed over the first passivation layer, wherein the MIM structure comprises: a plurality of conductor plate layers; and an insulator layer interposed between adjacent ones of the conductor plate layers; wherein the insulator layer comprises a multi-layer structure, and wherein the multi-layer structure comprises a first zirconium oxide (ZrO 2 ) layer, a second zirconium oxide layer, and a hafnium–zirconium oxide (HZO) layer interposed between the first and the second zirconium oxide layers.

[0015] In one embodiment, a second passivation layer is further disposed over the metal-insulator-metal structure.

[0016] In one embodiment, the hafnium–zirconium oxide layer comprises a stack of interleaved insulator layers, and wherein a bottommost layer of the stack of interleaved insulator layers comprises a third zirconium oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of various elements may be arbitrarily increased or reduced to clearly illustrate the components of the embodiments of the present disclosure.

[0018] Figure 1 is a flowchart of a method of forming a semiconductor device including a MIM capacitor according to some embodiments;

[0019] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 provide cross-sectional views of devices at intermediate stages of manufacturing and processing according to some embodiments of the present disclosure as Figure 1 ;

[0020] Figure 4A illustrate an insulator layer including a metal oxide sandwich structure according to some embodiments; and

[0021] Figure 7A and Figure 7BIllustrates some alternative MIM capacitor configurations according to some embodiments.

[0022] Description of reference numerals:

[0023] 100: Method

[0024] 102: Block

[0025] 104: Block

[0026] 106: Block

[0027] 108: Block

[0028] 110: Block

[0029] 112: Block

[0030] 114: Block

[0031] 116: Block

[0032] 118: Block

[0033] 120: Block

[0034] 122: Block

[0035] 200: Device

[0036] 202: Substrate

[0037] 210: Inter-Layer Dielectric (ILD)

[0038] 220: Carbide layer

[0039] 230: Dielectric layer

[0040] 240: Dielectric layer

[0041] 250: Dielectric layer

[0042] 251: Barrier layer

[0043] 252: First passivation layer

[0044] 253: Lower contact member

[0045] 254: Lower contact member

[0046] 255: Lower contact member

[0047] 256: Dielectric layer

[0048] 258: Dielectric layer

[0049] 260: Metal-Insulator-Metal (MIM) structure

[0050] 262: Bottom conductor plate layer

[0051] 264: Insulator layer

[0052] 264A: Bottom insulator layer

[0053] 264B: Intermediate insulator layer

[0054] 264B-1: Insulator layer

[0055] 264B-2: Insulator layer

[0056] 264C: Top insulator layer

[0057] 266: Intermediate conductor plate layer

[0058] 268: Insulator layer

[0059] 269: Top conductor plate layer

[0060] 270: Second passivation layer

[0061] 281: Barrier layer

[0062] 284: Opening

[0063] 285: Upper contact component

[0064] 286: Opening

[0065] 287: Upper contact component

[0066] 288: Opening

[0067] 289: Upper contact component

[0068] 290: Third passivation layer

[0069] 291: Dielectric layer

[0070] 292: Dielectric layer

[0071] 293: Opening

[0072] 294: Opening

[0073] 295: Opening

[0074] 300: Polyimide (PI) layer

[0075] 302: Opening

[0076] 303: Under-Bump Metallization (UBM)

[0077] 304: Opening

[0078] 305: Cu Pillar

[0079] 306: Opening

[0080] 307: Solder Bump Detailed Implementation Manner

[0081] The following discloses and provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments of the present disclosure. Of course, the above are merely examples and are not intended to limit the embodiments of the present disclosure. For example, when it is described that the first element is formed above the second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0082] Furthermore, relative spatial terms may be used, such as "under", "below", "lower", "above", "higher", etc. These are used to facilitate the description of the relationship between one or some components or parts and another or some other components or parts in the drawings. Relative spatial terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the relative spatial adjectives used therein will also be interpreted according to the turned orientation.

[0083] Furthermore, relative spatial terms may be used, such as "under", "below", "lower", "above", "higher", etc. These are used to facilitate the description of the relationship between one or some components or parts and another or some other components or parts in the drawings. Relative spatial terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the relative spatial adjectives used therein will also be interpreted according to the turned orientation. Additionally, when words such as "about" or "approximate" are used to describe a number or a range of numbers, the meaning of such words is to include numbers whose difference from the described number does not exceed ±10% unless otherwise specified. For example, the phrase "about 5 nanometers" includes a size range from 4.5 nanometers to 5.5 nanometers.

[0084] Metal-insulator-metal (MIM) capacitors have been widely used in functional circuits such as mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random-access memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-chip (SOC) applications, different capacitors of different functional circuits must be integrated on the same chip for different purposes. For example, in a mixed-signal circuit, the capacitor is used as a decoupling capacitor and a high-frequency noise filter. For DRAM and embedded DRAM circuits, the capacitor is used for memory storage, while for RF circuits, the capacitor is used in oscillators and phase-shift networks for coupling and / or bypassing purposes. For microprocessors, the capacitor is used for decoupling. As the name implies, an MIM capacitor includes a sandwich structure with alternating metal layers and insulator layers. Exemplary MIM capacitors include a bottom conductor plate layer, an intermediate conductor plate layer above the bottom conductor plate layer, and a top conductor plate layer above the intermediate conductor plate, where each conductor plate layer is insulated from an adjacent conductor plate layer by a dielectric layer.

[0085] In various embodiments, the MIM capacitor can be fabricated as part of a back-end-of-line (BEOL) process. In some examples, the MIM capacitor can be formed on a semiconductor substrate including a device layer (such as transistors, etc.) and a multi-layer interconnect (MLI) structure that provides interconnections between various microelectronic components within the substrate. In some embodiments, a passivation layer can be formed over the MIM capacitor, and contact vias can be formed to electrically couple a lower contact component to an upper contact component, such as a contact pad, for connection to an external circuit. In certain cases, the dielectric layer of the MIM capacitor may degrade during subsequent processes. For example, a high-pressure anneal (HPA) can be performed after forming the MIM capacitor to improve the performance of front-end-of-line (FEOL) devices. However, such a process may also reduce the reliability of the dielectric layer of the MIM capacitor (e.g., by introducing oxygen vacancies at the dielectric layer interface). Therefore, existing methods are not entirely satisfactory in all respects.

[0086] Embodiments of the present disclosure provide advantages over the prior art. However, it should be understood that other embodiments may provide different advantages, and not all advantages may be discussed herein, and not all embodiments need to have a particular advantage. For example, the embodiments discussed herein include methods and structures for enhancing the reliability of the dielectric layer of a MIM capacitor and thus enhancing the reliability of the MIM capacitor itself. Generally, embodiments of the present disclosure provide a high dielectric constant (high-k) dielectric film stack for use as an insulator layer of a MIM capacitor, which can meet performance and reliability goals while also resisting degradation from subsequent processes (e.g., from subsequent high-pressure annealing processes). In some embodiments, the high dielectric constant (high-k) dielectric film stack includes a metal oxide sandwich structure having the same top layer (metal oxide layer X) and bottom layer (metal oxide layer X), with a stack of interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) in between. In an example, metal oxide layer X may include a zirconia (ZrO 2 ) layer, and metal oxide layer Y may include a hafnia (HfO 2 ) layer. Thus, in some cases, the metal oxide sandwich structure may include ZrO 2 top and bottom layers interposed by a hafnium–zirconium oxide (HZO) layer, and the hafnium–zirconium oxide (HZO) layer includes interleaved HfO 2 and ZrO 2 layers. In at least some cases, the contact structure of the metal oxide layers of the stack of interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) with the bottom layer (metal oxide layer X) of the metal oxide sandwich is the same as the bottom layer (metal oxide layer X). In various embodiments, the thickness of the stack of interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) is at least ten times greater than the thickness of the top layer (metal oxide layer X) or the bottom layer (metal oxide layer X). By providing the disclosed metal oxide sandwich structure, the reliability of the MIM insulator layer (and the MIM capacitor) will be enhanced. Additional details of embodiments of the present disclosure are provided below, and additional benefits and / or other advantages will become apparent to those skilled in the art who benefit from the present disclosure.

[0087] Now referring to Figure 1 , method 100 for forming a semiconductor device including a MIM capacitor according to some embodiments is illustrated. Method 100 will be described in more detail below with reference to Figures 2 - 15 , Figure 4A , Figure 7A and Figure 7B . Figures 2 - 15A cross-sectional view of a semiconductor device 200 at different manufacturing stages is provided. Figure 4A An example of a high dielectric constant (high-k) dielectric film stack including a metal oxide interlayer structure is illustrated, and Figure 7A / Figure 7B Some alternative MIM structure configurations according to embodiments of the present disclosure are shown (e.g., compared to the Figure 7 MIM structure configuration shown). It should be understood that method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in method 100. Additionally, additional process steps can be implemented before, during, and after method 100, and according to various embodiments of method 100, some of the described process steps can be replaced or deleted. It should also be noted that, for the sake of clarity, not all steps are described in detail herein. Additionally, portions of method 100 can be fabricated through well-known complementary metal-oxide-semiconductor (CMOS) technology process flows, and thus only some processes are briefly described here.

[0088] Method 100 begins at block 102, where a substrate including one or more dielectric layers is provided. Referring to Figure 2 , and in an embodiment of block 102, device 200 including substrate 202 is provided. Substrate 202 can be a semiconductor substrate, such as a silicon substrate. Substrate 202 can include various layers, including conductive or insulating layers formed on substrate 202. Substrate 202 can include various doping configurations depending on design requirements known in the art. Substrate 202 can also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 can include compound semiconductors and / or alloy semiconductors. Additionally, in some embodiments, substrate 202 can include an epi-layer, substrate 202 can be strained to enhance performance, substrate 202 can include a silicon-on-insulator (SOI) structure, and / or substrate 202 can have other suitable enhancement components.

[0089] In some embodiments, substrate 202 includes one or more active and / or passive semiconductor devices, such as transistors, diodes, optoelectronic devices, resistors, capacitors, sensors, or other devices. In various examples, a transistor can include source / drain components, a gate structure, gate spacers, contact components, an isolation structure such as a shallow trench isolation (STI) structure, or other suitable components. For example, active and / or passive semiconductor devices formed within substrate 202 can be formed as part of a front-end-of-line (FEOL) process.

[0090] In various examples, the substrate 202 may further include an interconnect structure such as a multi-level interconnect (MLI) structure, which may include a plurality of patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between various microelectronic components formed within the substrate 202. For example, the MLI structure and other layers, components, elements, or devices formed above the MLI structure may be formed as part of a BEOL process. Additionally, and in at least some cases, one or more of the dielectric layers and / or conductive layers of the MLI structure may be formed above the substrate 202. As described above, the interconnect structure may include a plurality of conductive components and a plurality of dielectric components for providing isolation between the conductive components. In some embodiments, the conductive components may include contacts, vias, or metal lines to provide horizontal and vertical interconnections. In some cases, the metal lines may include copper (Cu), aluminum (Al), aluminum-copper (AlCu) alloy, ruthenium (Ru), cobalt (Co), or other suitable metal layers. In some examples, the contacts and / or vias may include Cu, Al, AlCu alloy, Ru, Co, tungsten (W), or other suitable metal layers. In some embodiments, the dielectric components of the MLI structure may include silicon oxide or silicon-oxide-containing materials, where silicon exists in various suitable forms. In some examples, the dielectric components may include low-k dielectric layers (e.g., having a dielectric constant less than SiO 2 2, with a dielectric constant of about 3.9), such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable low-k dielectric materials.

[0091] In some embodiments, and in another embodiment of block 102, an Inter-Layer Dielectric (ILD) 210 is formed over substrate 202. The ILD 210 may include silicon oxide, silicon-oxide-containing materials, or a low-dielectric-constant (low-k) dielectric layer, such as TEOS oxide, undoped silicate glass (USG), or doped silicon oxide such as BPSG, FSG, PSG, BSG, and / or other suitable low-dielectric-constant (low-k) dielectric materials. In various examples, the ILD 210 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. As an example, the ILD 210 may have a thickness of about 200 nm. In other embodiments, the ILD 210 may have a thickness between about 150 nm and about 250 nm. The ILD 210 may be conformally deposited and have a substantially uniform thickness.

[0092] In some examples, and in another embodiment of block 102, a carbide layer 220 is formed over the ILD 210. In some embodiments, the carbide layer 220 may be deposited by CVD, PVD, ALD, or a combination thereof. In some embodiments, the carbide layer 220 may include a silicon carbide (SiC) layer, but other types of carbide materials may also be used. In some examples, the carbide layer 220 may have a thickness of about 55 nm. In other embodiments, the carbide layer 220 may have a thickness between about 45 nm and about 65 nm. In some embodiments, the carbide layer 220 may be conformally deposited and have a substantially uniform thickness.

[0093] Still referring to Figure 2, and in another embodiment of block 102, the device 200 further includes a dielectric layer 230 formed over the carbide layer 220. In some embodiments, the dielectric layer 230 may include silicon oxide or a silicon-oxide-containing material. In some cases, the dielectric layer 230 may include undoped silicate glass (USG). In various examples, the dielectric layer 230 may be deposited by plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), ALD, PVD, or a combination thereof. In some cases, the dielectric layer 230 may have a thickness of about 620 nm. In other embodiments, the dielectric layer 230 may have a thickness between about 575 nm and about 675 nm. In some embodiments, the dielectric layer 230 may be conformally deposited and have a substantially uniform thickness.

[0094] In some embodiments, and in another embodiment of block 102, a dielectric layer 240 may be formed over the dielectric layer 230. In some cases, the dielectric layer 240 may include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 240 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxynitride carbide (SiOCN), silicon nitride (SiN), or a combination thereof. In some embodiments, the dielectric layer 240 may have a thickness of about 50 nm. In other embodiments, the dielectric layer 240 may have a thickness between about 45 nm and about 55 nm. In various examples, the dielectric layer 240 may be deposited by CVD, ALD, PVD, or a combination thereof. In some cases, the dielectric layer 240 may be used as an etch stop layer (ESL).

[0095] Method 100 proceeds to block 104, where a lower contact member is formed. Still referring to Figure 2, and in an embodiment of block 104, dielectric layer 250 can be deposited over dielectric layer 240. In some embodiments, dielectric layer 250 includes silicon oxide or a silicon-oxide-containing material. In some cases, dielectric layer 250 can include undoped silicate glass (USG). In various examples, dielectric layer 250 can be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, or a combination thereof. In some cases, dielectric layer 250 can have a thickness of about 900 nm. In other embodiments, dielectric layer 250 can have a thickness between about 800 nm and about 1000 nm. In some embodiments, dielectric layer 250 can be deposited conformally and have a substantially uniform thickness.

[0096] After depositing dielectric layer 250, and in another embodiment of block 104, dielectric layer 250 can be patterned to form trenches. In various examples, an appropriate combination of optical lithography processes (e.g., such as photoresist deposition, exposure, and development) can be used to pattern dielectric layer 250 to form an etch mask, and the etch mask can be used to perform an etch process to form trenches. In some cases, a hard mask layer (e.g., a nitride-containing layer) can be used as part of the patterning process for dielectric layer 250.

[0097] In some embodiments, and in another embodiment of block 104, lower contact members 253, 254, 255 are formed in the trenches provided by the patterning of dielectric layer 250. Although the lower contact members 253, 254, 255 are disposed below the upper contact members 253, 254, 255 (discussed below), the lower contact members 253, 254, and 255 are sometimes referred to as top metal (TM) contacts because they represent the top metal layer of the MLI structure, as previously discussed. In some embodiments, each of the lower contact members 253, 254, 255 can include a barrier layer 251 and a metal fill layer to complete the lower contact members 253, 254, 255. As an example, forming the lower contact members 253, 254, 255 includes multiple processes. In some embodiments, barrier layer 251 is formed in each trench provided by the patterning of dielectric layer 250, and then a metal fill layer is deposited over barrier layer 251. In some embodiments, barrier layer 251 includes titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the metal fill layer includes a metal or a metal alloy, such as copper, cobalt, nickel, aluminum, tungsten, titanium, or a combination thereof. In some embodiments, the metal fill layer is formed by deposition or electroplating, followed by a chemical mechanical planarization (CMP) process.

[0098] After forming the lower contact components 253, 254, 255, method 100 proceeds to block 106, where a first passivation layer is formed. As Figure 2 shown, and in the embodiment of block 106, a first passivation layer 252 is formed above the device 200 and above the lower contact components 253, 254, 255. In some embodiments, the first passivation layer 252 includes a dielectric layer 256 formed above the lower contact components 253, 254, 255. In some embodiments, the thickness of the dielectric layer 256 is about 75 nm. In other embodiments, the dielectric layer 256 may have a thickness between about 65 nm and about 85 nm. The dielectric layer 256 may include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 256 may include SiCN, SiOC, SiC, SiOCN, SiN, or a combination thereof. In various examples, the dielectric layer 256 may be deposited by CVD, ALD, PVD, or a combination thereof. In some embodiments, the dielectric layer 256 may protect the lower contact components 253, 254, 255 from oxidation.

[0099] The first passivation layer 252 may further include a dielectric layer 258 formed above the dielectric layer 256. In some embodiments, the dielectric layer 258 may include silicon oxide or a silicon-oxide-containing material. In some cases, the dielectric layer 258 may include undoped silicate glass (USG). The dielectric layer 258 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, or a combination thereof. Thus, in some cases, the dielectric layer 258 may be referred to as a plasma-enhanced oxide (PEOX). In some cases, the dielectric layer 258 may have a thickness of about 300 nm. In other embodiments, the dielectric layer 258 may have a thickness between about 250 nm and about 350 nm.

[0100] Then method 100 proceeds to block 108 (which includes sub-blocks 108-1, 108-2, and 108-3), where a metal-insulator-metal (MIM) capacitor structure is formed. As described below, the fabrication of the MIM capacitor structure involves multiple processes, such as the deposition and patterning of multiple conductor plates, and the formation of an insulator between adjacent conductor plates of the MIM capacitor. As Figure 1As shown in the example, sub-blocks 108-1 and 108-2 can be repeated N times, after which the method proceeds to sub-block 108-3 to complete the formation of the MIM capacitor. In some cases, N equals 0, meaning that each of sub-blocks 108-1 and 108-2 is only executed once before proceeding to sub-block 108-3, and meaning that the MIM capacitor will have two conductor plates. In another example, N equals 1, meaning that each of sub-blocks 108-1 and 108-2 is executed twice before proceeding to sub-block 108-3, and meaning that the MIM capacitor will have 3 conductor plates. In yet another example, N equals 2, meaning that each of sub-blocks 108-1 and 108-2 is executed three times before proceeding to sub-block 108-3, and meaning that the MIM capacitor will have 4 conductor plates. Thus, more generally, the number of conductor plates of the MIM capacitor will equal N + 2. In various embodiments, N ranges between 0 and 8. In this way, the number of conductor plates of the MIM capacitor can range between 2 and 10. For the purposes of the discussion below, it will be assumed that N equals 1 and the MIM capacitor has 3 conductor plates, including a bottom conductor plate, an intermediate conductor plate, and a top conductor plate. It should be understood that this example is merely exemplary, and as described above, other values of N and other numbers of conductor plates of the MIM capacitor can be equally used without departing from the scope of the present disclosure.

[0101] Now refer to Figure 3 , and in an embodiment of sub-block 108-1, the patterned bottom conductor plate layer 262 is formed over the dielectric layer 258. For example, the formation of the patterned bottom conductor plate layer 262 can include various processes such as layer deposition, optical lithography, development, and / or etching. In an embodiment, the bottom conductor plate layer 262 can include a metal nitride layer such as titanium nitride (TiN), however, other metals can equally be used. The bottom conductor plate layer 262 can undergo a surface treatment such as sidewall passivation using nitrous oxide (N 2 O) gas. In some embodiments, the thickness of the bottom conductor plate layer 262 is about 40 nm. In other embodiments, the bottom conductor plate layer 262 can have a thickness between about 35 nm and about 45 nm.

[0102] As Figure 4As shown, and in the embodiment of sub-block 108-2, an insulator layer 264 is formed over the device 200, including over the bottom conductor plate layer 262. In one embodiment, the insulator layer 264 is conformally deposited (e.g., by ALD or CVD, for example) and has a generally uniform thickness over the top surface of the device 200 (e.g., approximately the same thickness over the top surface and sidewall surfaces of the bottom conductor plate layer 262). More specifically, according to embodiments of the present disclosure, the insulator layer 264 may be a high-k dielectric film stack including a metal oxide sandwich structure (a three-layer structure or a multi-layer structure), as shown in the example of Figure 4A . The high-k dielectric film stack includes a high-k dielectric material having a dielectric constant (k value) greater than the dielectric constant (k value) of, for example, silicon oxide to provide an increased capacitance value for the MIM capacitor. The metal oxide sandwich structure of the insulator layer 264 may include a bottom insulator layer 264A, an intermediate insulator layer 264B over the bottom insulator layer 264A, and a top insulator layer 264C over the intermediate insulator layer 264B. In various embodiments, the bottom insulator layer 264A and the top insulator layer 264C are composed of the same material. By providing such symmetry between the bottom and top insulator layers 264A, 264C, stress on the MIM capacitor from an applied voltage bias can be balanced or minimized to provide improved reliability. The intermediate insulator layer 264B inserted between the bottom insulator layer 264A and the top insulator layer 264C is composed of a stack of two types of interleaved insulator layers 264B-1 and 264B-2, each insulator layer having a different material composition, where one type of the stack of the two types of interleaved insulator layers (insulator layers 264B-1, 264B-2) is composed of the same material (having the same material composition) as the bottom insulator layer 264A and the top insulator layer 264C. In the example, the bottom insulator layer 264A and the top insulator layer 264C may include a zirconia (ZrO 2 ) layer, and the intermediate insulator layer 264B may include a hafnium-zirconia (HZO) layer, which includes interleaved HfO 2 and ZrO 2 layers. In some embodiments, the insulator layer 264B-1 includes a ZrO 2 layer, such as the bottom and top insulator layers 264A, 264C, and the insulator layer 264B-2 includes a hafnium oxide (HfO 2 ) layer, thus providing the HZO layer. Thus, in some cases, the metal oxide sandwich structure of the insulator layer 264 may include ZrO 2Top and bottom layers. In some embodiments, the bottommost layer of the stack of interleaved insulator layers 264B-1, 264B-2 contacts the bottom insulator layer 264A, which is composed of the same material as the bottom insulator layer 264A (e.g., such as ZrO 2 ) to provide a higher quality insulator material (e.g., crystallinity, reduced oxygen vacancies, etc.). Although some examples of materials for the bottom insulator layer 264A, the intermediate insulator layer 264B, and the top insulator layer 264C have been given, other materials may be used in some cases without departing from the scope of the present disclosure. For example, in some embodiments, the bottom insulator layer 264A and the top insulator layer 264C may optionally include HfO 2 layers. In other embodiments, the intermediate insulator layer 264B may optionally include an alumina (Al 2 O 3 ) layer. In other embodiments, the insulator layer 264 may include a bilayer structure having an HZO layer and a ZrO 2 layer (or an HfO 2 layer) above (as a top capping layer) or below (as a bottom capping layer) the insulator layer 264.

[0103] In some embodiments, each of the bottom insulator layer 264A and the top insulator layer 264C has a thickness of about 0.4 nm. In other embodiments, each of the bottom insulator layer 264A and the top insulator layer 264C has a thickness in the range of about 0.3 - 0.5 nm. In some examples, the middle insulator layer 264B has a thickness in the range of about 5.6 - 6.5 nm. In other examples, the middle insulator layer 264B has a thickness in the range of about 5 - 7 nm. In various embodiments, the thickness of the stack of the interleaved insulator layers 264B-1, 264B-2 (the middle insulator layer 264B) is at least ten times greater than the thickness of the bottom insulator layer 264A or the top insulator layer 264C. In some cases, the thickness of the stack of the interleaved insulator layers 264B-1, 264B-2 (the middle insulator layer 264B) can be about 10 - 18 times greater than the thickness of the bottom insulator layer 264A or the top insulator layer 264C. The number and thickness of each layer of the stack of the interleaved insulator layers 264B-1 and 264B-2 can be selected to achieve a target total thickness, dielectric constant, crystal structure, interface properties, or other properties of the middle insulator layer 264B between the adjacent insulator layers 264B-1, 264B-2. In some examples, the thickness of the insulator layer 264B-1 can be greater than the thickness of the insulator layer 264B-2. In other examples, the thickness of the insulator layer 264B-2 can be greater than the thickness of the insulator layer 264B-1. In still other examples, the thickness of the insulator layer 264B-1 can be substantially the same as the thickness of the insulator layer 264B-2. Generally, the thickness of each of the bottom, middle, and top insulator layers 264A, 264B, 264C can be relatively thin to further provide an increased capacitance value while maintaining a sufficient thickness to avoid potential dielectric breakdown in the MIM capacitor (e.g., when there is a high potential difference between the two capacitor plates, current may leak between the plates, resulting in breakdown).

[0104] Recall that, for the purposes of this example, it is assumed that N equals 1, and the MIM capacitor will have 3 conductor plates. Thus, referring to Figure 1 , method 100 returns to sub-block 108-1 such that each of sub-blocks 108-1 and 108-2 will be executed twice before proceeding to sub-block 108-3. Specifically, referring to Figure 5And in the embodiment of sub-block 108-1, a patterned intermediate conductor plate layer 266 is formed over the device 200, including over the insulator layer 264. The intermediate conductor plate layer 266 can be formed using a process similar to that used to form the bottom conductor plate layer 262, but the pattern of the intermediate conductor plate layer 266 can be different from the pattern of the bottom conductor plate layer 262. In an embodiment, the intermediate conductor plate layer 266 can include a metal nitride layer such as TiN, although other metals can also be used. In some embodiments, the thickness of the intermediate conductor plate layer 266 is about 40 nm. In other embodiments, the intermediate conductor plate layer 266 can have a thickness between about 35 nm and about 45 nm. As Figure 6 shown, and in the embodiment of sub-block 108-2, an insulator layer 268 is formed over the device 200, including over the intermediate conductor plate layer 266. In an embodiment, the insulator layer 268 is conformally deposited (e.g., by ALD or CVD, for example) and has a generally uniform thickness over the top surface of the device 200 (e.g., about the same thickness over the top and sidewall surfaces of the intermediate conductor plate layer 266). In some embodiments, a process similar to the process used to form the insulator layer 264 can be used to form the insulator layer 268. Thus, in various examples, the insulator layer 268 can also include a metal oxide sandwich structure, as Figure 4A shown, including bottom, intermediate, and top insulator layers. Additionally, each of the bottom, intermediate, and top insulator layers of the insulator layer 268 can be formed using materials and thicknesses such as those described above with reference to the insulator layer 264.

[0105] After forming the insulator layer 268, and according to this example where N equals 1, method 100 now proceeds to sub-block 108-3. As Figure 7 shown, and in the embodiment of sub-block 108-3, a patterned top conductor plate layer 269 is formed over the device 200, including over the insulator layer 268. The top conductor plate layer 269 can be formed using a process similar to that used to form the intermediate conductor plate layer 266 or the bottom conductor plate layer 262, but the pattern of the top conductor plate layer 269 can be different from the pattern of the intermediate conductor plate layer 266 or the bottom conductor plate layer 262. In an embodiment, the top conductor plate layer 269 can include a metal nitride layer such as titanium nitride (TiN), although other metals can also be used. In some embodiments, the thickness of the top conductor plate layer 269 is about 40 nm. In other embodiments, the top conductor plate layer 269 can have a thickness between about 35 nm and about 45 nm.

[0106] As Figure 7As shown, and in the embodiment of block 108, the MIM structure 260 has been formed and includes a plurality of metal layers, the plurality of metal layers including a bottom conductor plate layer 262, an intermediate conductor plate layer 266, and a top conductor plate layer 269, which serve as the metal plates of the capacitor. The MIM structure 260 also includes a plurality of insulator layers, including an insulator layer 264 disposed between the bottom conductor plate layer 262 and the intermediate conductor plate layer 266 and an insulator layer 268 disposed between the intermediate conductor plate layer 266 and the top conductor plate. Although Figure 7 the MIM structure 260 in the example of Figure 7A includes three conductor plates (N = 1 at block 108), other configurations are possible. For example, Figure 7B illustrates a MIM structure 260A that includes two conductor plates (N = 0 at block 108), and

[0107] illustrates a MIM structure 260B that includes four conductor plates (N = 2 at block 108). Generally speaking, as described above, the number of conductor plates of the MIM capacitor is equal to N + 2, and N ranges from 0 to 8. Therefore, in various embodiments, the number of conductor plates of the MIM capacitor can range from 2 to 10. Regardless of the exact number of conductor plates in a given MIM capacitor, each conductor plate is separated from an adjacent conductor plate by an insulator layer that includes a metal oxide sandwich structure, as described above. Thus, according to an embodiment of the present disclosure, the MIM structure formed at block 108 will resist degradation from any high-pressure annealing (HPA) process performed after the MIM structure is formed, thereby providing enhanced MIM structure reliability while improving the performance of the FEOL device. Additionally, by way of example, the MIM structures disclosed herein (e.g., such as MIM structures 260, 260A, 260B or MIM structures having other configurations according to the present disclosure) can be used to implement one or more capacitors that can be connected to other microelectronic components (e.g., including active and / or passive devices as described above). Further, in some embodiments, the multi-layer MIM structures illustrated and described herein provide for a tight packaging of the capacitor in the vertical and lateral directions, thereby reducing the amount of lateral space required to implement the capacitor. As a result, the MIM structures disclosed herein can accommodate ultra-high density capacitors. After forming the MIM structure 260, or after forming a MIM structure having a different number of conductor plates and insulator layers (e.g., such as MIM structures 260A, 260B), method 100 proceeds to block 110, where a second passivation layer is formed. As Figure 8As shown, and in the embodiment of block 110, a second passivation layer 270 is formed above the device 200 and above the MIM structure 260. In some embodiments, the second passivation layer 270 may include a dielectric layer such as silicon oxide or a silicon oxide-containing material. In some cases, the second passivation layer 270 may include undoped silicate glass (USG). The second passivation layer 270 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, or a combination thereof. Thus, in some cases, the second passivation layer 270 may be referred to as a plasma enhanced oxide (PEOX). In some cases, the second passivation layer 270 may have a thickness between about 400 nm and 550 nm. As Figure 8 shown, the MIM structure 260 is disposed between the dielectric layer 258 and the second passivation layer 270. In some embodiments, the second passivation layer 270 may include substantially the same material. In some cases, and if the MIM structure 260 is not present, the dielectric layer 258 and the second passivation layer 270 may be combined into a single dielectric layer above the dielectric layer 256. Additionally, in some embodiments, a stress reducing component including a nitrogen-oxygen-nitrogen (NON) multilayer structure, a nitrogen-oxygen (NO) multilayer structure, or an oxygen-nitrogen (ON) multilayer structure may be embedded within the second passivation layer 270 above the MIM structure 260, for example, to prevent cracks (e.g., which may propagate from a nearby passivation layer) and / or other defects from forming within the metal plates of the MIM structure 260 and within the insulator layer of the MIM structure 260.

[0108] After forming the second passivation layer 270, method 100 proceeds to block 112, where an opening is formed to expose the underlying contact component. As Figure 9As shown, and in the embodiment of block 112, openings 284, 286, 288 are formed. Opening 284 can penetrate the second passivation layer 270, insulator layers 268, 264, and the first passivation layer 252 (including dielectric layer 258 and dielectric layer 256) from top to bottom to expose the top surface of the lower contact member 253. Opening 286 can penetrate the second passivation layer 270, a portion of the MIM structure 260 (including insulator layer 268, intermediate conductor plate layer 266, and insulator layer 264), and the first passivation layer 252 from top to bottom to expose the top surface of the lower contact member 254. Opening 288 can penetrate the second passivation layer 270, a portion of the MIM structure 260 (including top conductor plate layer 269, insulator layers 268, 264, and bottom conductor plate layer 262), and the first passivation layer 252 from top to bottom to expose the top surface of the lower contact member 254. In some embodiments, openings 284, 286, 288 can be formed using an etching process (e.g., such as a dry etching process, a wet etching process, or a combination thereof). In various embodiments, the sidewalls of each of openings 284, 286, 288 can expose the sidewalls of the respective layers through which openings 284, 286, 288 pass.

[0109] Then method 100 proceeds to block 114, where upper contact members are formed. Refer to Figure 10 , and in the embodiment of block 114, upper contact members 285, 287, 289 are respectively formed in and above each of openings 284, 286, 288. The upper contact members 285, 287, 289 include contact vias that fill openings 284, 286, 288 and can be referred to as contact vias, metal vias, or metal lines. In some embodiments, to form upper contact members 285, 287, 289, a barrier layer 281 is first conformally deposited over the second passivation layer 270 and into openings 284, 286, 288 using a suitable deposition technique (such as ALD, PVD, or CVD), and then a metal fill layer is deposited over the barrier layer 281 using a suitable deposition technique (e.g., ALD, PVD, or CVD). Then, the deposited barrier layer 281 and metal fill layer are patterned to form upper contact members 285, 287, 289, as shown in the example of Figure 10 . In some cases, contact members 285, 287, 289 can be referred to as contact pads. In some embodiments, the barrier layer 281 and metal fill layer are patterned in a two-stage or multi-stage etching process. In the example of Figure 10 , the portions of upper contact members 285, 287, 289 above the second passivation layer 270 have substantially straight sidewalls. However, in some alternative embodiments, the portions of upper contact members 285, 287, 289 above the second passivation layer 270 can have tapered sidewalls.

[0110] In some embodiments, the upper portions of the upper contact components 285, 287, 289 are part of a redistribution layer (RDL) that includes various metal lines for redistributing bonding pads to different locations, such as from peripheral locations to being evenly distributed on the chip surface. In various examples, the RDL couples a multi-layer interconnect (MLI) structure to the bonding pads for connection to an external circuit. The upper contact components 285, 287, 289 provide electrical contact to the lower contact components 253, 254, 255, respectively. Additionally, as Figure 10 shown in the example of, the upper contact component 287 is electrically coupled to the intermediate conductor plate layer 266 while being electrically isolated from the bottom conductor plate layer 262 and the top conductor plate layer 269. Further, the upper contact component 289 is electrically coupled to the bottom conductor plate layer 262 and the top conductor plate layer 269 while being electrically isolated from the intermediate conductor plate layer 266. Thus, the upper contact component 287 provides electrical contact to the first terminal of the MIM structure 260, and the upper contact component 289 provides electrical contact to the second terminal of the MIM structure 260.

[0111] Method 100 proceeds to block 116, where a third passivation layer is formed. Referring to Figure 11 , and in the embodiment of block 116, a third passivation layer 290 is formed over the device 200, including over the upper contact components 285, 287, 289 and over the second passivation layer 270. In some embodiments, the third passivation layer 290 includes a dielectric layer 291 formed over the upper contact components 285, 287, 289 and over the second passivation layer 270. In some embodiments, the dielectric layer 291 may include silicon oxide or a silicon-oxide-containing material. In some cases, the dielectric layer 291 may include undoped silicate glass (USG). The dielectric layer 291 can be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, or a combination thereof. Thus, in some cases, the dielectric layer 291 can be referred to as a plasma-enhanced oxide (PEOX). In some cases, the dielectric layer 291 can have a thickness of about 1200 nm. In other embodiments, the dielectric layer 291 can have a thickness between about 1000 nm and about 1400 nm. In some examples, the third passivation layer 290 further includes a dielectric layer 292 formed over the dielectric layer 291. In some embodiments, the thickness of the dielectric layer 292 is about 700 nm. In other embodiments, the dielectric layer 292 can have a thickness between about 600 nm and about 800 nm. The dielectric layer 292 can include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 292 can include SiCN, SiOC, SiC, SiOCN, SiN, or a combination thereof. In various examples, the dielectric layer 292 can be deposited by CVD, ALD, PVD, or a combination thereof.

[0112] Method 100 proceeds to block 118, where openings are formed to expose the upper contact members. As Figure 12 shown, and in the embodiment of block 118, openings 293, 294, 295 are formed. In some embodiments, each of the openings 293, 294, 295 may penetrate the dielectric layer 292 and the dielectric layer 291 of the third passivation layer 290 from top to bottom to expose the top surfaces of the upper contact members 285, 287, 289, respectively. In some embodiments, the openings 293, 294, 295 may be formed using an etching process (e.g., such as a dry etching process, a wet etching process, or a combination thereof). In various embodiments, the sidewalls of each of the openings 293, 294, 295 may expose the sidewalls of the respective layers penetrated by the openings 293, 294, 295.

[0113] Method 100 proceeds to block 120, where a patterned polyimide (PI) layer is formed. The formation of the patterned PI layer includes multiple steps, including the deposition of the PI layer and the patterning of the PI layer. Referring to Figure 13 and Figure 14 , in the embodiment of block 120, the PI layer 300 is first conformally deposited over the dielectric layer 292 and into the openings 293, 294, 295 using a suitable deposition technique (e.g., spin coating). In some examples, the PI layer 300 may have a thickness between about 5 μm and about 10 μm. In some embodiments, a baking process may be performed after depositing the PI layer 300. Then, the deposited PI layer 300 may be patterned using a suitable combination of optical lithography processes (e.g., such as photoresist deposition, exposure, and development) to form an etch mask, and the etch mask may be used to perform an etching process to form openings 302, 304, 306 that expose the top surfaces of the upper contact members 285, 287, 289, respectively. In at least some embodiments, the PI layer 300 includes a photosensitive chemical such that the PI layer 300 can be simply patterned by an optical lithography process without a subsequent etching process.

[0114] Method 100 proceeds to block 122, where a bumping process is performed. Referring to Figure 15, in an embodiment of block 122, the bump process includes forming an under-bump metallization (UBM) 303, a copper (Cu) pillar 305 (or Cu bump) above the UBM 303, and a solder bump 307 above the Cu pillar 305. In some embodiments, the UBM 303 provides a low-resistance electrical connection to the RDL within the upper portions of the upper contact components 285, 287, 289. The UBM 303 also hermetically seals and prevents the diffusion of other bump metals into the device 200. In various examples, the UBM 303 includes multiple layers of different metals, such as an adhesion layer (e.g., Ti, Cr, Al, or a combination thereof), a diffusion barrier layer (e.g., CrCu alloy), a solderable layer, and an oxidation barrier layer (e.g., Au). The respective layers of the UBM 303 can be deposited by electroplating, sputtering, evaporation, or other suitable methods. In some embodiments, a Cu seed layer can be deposited before forming the Cu pillar 305, and the Cu pillar 305 can be formed by an electroplating process. Additionally, and in some cases, a diffusion barrier layer (e.g., Ni) can be formed between the Cu pillar 305 and the solder bump 307 to prevent the formation of an intermetallic layer and / or to prevent the formation of microvoids. After forming the Cu pillar 305, an electroplating process can be used to form the solder bump 307 above the Cu pillar 305. One or more patterning processes (e.g., optical lithography and / or etching processes) can be performed to pattern one or more layers deposited during the bump process. In some embodiments, a reflow process can also be performed after solder deposition to form the solder bump 307. For example, the formation of the UBM 303, the Cu pillar 305, and the solder bump 307 provides a contact structure for connection to an external circuit.

[0115] In addition, to improve the performance of the FEOL device, and in some embodiments, high-pressure annealing (HPA) can be performed after forming the MIM structure (block 108), including before, during, or after any of the steps in steps 110 - 122 of method 100. In one example, the HPA can be performed using hydrogen (H 2 ) at a temperature between about 350 °C and 450 °C for a duration between about 1 - 60 minutes, and the pressure is between about 5 - 100 atm. However, according to embodiments of the present disclosure, the metal oxide sandwich structure of the insulator layer of the MIM structure will resist the degradation of such an HPA process, thereby providing enhanced MIM structure reliability while improving the performance of the FEOL device.

[0116] Accordingly, the various embodiments described herein provide several advantages over the prior art. It should be understood that not all advantages may be discussed herein, that all embodiments need not have a particular advantage, and that other embodiments may provide different advantages. As an example, the embodiments discussed herein include methods and structures for enhancing the reliability of the dielectric layer of a MIM capacitor and thus enhancing the reliability of the MIM capacitor itself. Embodiments of the present disclosure provide a high dielectric constant (high-k) dielectric thin film stack for use as an insulator layer of a MIM capacitor, wherein the high dielectric constant dielectric film stack includes a metal oxide sandwich structure having the same top layer (metal oxide layer X) and bottom layer (metal oxide layer X), with interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) therebetween. In an example, metal oxide layer X may include a zirconium oxide (ZrO 2 ) layer, and metal oxide layer Y may include a hafnium oxide (HfO 2 ) layer. Thus, in some cases, the metal oxide sandwich structure may include a ZrO 2 top layer and bottom layer interposed by a hafnium zirconium oxide (HZO) layer, the hafnium zirconium oxide (HZO) layer including interleaved HfO 2 and ZrO 2 layers. In at least some cases, the contact structure of the metal oxide layers of the stack of interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) with the bottom layer (metal oxide layer X) of the metal oxide sandwich is the same as the bottom layer (metal oxide layer X). In various embodiments, the thickness of the stack of interleaved metal oxide layers (metal oxide layer X / metal oxide layer Y) is at least ten times greater than the thickness of the top layer (metal oxide layer X) or the bottom layer (metal oxide layer X). By providing the disclosed metal oxide sandwich structure, the reliability of the MIM insulator layer (and the MIM capacitor) will be enhanced. Additional benefits and / or other advantages will become apparent to those skilled in the art who benefit from the present disclosure.

[0117] Accordingly, one embodiment of the present disclosure describes an apparatus that includes a substrate having one or more semiconductor devices, a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (MIM) capacitor structure formed thereover. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer over the first conductor plate layer, and a second conductor plate layer over the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.

[0118] In another embodiment, a device is discussed that includes a first passivation layer disposed above a substrate and a metal-insulator-metal (MIM) structure formed above the first passivation layer, the substrate having active semiconductor devices. In some embodiments, the MIM structure includes a plurality of conductor plate layers and an insulator layer interposed between adjacent conductor plate layers among the plurality of conductor plate layers. In various examples, the insulator layer includes a multilayer structure, where the multilayer structure includes a first zirconium oxide (ZrO 2 ) layer, a second ZrO 2 layer, and a hafnium-zirconium oxide (HZO) layer interposed between the first and second zirconium oxide layers.

[0119] In yet another embodiment, a method is discussed that includes depositing a first passivation layer above a substrate having one or more semiconductor devices and forming a metal-insulator-metal (MIM) capacitor above the first passivation layer. In some embodiments, forming the MIM capacitor includes forming a patterned first conductor plate above the first passivation layer, depositing an insulator layer above the patterned first conductor plate, and forming a patterned second conductor plate above the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure that has a bottom layer, an intermediate layer above the bottom layer, and a top layer above the intermediate layer. In some cases, the bottom layer and the top layer are composed of the same material.

[0120] The foregoing outlines components of several embodiments so that those skilled in the art of the present disclosure can more readily understand the perspective of the embodiments of the present disclosure. Those skilled in the art of the present disclosure should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art of the present disclosure should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising one or more semiconductor devices; a first passivation layer disposed above the one or more semiconductor devices; as well as A metal-insulator-metal capacitor structure is formed above the first passivation layer, wherein the metal-insulator-metal capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer, and wherein the insulator layer includes a metal oxide sandwich structure.

2. The semiconductor device according to claim 1, wherein Also included is a second passivation layer disposed on the metal-insulator-metal capacitor structure.

3. The semiconductor device according to claim 1, wherein: The metal oxide sandwich structure includes a bottom insulator layer, a middle insulator layer on the bottom insulator layer, and a top insulator layer on the middle insulator layer, and wherein the bottom insulator layer and the top insulator layer are composed of the same material.

4. The semiconductor device according to claim 3, wherein: The middle insulator layer is composed of a stack of two types of staggered insulator layers having different material compositions, and wherein one type of insulator layer in the stack of the two types of staggered insulator layers has a same material composition as the bottom insulator layer and the top insulator layer.

5. The semiconductor device according to claim 3, wherein: A first thickness of the middle insulator layer is at least ten times greater than a second thickness of the bottom insulator layer or the top insulator layer.

6. The semiconductor device according to claim 2, wherein: Also includes: A multi-layer interconnect structure is at least partially disposed within the substrate, wherein the first passivation layer is disposed above the multi-layer interconnect structure.

7. The semiconductor device according to claim 6, wherein: Also includes: A contact component is disposed above the second passivation layer, wherein the contact component is electrically coupled to the multi-layer interconnect structure.

8. A semiconductor device, characterized in that: include: a first passivation layer disposed above a substrate including an active semiconductor device; as well as A metal-insulator-metal structure is formed above the first passivation layer, wherein the metal-insulator-metal structure comprises: a plurality of conductor plate layers; and an insulator layer inserted into an adjacent conductor plate layer of the conductor plate layer; The insulator layer includes a multi-layer structure, and the multi-layer structure includes a first zirconium oxide layer, a second zirconium oxide layer, and a hafnium zirconium oxide layer between the first and second zirconium oxide layers.

9. The semiconductor device according to claim 8, wherein: Also included is a second passivation layer disposed above the metal-insulator-metal structure.

10. The semiconductor device according to claim 8, wherein The hafnium zirconium oxide layer includes a stack of alternating insulator layers, and wherein a bottommost layer of the stack of alternating insulator layers includes a third zirconium oxide layer.

Images