Quantum chip packaging structure and quantum computer

Abstract

The utility model discloses a quantum chip packaging structure and a quantum computer, and belongs to the technical field of integrated circuit packaging. The quantum chip packaging structure comprises a quantum chip and a circuit board electrically connected with the quantum chip, the circuit board comprises a superconductive metal layer and a substrate which are stacked, and a coplanar waveguide signal line is formed on the superconductive metal layer; the coplanar waveguide signal line is used for being connected with the quantum chip and an external annunciator. According to the circuit board, the coplanar waveguide signal line is used for signal transmission, and parameters of the coplanar waveguide signal line can be optimized through simulation, so that the controllability of impedance of the circuit board can be improved, the impedance matching requirement between the circuit board with the coplanar waveguide signal line and the quantum chip can be met, and the reliability of the circuit board is improved. And the risk of impedance mismatch between the quantum chip and the circuit board is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuit packaging, in particular to a quantum chip packaging structure and a quantum computer. Background Art

[0002] In the prior art, the signal fan-out of a quantum chip is realized by bonding the pads of a printed circuit board (PCB) to the signal ports of the quantum chip, and the printed circuit board is connected to an external signal connector to input a control signal to the quantum chip.

[0003] However, in the process of signal transmission between the quantum chip and the external measurement and control equipment by using the printed circuit board, the problem of impedance mismatch will occur, which may affect the performance of the quantum chip.

[0004] Based on this, how to improve the impedance matching of the quantum chip packaging structure is an urgent problem to be solved. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a quantum chip packaging structure and a quantum computer to solve the deficiencies in the prior art, and it can facilitate reducing the crosstalk intensity in the flip-chip quantum chip structure.

[0006] The solution of the example of the present application is implemented through the following content.

[0007] In a first aspect, an example of the present application proposes a quantum chip packaging structure, including a quantum chip and a circuit board electrically connected to the quantum chip;

[0008] The circuit board includes a stacked superconducting metal layer and a substrate, and a coplanar waveguide signal line is formed on the superconducting metal layer;

[0009] The coplanar waveguide signal line is used to connect to the quantum chip and an external signal device respectively.

[0010] According to some examples of the present application, pads are provided at the signal ports of the coplanar waveguide signal line;

[0011] The quantum chip is bonded to the coplanar waveguide signal line through the pads.

[0012] According to some examples of the present application, the packaging structure further includes a carrier board;

[0013] The quantum chip and the circuit board are both disposed on the upper surface of the carrier board;

[0014] The circuit board is located around the quantum chip.

[0015] According to some examples of the present application, the packaging structure further includes a placement table on which the quantum chip is fixed, and a carrying plate that carries the circuit board;

[0016] The circuit board, the carrier plate and the placement table are stacked in a direction perpendicular to the upper surface of the quantum chip;

[0017] The circuit board and the carrier board both have through holes for exposing the quantum chip.

[0018] According to some examples of the present application, the circuit board includes a first sub-substrate and a second sub-substrate, the first sub-substrate having a first coplanar waveguide signal line, the second sub-substrate having a second coplanar waveguide signal line electrically connected to the first coplanar waveguide signal line;

[0019] The quantum chip is located between the first sub-substrate and the second sub-substrate;

[0020] The first coplanar waveguide signal line is used to connect to the quantum chip;

[0021] The second coplanar waveguide signal line is used to connect to the external signal device.

[0022] According to some examples of the present application, the first sub-substrate and the second sub-substrate are detachably connected.

[0023] According to some examples of the present application, the quantum chip is disposed on a transfer substrate;

[0024] A connection conductor is formed on the transfer substrate, and two ends of the connection conductor are respectively connected to the first coplanar waveguide signal line and the second coplanar waveguide signal line.

[0025] According to some examples of the present application, the end of the connecting conductor is an elastic structure.

[0026] According to some examples of the present application, the substrate includes a ceramic substrate.

[0027] In a second aspect, an example of the present application proposes a quantum computer, comprising the above-mentioned quantum chip packaging structure.

[0028] In the quantum chip packaging structure of the aforementioned example of the present application, the circuit board used has a coplanar waveguide signal line formed on a superconducting metal layer. Compared with the printed circuit board in the prior art, the circuit board uses coplanar waveguide signal lines for signal transmission. The parameters of the coplanar waveguide signal lines can be optimized through simulation, which is conducive to improving the controllability of the impedance of the circuit board. The parameters of the coplanar waveguide signal lines can be optimized through simulation, so that the impedance matching requirements between the circuit board with the coplanar waveguide signal lines and the quantum chip are met, thereby reducing the risk of impedance mismatch between the quantum chip and the circuit board. Brief Description of the Drawings

[0029] For a clearer illustration, the accompanying drawings required for the description will be briefly introduced below.

[0030] Figure 1 A top view of the quantum chip packaging structure in an example of the present application;

[0031] Figure 2 A side view of the quantum chip packaging structure in another example of the present application;

[0032] Figure 3 An exploded view of the structure of the quantum chip packaging structure in another example of the present application. Detailed Description of the Embodiments

[0033] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as a limitation of the present application.

[0034] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0035] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0036] In the existing quantum chip packaging structure, a printed circuit board (PCB) is used for signal transmission between the quantum chip and external measurement and control devices. Specifically, the quantum chip is bonded to the printed circuit board, and the external measurement and control device is connected to the port of the printed circuit board. The signal output by the quantum chip is transmitted to the external measurement and control device through the printed circuit board, and the test signal output by the external measurement and control device is input into the quantum chip through the printed circuit board.

[0037] However, the impedance controllability of the printed circuit board is poor. During the process of using the printed circuit board for signal transmission between the quantum chip and external measurement and control devices, there will be a problem of impedance mismatch between the quantum chip and the printed circuit board, which may affect the performance of the quantum chip.

[0038] Based on this, as Figure 1 shown, an embodiment of the present utility model provides a quantum chip packaging structure for illustration. The quantum chip packaging structure includes a quantum chip 100 and a circuit board 200 electrically connected to the quantum chip 100;

[0039] The circuit board 200 includes a stacked superconducting metal layer and a substrate 210, and a coplanar waveguide signal line 220 is formed on the superconducting metal layer;

[0040] The coplanar waveguide signal line 220 is used to be connected to the quantum chip 100 and an external signaler respectively.

[0041] Among them, the coplanar waveguide signal line 220 includes a center strip 221 and ground strips 222 located on both sides of the center strip 221. The center strip 221 of the coplanar waveguide signal line 220 is used to be connected to the quantum chip 100 and an external signaler respectively. The circuit board 200 having the coplanar waveguide signal line 220 and the quantum chip 100 meet the requirements of impedance matching. Based on the impedance of the quantum chip 100, impedance simulation software can be used for simulation to obtain the parameter information of the coplanar waveguide signal line 220 that meets the impedance matching, so as to fabricate the circuit board 200 that matches the quantum chip 100.

[0042] Specifically, in the quantum chip packaging structure, the coplanar waveguide signal line 220 is bonded to the quantum chip 100. The coplanar waveguide signal line 220 also has a connection port for the external measurement and control device to be electrically connected to the coplanar waveguide signal line 220 through the connection port. It should be noted that in this embodiment, only the electrical connection between the quantum chip 100 and the circuit board 200 needs to be ensured, and the relative position relationship between the quantum chip 100 and the circuit board 200 can be set according to actual needs, such as: the quantum chip 100 and the circuit board 200 are arranged on the surface of the same flat plate, the quantum chip 100 and the circuit board 200 are stacked, etc.

[0043] In the quantum chip packaging structure provided by the embodiments of the present application, a coplanar waveguide signal line 220 is formed on a substrate 210. The coplanar waveguide signal line 220 is used to connect to a quantum chip 100 and an external measurement and control device respectively, and is used for signal transmission between the quantum chip 100 and the external measurement and control device. In the present application, a circuit board 200 with a coplanar waveguide signal line 220 is used for chip packaging. Since the parameters of the coplanar waveguide signal line 220 can be optimized through simulation, this is conducive to improving the controllability of the impedance of the circuit board 200. The parameters of the coplanar waveguide signal line 220 can be optimized through simulation, so that the impedance matching requirement is satisfied between the circuit board 200 with the coplanar waveguide signal line 220 and the quantum chip 100, and the risk of impedance mismatch between the quantum chip 100 and the circuit board 200 is reduced.

[0044] In an embodiment of the present application, pads are provided at the signal ports of the coplanar waveguide signal line 220;

[0045] The quantum chip 100 is bonded to the coplanar waveguide signal line 220 through the pads.

[0046] To avoid the problem of non-wetting between the superconducting metal and the existing solder, pads are plated at the ports of the coplanar waveguide signal line 220, so that the quantum chip 100 can be bonded to the coplanar waveguide signal line 220 through the pads, and it is also convenient for the external measurement and control device to be electrically connected to the coplanar waveguide signal line 220 through the pads.

[0047] As Figure 2 shown, in an embodiment of the present application, the quantum chip packaging structure further includes a carrier board 300;

[0048] Both the quantum chip 100 and the circuit board 200 are disposed on the upper surface of the carrier board 300;

[0049] The circuit board 200 is located around the quantum chip 100.

[0050] Wherein, the upper surface of the carrier board 300 may have an adhesive layer, and the adhesive layer is used to fix the quantum chip 100 and the circuit board 200 on the upper surface. In addition, the way of fixing the circuit board 200 on the upper surface of the carrier board 300 further includes: connecting buckles are provided at corresponding positions of the circuit board 200 and the carrier board 300, so that a detachable connection is realized between the circuit board 200 and the carrier board 300.

[0051] Specifically, both the quantum chip 100 and the circuit board 200 are disposed on the same surface of the carrier board 300. The quantum chip 100 can be bonded to the coplanar waveguide signal line 220 (pads) on the circuit board 200 through bonding wires to realize signal transmission.

[0052] As Figure 3As shown, in an embodiment of the present application, the quantum chip packaging structure further includes a placement table 400 on which a quantum chip 100 is fixed, and a carrier board 300 for carrying a circuit board 200;

[0053] Along a direction perpendicular to the upper surface of the quantum chip 100, the circuit board 200, the carrier board 300, and the placement table 400 are stacked;

[0054] Both the circuit board 200 and the carrier board 300 have through holes exposing the quantum chip 100.

[0055] Among them, the quantum chip 100 is fixed on the upper surface of the placement table 400. The placement table 400 may include a placement member 410 with a preset height and a placement flat plate 420. The quantum chip 100 is fixed on the upper surface of the placement member 410. The placement member 410 is located on the upper surface of the placement flat plate 420, and the placement member 410 and the placement flat plate 420 are detachably connected or integrally formed.

[0056] Specifically, along a direction perpendicular to the upper surface of the quantum chip 100, the circuit board 200 and the carrier board 300 are sequentially stacked on the upper surface of the placement table 400. Both the circuit board 200 and the carrier board 300 have through holes exposing the quantum chip 100. The quantum chip 100 can be bonded to the coplanar waveguide signal line 220 (pad) on the circuit board 200 through a bonding wire to achieve signal transmission.

[0057] In an embodiment of the present application, the quantum chip packaging structure may further include a cover plate 500, a partition plate 600, and side plates. The seal formed by the placement table 400, the cover plate 500, and the side plates surrounding the placement table 400 serves as a packaging box. Along a direction perpendicular to the upper surface of the quantum chip 100, the cover plate 500, the partition plate 600, the circuit board 200, the carrier board 300, and the placement table 400 are stacked. The partition plate 600, the circuit board 200, and the carrier board 300 all have through holes exposing the quantum chip 100. Among them, the cover plate 500 may further include a top cover 510 and an observation cover 520; the observation cover 520 includes an observation window that can expose the quantum chip 100 and is used to observe the connection state of the quantum chip 100 inside the packaging box.

[0058] In an embodiment of the present application, the circuit board 200 includes a first sub-substrate and a second sub-substrate. The first sub-substrate has a first coplanar waveguide signal line, and the second sub-substrate has a second coplanar waveguide signal line electrically connected to the first coplanar waveguide signal line;

[0059] The quantum chip 100 is located between the first sub-substrate and the second sub-substrate;

[0060] The first coplanar waveguide signal line is used to connect to the quantum chip 100;

[0061] The second coplanar waveguide signal line is used for connecting to an external signal device.

[0062] The quantum chip 100 is placed on the transfer substrate 210 , and the first sub-substrate, the transfer substrate 210 and the second sub-substrate are stacked in a direction perpendicular to the upper surface of the quantum chip 100 , and the first sub-substrate has a through hole exposing the quantum chip 100 .

[0063] Specifically, the first coplanar waveguide signal line on the first sub-substrate is used to bond and connect with the quantum chip 100, and the second coplanar waveguide signal line on the second sub-substrate is used to connect with an external signal device (i.e., an external measurement and control device) to ensure that the electrical signal is transmitted along the quantum chip 100 to the first coplanar waveguide signal line, then to the second coplanar waveguide signal line, and finally to the external measurement and control device, and to ensure that the electrical signal is transmitted along the external measurement and control device to the second coplanar waveguide signal line, then to the first coplanar waveguide signal line, and finally to the quantum chip 100.

[0064] In one embodiment of the present application, the first sub-substrate and the second sub-substrate are detachably connected.

[0065] Among them, the first sub-baseboard and the second sub-baseboard can be connected through a plug-in structure, and the first sub-baseboard can be detachably placed on the second sub-baseboard by means of the plug-in structure, but it can be understood that the specific implementation of this application is not limited to this, as long as the structure can realize the separation and combination of the first sub-baseboard and the second sub-baseboard, and the structure can ensure that when the two are combined, the first coplanar waveguide signal line and the second coplanar waveguide signal line can be easily electrically connected. In some examples, the plug-in structure includes a column formed on the first sub-baseboard and a limiting hole formed on the second sub-baseboard, and the limiting hole and the column are used in combination.

[0066] In the quantum chip packaging structure provided by the present application, the detachable first and second sub-substrates facilitate the synchronous connection between the second coplanar waveguide signal line on the second sub-substrate and the external circuit (i.e., the external signal device), and the bonding connection between the first coplanar waveguide signal line on the first sub-substrate and the quantum chip 100, and then the first sub-substrate is placed on the second sub-substrate, and the first coplanar waveguide signal line and the second coplanar waveguide signal line are electrically connected. Based on this, this structure helps to improve the installation efficiency of the quantum chip packaging structure.

[0067] In one embodiment of the present application, the quantum chip 100 is disposed on a transfer substrate 210;

[0068] A connection conductor is formed on the transfer substrate 210 , and two ends of the connection conductor are respectively connected to the first coplanar waveguide signal line and the second coplanar waveguide signal line.

[0069] In one embodiment of the present application, the end of the connecting conductor is an elastic structure.

[0070] Wherein, both ends of the connecting conductor are respectively connected to the first coplanar waveguide signal line and the second coplanar waveguide signal line to ensure the electrical signal transmission between the first coplanar waveguide signal line and the second coplanar waveguide signal line. To avoid damaging the first coplanar waveguide signal line and the second coplanar waveguide signal line when the connecting conductor is connected to them and affecting the signal transmission, the end of the connecting conductor is set as an elastic structure, and the elastic structure forms a buffer to ensure a soft contact between the connecting conductor and the first coplanar waveguide signal line and the second coplanar waveguide signal line.

[0071] In one embodiment of the present application, the substrate 210 includes a ceramic substrate 210.

[0072] Wherein, when the substrate 210 meets two conditions, it is a preferred option for the embodiment of the present application. These two conditions include: the transmission loss of the substrate 210 is lower than a preset threshold, and the preset threshold can be selected according to historical experience; the surface of the substrate 210 is suitable for preparing superconducting metal lines.

[0073] Specifically, the ceramic substrate 210 has the characteristic of low loss and is suitable for the preparation of superconducting metal lines, and can be used as the substrate 210 of the circuit board 200 in the quantum chip packaging structure disclosed in the present application. It should be noted that the material of the substrate 210 can be selected according to actual needs, and the ceramic substrate 210 is only a preferred embodiment.

[0074] Based on the same inventive concept, the embodiment of the present application also proposes a quantum computer, including the above-mentioned quantum chip packaging structure. Therefore, it has the same beneficial effects as the above-mentioned quantum chip packaging structure, which will not be elaborated here.

[0075] In the description of this specification, the description referring to terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0076] The above are only the preferred embodiments of the present utility model and do not impose any restrictive effect on the present utility model. Any person skilled in the relevant technical field, without departing from the technical solution of the present utility model, making any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present utility model shall fall within the content of the technical solution of the present utility model and still be within the protection scope of the present utility model.

Claims

1. A quantum chip packaging structure, characterized in that: A circuit board including a quantum chip and being electrically connected to the quantum chip; The circuit board comprises a stacked superconducting metal layer and a substrate, wherein the superconducting metal layer is formed with a coplanar waveguide signal line; The coplanar waveguide signal line is used to connect to the quantum chip and an external signal device respectively.

2. The quantum chip packaging structure according to claim 1, characterized in that: The signal port of the coplanar waveguide signal line is provided with a pad; The quantum chip is bonded to the coplanar waveguide signal line via the pad.

3. The quantum chip packaging structure according to claim 1, characterized in that: The packaging structure also includes a carrier plate; The quantum chip and the circuit board are both arranged on the upper surface of the carrying plate; The circuit board is located around the quantum chip.

4. The quantum chip packaging structure according to claim 1, characterized in that: The packaging structure also includes a placement table on which the quantum chip is fixed, and a carrying plate on which the circuit board is carried; The circuit board, the carrier plate and the placement table are stacked in a direction perpendicular to the upper surface of the quantum chip; The circuit board and the carrier board both have through holes for exposing the quantum chip.

5. The quantum chip packaging structure according to claim 1, characterized in that: The circuit board comprises a first sub-substrate and a second sub-substrate, the first sub-substrate having a first coplanar waveguide signal line, the second sub-substrate having a second coplanar waveguide signal line electrically connected to the first coplanar waveguide signal line; The quantum chip is located between the first sub-substrate and the second sub-substrate; The first coplanar waveguide signal line is used to connect to the quantum chip; The second coplanar waveguide signal line is used to connect to the external signal device.

6. The quantum chip packaging structure according to claim 5, characterized in that: The first sub-baseboard and the second sub-baseboard are detachably connected.

7. The quantum chip packaging structure according to claim 5, characterized in that: The quantum chip is arranged on a transfer substrate; A connection conductor is formed on the transfer substrate, and two ends of the connection conductor are respectively connected to the first coplanar waveguide signal line and the second coplanar waveguide signal line.

8. The quantum chip packaging structure according to claim 7, characterized in that: The end of the connecting conductor is an elastic structure.

9. The quantum chip packaging structure according to claim 1, characterized in that: The substrate includes a ceramic substrate.

10. A quantum computer, characterized in that: Comprising a quantum chip packaging structure as described in any one of claims 1 to 9.

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