Double-pulse test circuit applied to MOS (Metal Oxide Semiconductor) device

Abstract

The utility model provides a double-pulse test circuit applied to an MOS device, which comprises a driving circuit and a test circuit, the driving circuit and the test circuit are arranged on the same test circuit board, one end of the driving circuit is connected with a grid electrode of a second tested MOS tube Q5, and the other end of the driving circuit is connected with an external signal generator for receiving signals; a second to-be-tested MOS tube Q4 is connected in series between the second to-be-tested MOS tube Q5 and the power supply VCC, the source electrode of the second to-be-tested MOS tube Q4 is connected with the drain electrode of the second to-be-tested MOS tube Q5, and the second to-be-tested MOS tube Q4 and the second to-be-tested MOS tube Q5 are arranged on the same to-be-tested circuit board; one end of the test circuit is connected with a power supply VCC, the other end of the test circuit is grounded, and the test circuit is connected with the second tested MOS tube Q5 in parallel; in the testing process, through a mode of connecting the PCBs, namely a mode of connecting the testing circuit board and the tested circuit board, a loop between a driving signal and the tested MOS tube and a loop between the driving signal and the tested circuit are reduced, and generated interference oscillation is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS device testing, in particular to a double pulse testing circuit applied to MOS devices. Background Art

[0002] The basic principle of MOSFET is to use a structure composed of a metal gate, oxide and semiconductor to control the resistance of the conductor. When voltage is applied to the metal gate, an electric field is formed in the oxide layer, which can affect the charge distribution in the semiconductor material below the oxide layer, thereby controlling the conductive properties of the channel. In addition, MOSFET has significant advantages in high-frequency applications, such as simple driving circuit, low driving power, fast switching speed, good high-frequency characteristics, etc., so it is widely used in chargers, adapters, motor control, PC power supply, communication power supply, new energy power generation, UPS, charging piles and other occasions.

[0003] In normal use, we basically learn about the various performance parameters of power devices through chip manuals. However, the measurement environment of the parameters in the manuals is under ideal conditions, which are more or less different from actual use. Therefore, it is necessary to test through MOS devices to obtain the parameters of the devices under real working conditions. In double pulse testing, devices with different packages are generally connected to the test circuit by replacing fixtures, welding wires, etc. The use of fixtures will cause oscillations in the test waveform. The welding connection of a single device is not only time-consuming, but the test waveform will often oscillate due to reasons such as too long welding wires. Utility Model Content

[0004] In view of the deficiencies existing in the prior art, the utility model provides a double pulse test circuit applied to MOS devices, which solves the above problems existing in the prior art.

[0005] According to an embodiment of the utility model, a double pulse test circuit applied to a MOS device includes:

[0006] A driving circuit and a test circuit, wherein the driving circuit and the test circuit are arranged on the same test circuit board, one end of the driving circuit is connected to an external signal generator for receiving a signal, and the other end of the driving circuit is used to connect to a circuit board under test, and a dual-mode pulse test circuit is formed in combination with the test circuit; wherein the circuit board under test comprises: a first MOS tube under test Q4, a second MOS tube under test Q5 and a circuit board, the first MOS tube under test Q4 and the second MOS tube under test Q5 are integrated on the circuit board, and one end of the driving circuit is connected to a gate of the second MOS tube under test Q5;

[0007] The test circuit includes an energy consumption circuit. One end of the energy consumption circuit is connected to the power supply VCC, the other end is grounded, and the energy consumption circuit is connected in parallel with the second MOS transistor Q5 to be measured.

[0008] Preferably, the drive circuit includes:

[0009] A radio frequency coaxial connector RF1, a chip U1, a first resistor R1, a second resistor R2, a first capacitor C1, and a fast recovery diode D1. The input end of the radio frequency coaxial connector RF1 is connected to an external signal generator. The pin 1 of the radio frequency coaxial connector RF1 is connected to the IN+ port of the chip U1. The pins 2, 3, and 4 of the radio frequency coaxial connector RF1 are all grounded. The VDD port of the chip U1 is connected to the power supply. The OUT_SRC port and OUT_SNK port of the chip U1 are respectively connected to one end of the first resistor R1 and one end of the second resistor R2. The other end of the first resistor R1 and the other end of the second resistor R2 are both connected to one end of the fast recovery diode D1. The other end of the fast recovery diode D1 is connected to the gate of the second MOS transistor Q5 to be measured;

[0010] One end of the first capacitor C1 is connected to the power supply, and the other end of the first capacitor C1 is grounded.

[0011] Preferably, the drive circuit further includes:

[0012] An NPN transistor Q3. The base of the NPN transistor Q3 is connected to the first resistor R1. The emitter of the NPN transistor Q3 is grounded. The collector of the NPN transistor Q3 is connected to the gate of the second MOS transistor Q5 to be measured.

[0013] Preferably, the drive circuit further includes:

[0014] A third resistor R3. One end of the third resistor R3 is connected to the gate of the second MOS transistor Q5 to be measured, and the other end of the third resistor R3 is grounded;

[0015] A second capacitor C2. One end of the second capacitor C2 is connected to the gate of the second MOS transistor Q5 to be measured, and the other end of the second capacitor C2 is grounded.

[0016] Preferably, the energy consumption circuit includes:

[0017] A third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. One end of the third capacitor C3 is connected to the power supply VCC, the other end of the third capacitor C3 is grounded, and the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are all connected in parallel with the third capacitor C3.

[0018] Preferably, the energy consumption circuit further includes:

[0019] The fourth resistor R4, the push-button switch SW1, and the fifth resistor R5 are connected in series in sequence, and the fourth resistor R4, the push-button switch SW1, and the fifth resistor R5 are connected in parallel with the third capacitor C3.

[0020] Preferably, the source of the second MOS transistor Q5 to be measured is grounded, and the source and gate of the first MOS transistor Q4 to be measured are connected;

[0021] A second MOS transistor Q4 to be measured is connected in series between the second MOS transistor Q5 to be measured and the power supply VCC, and the source of the second MOS transistor Q4 to be measured is connected to the drain of the second MOS transistor Q5 to be measured.

[0022] Preferably, the resistance values of the first resistor R1 and the second resistor R2 are 0 - 5.1 Ω, the resistance value of the third resistor R3 is 10 - 20 KΩ, and the resistance values of the fourth resistor R4 and the fifth resistor R5 are 1 - 3 Ω; the power supply is a 10V - 15V power supply.

[0023] Preferably, the capacitance of the first capacitor C1 is 10 - 25 uF, the capacitance of the second capacitor C2 is 1 - 15 nF, and the capacitances of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are 1 - 5 uF, and the withstand voltage is greater than or equal to 150V.

[0024] Preferably, the test circuit further includes:

[0025] An adjustable inductor L, and both ends of the adjustable inductor L are respectively connected to the source and drain of the first MOS transistor Q4 to be measured.

[0026] Compared with the prior art, the present utility model has the following beneficial effects: During the test process, by connecting the PCB to the PCB board, that is, the connection method of the test circuit board and the circuit board to be measured, the loop between the driving signal, the MOS transistor to be measured, and the circuit to be measured is reduced, and the generated interference oscillation is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic circuit diagram of an embodiment of the present utility model;

[0028] Figure 2 is a 3D view of a part of the circuit board of another embodiment of the present utility model;

[0029] Figure 3 is a 3D view of another part of the circuit board of another embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The technical solutions in the present utility model will be further described below with reference to the accompanying drawings and embodiments.

[0031] As Figure 1As shown in the figure, an embodiment of the present utility model provides a double-pulse test circuit applied to MOS devices, including:

[0032] A drive circuit and a test circuit. The drive circuit and the test circuit are arranged on the same test circuit board. One end of the drive circuit is connected to an external signal generator for receiving signals, and the other end of the drive circuit is used to connect to the circuit board under test, and together with the test circuit, a dual-mode pulse test circuit is formed; wherein, the circuit board under test includes: a first MOS transistor Q4 under test, a second MOS transistor Q5 under test, and a circuit board. The first MOS transistor Q4 under test and the second MOS transistor Q5 under test are integrated on the circuit board, and one end of the drive circuit is connected to the gate of the second MOS transistor Q5 under test;

[0033] The test circuit includes an energy consumption circuit. One end of the energy consumption circuit is connected to the power supply VCC, the other end of the energy consumption circuit is grounded, and the energy consumption circuit is connected in parallel with the second MOS transistor Q5 under test;

[0034] The working principle of the above technical solution: There is a drive circuit and a test circuit on the test circuit board. The drive circuit receives the signal generated by the external signal generator and outputs the signal to the gate of the second MOS transistor Q5 under test, and the test circuit completes the test; wherein, the first MOS transistor Q4 under test and the second MOS transistor Q5 under test are integrated on the circuit board. During the test process, the double-pulse test is continuously carried out by replacing the circuit board under test;

[0035] The beneficial effect of the above technical solution: Through the above technical solution, during the test process, by connecting the PCB to the PCB board, that is, the connection method of the test circuit board and the circuit board under test, the loop between the drive signal and the MOS transistor under test and the circuit under test is reduced, and the interference oscillation generated is reduced.

[0036] In one embodiment, the drive circuit includes:

[0037] A radio frequency coaxial connector RF1, a chip U1, a first resistor R1, a second resistor R2, a first capacitor C1, and a fast recovery diode D1. The input end of the radio frequency coaxial connector RF1 is connected to an external signal generator. The pin 1 of the radio frequency coaxial connector RF1 is connected to the IN+ port of the chip U1. The pins 2, 3, and 4 of the radio frequency coaxial connector RF1 are all grounded. The VDD port of the chip U1 is connected to the power supply. The OUT_SRC port and the OUT_SNK port of the chip U1 are respectively connected to one end of the first resistor R1 and one end of the second resistor R2; the other end of the first resistor R1 and the other end of the second resistor R2 are both connected to one end of the fast recovery diode D1, and the other end of the fast recovery diode D1 is connected to the gate of the second MOS transistor Q5 under test;

[0038] One end of the first capacitor C1 is connected to the power supply, and the other end of the first capacitor C1 is grounded;

[0039] Working principle and beneficial effects of the above technical solution: The input end of the RF coaxial connector RF1 is connected to a signal generator, and the signal is input to the IN+ port of the chip U1 to control the output. The VDD port of the chip U1 is connected to a power supply. The voltage of the power supply not only ensures the normal operation of the chip U1, but also makes the output voltage of the OUT port of the chip U1 be 10V, so as to simulate the voltage of the MOS transistor device under test during actual operation. The output capacity of 9A ensures the stable opening of the gate of the second MOS transistor Q5 under test; the output signal supplies the gate operating voltage of the second MOS transistor Q5 through the fast recovery diode D1; among them, the model of the chip U1 is 1END7511B.

[0040] In one embodiment, the drive circuit further includes:

[0041] An NPN transistor Q3, the base of the NPN transistor Q3 is connected to the first resistor R1, the emitter of the NPN transistor Q3 is grounded, and the collector of the NPN transistor Q3 is connected to the gate of the second MOS transistor Q5 under test;

[0042] Working principle and beneficial effects of the above technical solution: The first resistor R1 is connected to the base of the NPN transistor Q3, so as to output high and low level signals to the output NPN transistor Q3 to control the operation of the NPN transistor Q3. When the output is low level, it conducts and accelerates the turn-off.

[0043] In one embodiment, the drive circuit further includes:

[0044] A third resistor R3, one end of the third resistor R3 is connected to the gate of the second MOS transistor Q5 under test, and the other end of the third resistor R3 is grounded;

[0045] A second capacitor C2, one end of the second capacitor C2 is connected to the gate of the second MOS transistor Q5 under test, and the other end of the second capacitor C2 is grounded;

[0046] Working principle and beneficial effects of the above technical solution: The third resistor R3 is mainly provided to prevent surge current from damaging the device. The function of the provided second capacitor C2 is to optimize the waveform, reduce the gate spike, and will also extend the turn-on time to a certain extent.

[0047] In one embodiment, the energy consumption circuit includes:

[0048] A third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6. One end of the third capacitor C3 is connected to the power supply VCC, the other end of the third capacitor C3 is grounded, and the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are all connected in parallel with the third capacitor C3;

[0049] The test circuit further includes:

[0050] A fourth resistor R4, a push-button switch SW1, and a fifth resistor R5, where the fourth resistor R4, the push-button switch SW1, and the fifth resistor R5 are connected in series in sequence, and the fourth resistor R4, the push-button switch SW1, and the fifth resistor R5 are connected in parallel with a third capacitor C3;

[0051] The working principle and beneficial effects of the above technical solution: The provided third capacitor C3, fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6 function to reduce the bus voltage oscillation and stabilize the voltage; the push-button switch SW1, as well as the fourth resistor R4 and the fifth resistor R5, are used to consume the energy of the third capacitor C3, fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6 after closing after the test is completed, increasing the safety of the test.

[0052] In one embodiment, the test circuit further includes:

[0053] A tunable inductor L, with both ends of the tunable inductor L connected to the source and drain of the first MOS transistor Q4 to be measured respectively;

[0054] The working principle and beneficial effects of the above technical solution: The provided tunable inductor L is connected in parallel with Q4 mainly to test the FRD characteristics of the upper transistor (the first MOS transistor Q4 to be measured), and the lower transistor (the second MOS transistor Q5 to be measured) is tested for its double-pulse dynamic characteristics.

[0055] In one embodiment, the resistance values of the first resistor R1 and the second resistor R2 are 0 - 5.1 Ω, the resistance value of the third resistor R3 is 10 - 20 KΩ, the resistance values of the fourth resistor R4 and the fifth resistor R5 are 1 - 3 Ω, and they have strong overcurrent capacity; the power supply is a 10V - 15V power supply.

[0056] In one embodiment, the capacitance of the first capacitor C1 is 10 - 25 uF, the capacitance of the second capacitor C2 is 1 - 15 nF, and the capacitances of the third capacitor C3, fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6 are 1 - 5 uF, and their withstand voltages are greater than or equal to 150V.

[0057] As Figure 2 and Figure 3 shown, a plurality of pads are provided on both the test circuit board and the circuit board to be measured;

[0058] Working principle and beneficial effects of the above technical solution: Since the test circuit board and the circuit board under test are designed, grooving treatment is performed on both the test circuit board and the circuit board under test. The groove of the circuit board under test is slightly smaller than that of the test circuit board to facilitate soldering. Among them, the 1st and 2nd pads are welding positions reserved for the adjustable inductor L, and the 1st and 2nd are also connection positions with the 5th and 7th pads of the device board; the 3rd and 4th pads are current probe positions reserved for measuring Id in the double pulse, and the 4th is also the connection position with the 8th pad; the 9th and 10th pads are connected to transmit the gate control signal of the MOS transistor under test; the 11th and 12th pads are connected; the 5th and 6th pads are positions reserved for measuring Irrm of the FRD of the upper transistor; the design of multiple pads can greatly facilitate the capture of current and voltage, and the reasonable layout also reduces the loop of the original test board and reduces interference; the design of the circuit board under test greatly facilitates the measurement of surface-mounted devices. At the same time, when testing devices with different packages (the packages of MOS transistors on different circuit boards under test are different), only the circuit board under test needs to be changed. Multiple circuit boards under test with different packages can be designed and combined with the test circuit board; multiple pads are reserved to facilitate the capture of current and voltage probes. The design of the general test board can also expand the test range and improve the test efficiency.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A double pulse test circuit for MOS devices, characterized in that: include: A driving circuit and a test circuit, wherein the driving circuit and the test circuit are arranged on the same test circuit board, one end of the driving circuit is connected to an external signal generator for receiving a signal, and the other end of the driving circuit is used to connect to a circuit board under test, and a dual-mode pulse test circuit is formed in combination with the test circuit; wherein the circuit board under test comprises: a first MOS tube under test Q4, a second MOS tube under test Q5 and a circuit board, the first MOS tube under test Q4 and the second MOS tube under test Q5 are integrated on the circuit board, and one end of the driving circuit is connected to a gate of the second MOS tube under test Q5; The test circuit comprises an energy consumption circuit, one end of the energy consumption circuit is connected to a power supply VCC, the other end of the energy consumption circuit is grounded, and the energy consumption circuit is connected in parallel with the second MOS tube Q5 to be tested.

2. A double pulse test circuit for MOS devices as claimed in claim 1, characterized in that: The drive circuit includes: RF coaxial connector RF1, chip U1, first resistor R1, second resistor R2, first capacitor C1 and fast recovery diode D1, the input end of RF coaxial connector RF1 is connected to the external signal generator, pin 1 of RF coaxial connector RF1 is connected to IN+ port of chip U1, pins 2, 3 and 4 of RF coaxial connector RF1 are all grounded, VDD port of chip U1 is connected to power supply, OUT_SRC port and OUT_SNK port of chip U1 are respectively connected to one end of the first resistor R1 and one end of the second resistor R2; the other end of the first resistor R1 and the other end of the second resistor R2 are both connected to one end of the fast recovery diode D1, and the other end of the fast recovery diode D1 is connected to the gate of the second MOS tube Q5 under test; One end of the first capacitor C1 is connected to the power supply, and the other end of the first capacitor C1 is grounded.

3. A double pulse test circuit for MOS devices as claimed in claim 2, characterized in that: The drive circuit also includes: NPN transistor Q3, the base of the NPN transistor Q3 is connected to the first resistor R1, the emitter of the NPN transistor Q3 is grounded, and the collector of the NPN transistor Q3 is connected to the gate of the second MOS transistor Q5 to be tested.

4. A double pulse test circuit for MOS devices as claimed in claim 2, characterized in that: The drive circuit also includes: A third resistor R3, one end of the third resistor R3 is connected to the gate of the second MOS transistor Q5 under test, and the other end of the third resistor R3 is grounded; A second capacitor C2, one end of the second capacitor C2 is connected to the gate of the second MOS transistor Q5 under test, and the other end of the second capacitor C2 is grounded.

5. A double pulse test circuit for MOS devices as claimed in claim 1, characterized in that: Energy consumption circuits include: The third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6, one end of the third capacitor C3 is connected to the power supply VCC, the other end of the third capacitor C3 is grounded, and the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are respectively arranged in parallel with the third capacitor C3.

6. A double pulse test circuit for MOS devices as claimed in claim 5, characterized in that: The energy consumption circuit also includes: The fourth resistor R4, the key switch SW1 and the fifth resistor R5 are connected in series in sequence, and the fourth resistor R4, the key switch SW1 and the fifth resistor R5 are connected in parallel with the third capacitor C3.

7. A double pulse test circuit for MOS devices as claimed in claim 1, characterized in that: The source of the second MOS transistor Q5 under test is grounded, and the source and gate of the first MOS transistor Q4 under test are connected; A second MOS transistor Q4 is connected in series between the second MOS transistor Q5 and the power source VCC, and a source of the second MOS transistor Q4 is connected to a drain of the second MOS transistor Q5.

8. A double pulse test circuit for MOS devices as claimed in claim 6, characterized in that: The resistance of the first resistor R1 and the second resistor R2 is 0-5.1Ω, the resistance of the third resistor R3 is 10-20KΩ, the resistance of the fourth resistor R4 and the fifth resistor R5 is 1-3Ω; the power supply is a 10V-15V power supply.

9. A double pulse test circuit for MOS devices as claimed in claim 5, characterized in that: The capacitance of the first capacitor C1 is 10-25uF, the capacitance of the second capacitor C2 is 1-15nF, the capacitance of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 is 1-5uF, and the withstand voltage is greater than or equal to 150V.

10. A double pulse test circuit for MOS devices according to any one of claims 1 to 9, characterized in that: The test circuit also includes: The adjustable inductor L has two ends connected to the source and the drain of the first MOS tube Q4 under test respectively.

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