Integrated circuit, radar chip, radar sensor and electronic equipment

Abstract

The embodiment of the utility model relates to the technical field of integrated circuits, and discloses an integrated circuit, a radar chip, a radar sensor and electronic equipment. The integrated circuit comprises a power management circuit and a signal processor connected with the power management circuit, the signal processor outputs an interrupt signal to the power management circuit; the power management circuit responds to an interrupt signal and switches the integrated circuit from a low power consumption mode to a normal working mode; wherein in the low power consumption mode, the power management circuit controls a circuit in the integrated circuit to periodically switch between a wake-up state and a sleep state. And the power consumption of the integrated circuit is reduced under the condition that the performance is not influenced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular, to an integrated circuit, a radar chip, a radar sensor, and an electronic device. Background Art

[0002] Power consumption is an important performance of an integrated circuit (IC), especially in some environments where power supply and other conditions are limited, the control of power consumption is particularly important.

[0003] However, with the expansion of sensors in different application scenarios, the power consumption of the involved integrated circuits is still not satisfactory. Utility Model Content

[0004] The embodiments of the present application provide an integrated circuit, a radar chip, a radar sensor, and an electronic device, which are at least beneficial to reducing the power consumption of the integrated circuit without affecting the performance.

[0005] According to some embodiments of the present application, in the first aspect of the embodiments of the present application, an integrated circuit is provided, which includes: a power management circuit, and a signal processor connected to the power management circuit; the signal processor outputs an interrupt signal to the power management circuit; the power management circuit responds to the interrupt signal and switches the integrated circuit from the low-power mode to the normal operating mode; wherein, in the low-power mode, the power management circuit controls the circuits in the integrated circuit to periodically switch between the wake-up state and the sleep state.

[0006] In the second aspect of the embodiments of the present application, a radar chip is provided, which includes: the integrated circuit as described above.

[0007] In the third aspect of the embodiments of the present application, a radar sensor is provided, which includes: a carrier; the integrated circuit as described above, disposed on the carrier; an antenna, disposed on the carrier, or the antenna and the integrated circuit are integrated into an integrated device and disposed on the carrier; wherein, the integrated circuit is connected to the antenna and is used to transmit radio frequency transmission signals and / or receive radio frequency reception signals.

[0008] In the fourth aspect of the embodiments of the present application, an electronic device is provided, which includes: a device body; the radar sensor as described above, disposed on the device body; wherein, the radar sensor is used to provide measurement information. The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0009] A power management circuit is provided in the integrated circuit, which can periodically switch the circuits in the integrated circuit between the wake-up state and the sleep state in the low-power mode. It is compatible with both the low-power mode and the working mode. While reducing power consumption, it provides a flexible multi-mode switching method. Since the present application adopts the method of establishing a connection between the power management circuit and the signal processor, it supports the function that the signal processor can trigger the power management circuit to perform mode switching when obtaining measurement information. Thus, the dependence on the main control circuit and the memory is reduced. Compared with the method of realizing software wake-up through the main control circuit and the memory, it not only shortens the time spent on software scheduling, but also reduces the additional power consumption brought by the hardware devices for running the scheduling, further reducing the overall power consumption of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0011] Figure 1 is a schematic diagram of the working process of the existing integrated circuit provided by the present application;

[0012] Figure 2 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 1 ;

[0013] Figure 3 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 2 ;

[0014] Figure 4 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 3 ;

[0015] Figure 5 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 4 ;

[0016] Figure 6 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 5 ;

[0017] Figure 7 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 6 ;

[0018] Figure 8 is a schematic structural diagram of the integrated circuit provided by the embodiment of the present application Figure 7 ;

[0019] Figure 9It is a schematic diagram showing the variation of power consumption over time during the application of the integrated circuit provided in the embodiments of the present application. Detailed implementation manners

[0020] As can be seen from the background art, the power consumption of current integrated circuits is still not satisfactory. Taking a radar sensor as an example, in an Advanced Driving Assistance System (ADAS), the radar sensor provides measurement information around the vehicle, such as at least one of distance, speed, and angle. This enables the radar sensor to always be in the powered-on working mode during the operation of the ADAS system. With the in-depth development of vehicle intelligence, the radar sensor can also provide measurement information for decision-making processing for functions such as in-cabin detection and automatic door opening. However, in new applications, the radar sensor needs to have lower power consumption, which is not consistent with the detection requirements of the ADAS system. In some examples, the radar sensor uses a software control method to adjust the power-on / off of some circuits in the radar sensor at a relatively small improvement cost, thus reducing the overall power consumption of the radar sensor. However, this method still has at least one problem such as the low-power index can still be optimized and the flexibility of the controllable hardware circuit is poor.

[0021] After analysis, it is found that the reasons for the above problems are at least: the hardware design of current integrated circuits does not consider low-power requirements, which makes the coupling degree of the hardware circuits between different functions large, especially in the digital circuit part. This causes the processor and memory in the integrated circuit to need to remain powered even in the sleep state because software needs to switch between wake-up and sleep. Therefore, the power consumption of the integrated circuit is still high.

[0022] Taking the integrated circuit in a Frequency Modulated Continuous Wave (FMCW) Radar system as an example, in low-speed application scenarios (such as target detection, kick-to-open tailgate, Child Presence Detection (CPD), etc.), its working principle is: in each radar transceiver cycle, a detection signal frame is transmitted and the echo signal reflected by the target is received; a series of digital signal processing is performed on the echo signal, such as Analog to Digital Converter (ADC), Fast Fourier Transform (FFT), Vector Signal Analysis (VSA), Constant False-Alarm Rate (CFAR), Direction Of Arrival (DOA), etc., to obtain measurement information. Among them, such asFigure 1 As shown, within one radar transceiver cycle, the duration of T0 represents the time for the transceiver circuit in the integrated circuit to transmit a detection signal and receive an echo; the duration of T1 represents a series of digital signal processing performed by the signal processor in the integrated circuit on the received echo. Since the transceiver circuit transmits the detection signal and receives the echo simultaneously, T0 and T1 partially overlap. Usually, to ensure that the transceiver circuit of the radar returns to the initial frequency of the next detection signal, after the digital signal processing is completed, the transceiver circuit, signal processor, etc. need to enter the idle state (IDLE). Among them, the idle state is not less than the duration required for the above recovery operation.

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are presented to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0024] The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present application. Each embodiment can be combined and cross-referenced with each other on the premise of not being contradictory.

[0025] One aspect of the embodiments of the present application provides an integrated circuit, especially an integrated circuit capable of transmitting and receiving radio frequency signals, which has a switchable low-power mode and working mode. For example, the integrated circuit is applied to a radar system, such as a millimeter-wave radar system, a frequency-modulated continuous-wave radar system, etc. Another example is that the integrated circuit is applied to a mobile communication system, such as a 5G communication system, a 6G communication system, etc.

[0026] Taking an integrated circuit in a radar system as an example, the integrated circuit includes a transceiver circuit, a signal processor, a main control circuit, etc. Among them, the transceiver circuit is used to send detection signals, receive echo signals reflected by an object, and convert the echo signals into digital sequences and output them; the signal processor is coupled to the transceiver circuit to perform signal processing on at least one digital sequence, including but not limited to interference cancellation, FFT, DOA, CFAR, etc. The signal processor includes a dedicated digital processing circuit for logical calculation, as well as registers, memory, etc. The main control circuit is coupled to the transceiver circuit, the signal processor, etc., and is not only used to configure the transceiver circuit, but also post-process the measurement information output by the signal processor, such as FFT calculation, DOA calculation, super-resolution calculation, vital sign calculation, etc. Among them, the measurement information includes but is not limited to: energy data of at least one dimension in distance / speed / angle. For example, to adapt to different application requirements, the measurement information output by the signal processor to the main control circuit includes energy data in the range-Doppler dimension, or energy data in the range-angle dimension, etc. The main control circuit includes: a memory such as a memory / register that is easy to read and write at high speed, a device for logical calculation such as a microcontroller unit (MCU) / central processing unit (CPU), and an IO interface such as a universal serial bus (USB) / controller area network bus (CAN). The main control circuit and / or the signal processor can also be data-connected to a first memory. The first memory includes a memory such as a non-volatile memory that is slow to read and write. For example, the first memory stores data that can be read and written by the main control circuit and the signal processor together. Another example is that the first memory stores data that can be repeatedly read and written by the main control circuit and / or the signal processor.

[0027] The integrated circuit further includes a circuit mainly for performing mode switching: a power management circuit, which is connected to the signal processor at least through a signal line, and at least uses the interrupt signal IRQ_1 (Interrupt Request) output by the signal processor to switch the integrated circuit from the low-power mode to the normal operating mode. In some embodiments, as Figure 2 shown, the integrated circuit includes a power management circuit 100 (also known as the Always On circuit) and a signal processor 200. Among them, the power management circuit 100 can operate in a low-power sleep state. The signal processor 200 is connected to the power management circuit 100 to trigger the power management circuit 100 to switch modes. The power management circuit 100 can be composed of a hardware state machine circuit such as a configuration register, a trigger, a controller, etc.

[0028] The signal processor 200 selectively outputs an interrupt signal IRQ_1 by comparing the differences between at least two measurement information obtained successively. When the interrupt signal IRQ_1 is generated, the power management circuit 100 wakes up each circuit in the sleep state in the integrated circuit in response to the interrupt signal IRQ_1 and restores it to the operating state. In this way, the integrated circuit switches from the low-power mode to the normal operating mode. Examples of the differences between at least two measurement information include: whether there is a sudden increase in the peak value of the energy data in each unit (bin) within the same dimension; or a significant increase in the energy data corresponding to a short distance within the same dimension, etc.

[0029] It should be noted that the difference between at least two measurement information reflects the need for the integrated circuit to perform detection in the operating mode to meet the requirements of real-time response of the upper-layer application. For example, in a radar system including an integrated circuit, considering requirements such as kick motion detection, when the signal processor 200 detects a change in the measurement information, it issues an interrupt signal IRQ_1, so that the power management circuit 100 wakes up each circuit in the sleep state and aborts the timing of the wake-up state in the low-power mode. In this way, the integrated circuit switches to the operating mode, and the main control circuit masters the control rhythm of the transceiver circuit, signal processing circuit, etc. In this way, it can more accurately detect whether there is a kick motion and report it to the kick application program through the radar system to control the opening or closing of the door.

[0030] In this embodiment, the logical computing ability of the signal processor 200 is utilized to generate an interrupt signal IRQ_1 for mode conversion, so that the power management circuit 100 does not need to rely on the main control circuit to run the power management program to monitor the interrupt signal in the low-power mode, thereby reducing the power consumption of the main control circuit in the low-power mode and further reducing the power consumption of the integrated circuit.

[0031] In the operating mode, the power management circuit powers on all circuits of the integrated circuit and transmits a detection signal according to a period as shown in Figure 1 For example, at least one frame of detection signal is transmitted. In this way, the integrated circuit calculates the measurement information using the corresponding digital sequence frame. In the low-power mode, the power management circuit controls the circuits in the integrated circuit to wake up and sleep periodically.

[0032] In the wake-up state of the low-power mode, the power management circuit wakes up at least the transceiver circuit and the signal processor in the integrated circuit and according to as shown in Figure 1At least one of the shown periods runs to obtain at least one piece of measurement information. In the sleep state of the low-power mode, the power management circuit shuts off the power supply of the awakened circuit to reduce the overall power consumption of the integrated circuit. Among them, in the awakened state, some or all of the circuits in the integrated circuit are powered on and running. In some examples, the power consumption of the integrated circuit in the awakened state is basically the same as that in the working mode. In some other examples, the power consumption of the integrated circuit in the awakened state is less than that in the working mode. For example, in the low-power mode, the main control circuit in the integrated circuit is in the sleep state, and the transceiver circuit and the signal processor are in the awakened state. The signal processor processes the digital sequence corresponding to the echo to determine whether to awaken the main control circuit.

[0033] For the convenience of distinction, the sleep state in the low-power mode represents the state where the integrated circuit maintains the lowest power consumption; the awakened state in the low-power mode represents the state where the power consumption of the integrated circuit is higher than the lowest power consumption; the average power consumption per unit time of the integrated circuit in the working mode is higher than the average power consumption per unit time in the low-power mode.

[0034] As can be seen from the above, in the low-power mode, the integrated circuit can detect the surrounding environment. In some examples, the signal processor can use at least two pieces of measurement information obtained from multiple rounds of wake-up / sleep state cycles to calculate and generate the interrupt signal IRQ_1. In this way, the overall power consumption of the integrated circuit can be further reduced. For this purpose, the integrated circuit further includes a second memory powered in the sleep state, which is connected to the signal processor and used to store the data written by the signal processor in at least one awakened state. The second memory can be a part of the first memory or be independently provided from the first memory. By using the second memory, the integrated circuit can store the unprocessed data in the awakened state for continued execution after subsequent wake-up. The data includes at least one piece of measurement information, unexecuted program instructions, etc. By selecting the storage capacity, the power consumption of the second memory has little impact on the overall power consumption in the sleep state.

[0035] In some embodiments, for the convenience of those skilled in the art to better understand the control of the power management circuit 100 in the low-power mode, the following will be described in combination with different circuits in the integrated circuit.

[0036] Such as Figure 3As shown, the main control circuit 300 in the integrated circuit is connected to the power management circuit 100. In this way, the power management circuit 100 can respond to another interrupt signal IRQ_2 from the main control circuit 300 to switch from the working mode to the low-power mode. For example, when the main control circuit 300 does not detect a new target within a preset time period after completing the target detection, the interrupt signal IRQ_2 is generated; or when the main control circuit 300 receives a mode conversion instruction from the upper-layer application, the interrupt signal IRQ_2 is generated. Among them, the interrupt signal IRQ_2 can be inverted or the same as IRQ_1. The logic circuit in the power management circuit can perform mode conversion based on the current mode and the timing logic of the received interrupt signal IRQ_2 or IRQ_1.

[0037] The working mode of the integrated circuit includes the wake-up state and the idle state. Different from the low-power mode, the duty cycle of the wake-up state in the working mode is greater than that in the low-power mode.

[0038] For example, in the cycle as Figure 1 shown, all the circuits in the integrated circuit are powered on and running during the T0 + T1 period, and enter the idle state during the IDLE period.

[0039] In the working mode, as Figure 4 shown, the main control circuit 300 and the signal processor 200 complete data reading and writing using the shared first memory 400. The main control circuit 300 also performs post-processing to output more complete measurement information, such as measurement data including angle, distance, speed, etc.

[0040] For example, as Figure 5 shown, the signal processor 200 includes a processing sub-circuit 201 and a writing sub-circuit 202. The processing sub-circuit 201 is connected to the writing sub-circuit 202, and the writing sub-circuit 202 is connected to the first memory 400. The first memory 400 is also connected to the main control circuit 300.

[0041] To cooperate with the operation of the integrated circuit in the low-power mode and the working mode, the integrated circuit also includes a fully integrated or partially integrated first clock circuit and a second clock circuit. Among them, the frequency of the first clock signal generated by the first clock circuit is greater than the frequency of the second clock signal generated by the second clock circuit. The power management circuit is respectively connected to the first clock circuit and the second clock circuit; in the normal working mode, the power management circuit works based on the first clock signal. In other words, the first clock circuit or the second clock circuit is used to support the part of the circuit in the integrated circuit that works at the beat frequency of the first clock signal or the second clock signal. In this way, the circuit operating in the low-power mode will consume less power due to the low-frequency clock compared to the same circuit in the working mode.

[0042] As Figure 6 andFigure 7 As shown, the frequency of the clock signal generated by the first clock circuit 500 is greater than the frequency of the clock signal generated by the second clock circuit 600. The power management circuit 100 is respectively connected to the first clock circuit 500 and the second clock circuit 600, so that the power management circuit 100 responds to the interrupt signal and switches from operating based on the clock signal generated by the second clock circuit 600 to operating based on the clock signal generated by the first clock circuit 500. That is to say, when the power management circuit 100 switches from the low-power mode to the normal mode in response to the interrupt signal, the working clock signal used will also switch from the second clock signal to the first clock signal, that is, from the low-frequency working clock to the normal high-frequency working clock.

[0043] In some embodiments, as Figure 6 shown, the first clock circuit 500 and the second clock circuit 600 are independent of each other. Under the control of the power management circuit, the first clock circuit 600 has a sleep state in the low-power mode. In some embodiments, as Figure 7 shown, the first clock circuit 500 and the second clock circuit 600 are connected. The second clock circuit 600 divides the clock signal generated by the first clock circuit 500 to obtain a clock signal with a frequency lower than that of the clock signal generated by the first clock circuit 500. In some other embodiments, still referring to Figure 7 , the first clock circuit 500 and the second clock circuit 600 are connected. The first clock circuit 500 multiplies the frequency of the second clock signal to obtain a first clock signal with a frequency higher than that of the second clock signal.

[0044] In some embodiments, in the low-power mode, the power management circuit uses the beat frequency of the second clock signal to time the duration of the sleep state. When the timing times out, it switches to using the beat frequency of the first clock signal to time the duration of the wake state. In this way, not only can the power management circuit periodically control the state of the integrated circuit between the wake-sleep states, but also ensure the basic transceiver and digital sequence processing functions of the integrated circuit during the wake state. In another example, in response to the interrupt signal IRQ_1, the power management circuit counts the duration of the interrupt or reset wake state and controls the operation of the circuits in the low-power mode in the integrated circuit to switch to the working mode. In the working mode, the working clock signal used by the power management circuit is the first clock signal. In this way, it switches from a low-frequency working clock to a high-frequency working clock to operate under the same clock system as other circuits in the integrated circuit. In yet another example, when the power management circuit switches from the working mode to the low-power mode in response to the interrupt signal IRQ_2, the working clock signal used switches from the first clock signal to the second clock signal, that is, from a high-frequency working clock to a low-frequency working clock. Since a lower-frequency clock signal is used in the low-power mode of the integrated circuit, the power consumption is further reduced; and a high-frequency clock signal is used in the wake state or the working mode, enabling the integrated circuit to operate normally.

[0045] To facilitate a better understanding of the working process of the integrated circuit provided in the above embodiments by those skilled in the art, the following will be combined with Figure 8 the shown integrated circuit and Figure 9 the shown based on Figure 8 the statistical chart of the power consumption of the integrated circuit changing with time obtained by testing the shown basic circuit, where the integrated circuit is used to support a radar system.

[0046] As Figure 8 shown, the integrated circuit includes a power management circuit 100, a signal processor 200, a main control circuit 300, a first / second memory 400, a first clock circuit 500, a second clock circuit 600, and a transceiver circuit 700. Among them, the crystal oscillator 501 in the first clock circuit is optionally located outside the integrated circuit and provides a reference clock signal to the inside of the integrated circuit by connecting to the pins of the integrated circuit. The power management circuit 100 is respectively connected to the signal processor 200, the main control circuit 300, the first clock circuit 500, the second clock circuit 600, and the transceiver circuit 700. The signal processor 200 and the main control circuit 300 are respectively connected to the first / second memory 400, and the signal processor 200 is also connected to the transceiver circuit 700. Among them, the first / second memory 400 represents a memory integrating a first memory and a second memory, or at least one of the memories selectively connected to the signal processor and the main control circuit according to the actual design.

[0047] Among them, the first clock circuit 500 is composed of a connected crystal oscillator 501 and a phase-locked loop circuit 502 to output a high-frequency first clock signal. The second clock circuit 600 is an RC oscillator circuit to output a low-frequency second clock signal.

[0048] During application, first set the wake-up configuration and sleep configuration in the power management circuit 100. Among them, the wake-up configuration, that is, Pre-config_wake_up, includes at least one of the following information: crystal oscillator power-on delay (XTL power on delay), phase-locked loop power-on delay (PLL power on delay), the configuration of the radio frequency and baseband that needs to be restored, PLL lock delay. The sleep configuration, that is, Pre-config_sleep, includes at least one of the following information: sleep time, radio power-off delay, BB power-off delay, and XTL power-off delay.

[0049] After the configuration is completed, when the integrated circuit is in the low-power mode, the power management circuit 100 periodically queries the above-pre-set configuration and automatically wakes up and sleeps periodically. Specifically, as Figure 9 shown, after the start of a working cycle, first, the power management circuit 100 generates an interrupt signal and sends it to the first clock circuit to wake up the first clock circuit 500 (that is, the crystal oscillator 501 and the phase-locked loop circuit 502), and the power consumption initially increases (at time t1), then the power management circuit 100 generates an interrupt signal and sends it to the transceiver circuit 700 and the signal processor 200 to restore the configuration of the transceiver circuit 700 and the signal processor 200, and the power consumption further increases (at time t2). Then, the power management circuit 100 continues to generate an interrupt signal and sends it to the transceiver circuit 700 and the signal processor 200 to set the radio frequency lock and start the engine of the signal processor 200 (at time t3). After these are completed, the integrated system will enter the active stage (from time t3 to time t4), detect signal transmission and echo reception based on the transceiver circuit 700 and perform digital signal processing based on the signal processor 200. At this time, the power consumption of the integrated circuit reaches the highest power consumption in the low-power mode (at time t5). At this time, if no target is detected, the low-power mode will continue to be maintained. Therefore, as Figure 9As shown by the dotted line in the figure, after the transceiver circuit 700 and the signal processor 200 complete the work of the current cycle, they enter the idle state. At this time, the power consumption of the integrated circuit begins to decrease (at time t6). Then, the power management circuit 100 generates an interrupt signal and sends it to the transceiver circuit 700 and the signal processor 200, so that the transceiver circuit 700 and the signal processor 200 store the status information and then enter the sleep state, and the power consumption of the integrated circuit further decreases (at time t7). Finally, the power management circuit 100 generates an interrupt signal and sends it to the first clock circuit 500, so that the first clock circuit 500 shuts down the power supply and enters the sleep state (at time t8). After that, the integrated circuit enters the sleep state. During this process, the second clock circuit 600 provides a working clock signal for the power management circuit 100 until the power management circuit 100 determines the start of the next working cycle through counting and wakes up the corresponding circuits in turn as shown before. At the same time, during this process, the data processed by the signal processor 200 can be written into the first / second memory 400, while the main control circuit 300 is always in the sleep state. If a target is detected, the signal processor 200 will generate an interrupt signal and send it to the power management circuit 100. Then, the power management circuit 100 will respond to the received interrupt signal and control the entire integrated circuit to resume the normal working mode. At this time, the first / second memory 400 and the main control circuit 500 will be woken up. Therefore, as Figure 9 shown by the dash-dotted line, the power consumption of the integrated circuit further increases above the maximum power consumption in the low-power mode and reaches the maximum power consumption of the integrated circuit.

[0050] From the above description, it can be seen that an interrupt signal is used in the application process of the integrated circuit instead of the software interrupt method. Therefore, the response speed will be faster. For example, the wake-up process of the first clock circuit 500 will be delayed longer, and the time in the sleep state during a working cycle will be longer, etc., that is, the power consumption will be lower. And the sleep process is pre-set in advance to reduce the wake-up time overhead and increase the sleep time per unit time. At the same time, the operation of power-consuming circuits is reduced. For example, the main control circuit 300, the first / second memory 400, and the clock tree circuit of the system on chip (SOC) not shown are basically powered off in the low-power mode. Therefore, the power consumption is reduced and the hardware resource overhead becomes smaller.

[0051] The above circuit division of various integrated circuits is only for clear description. When implemented, they can be combined into one circuit or some circuits can be split into multiple circuits. As long as the same logical relationship is included, they are all within the protection scope of this patent; adding insignificant modifications or introducing insignificant designs to the circuits of the integrated circuit without changing its core design are all within the protection scope of this patent.

[0052] Another aspect of the embodiments of the present application provides a chip, including the basic circuit described in any of the previous embodiments.

[0053] It is not difficult to find that the above embodiments are chip embodiments corresponding to the circuit embodiments, and the above embodiments can be implemented in cooperation with the chip embodiments. The relevant technical details mentioned in the chip embodiments are still valid in the above embodiments. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to the chip embodiments.

[0054] Another embodiment of the present application relates to a radar sensor, including: a carrier, an integrated circuit disposed on the carrier, and an antenna disposed on the carrier, or the antenna and the integrated circuit are integrated into a single device and disposed on the carrier. Among them, the integrated circuit is connected to the antenna and is used to process the echo signal received through the antenna. The integrated circuit is the integrated circuit provided in the foregoing embodiments. The integrated circuit is the integrated circuit provided in any embodiment of the present application.

[0055] When the antenna and the integrated circuit are not integrated into a single device, the integrated circuit is connected to the antenna through a first transmission line, and the first transmission line can be a Printed Circuit Board (PCB) trace. The carrier can be a printed circuit board PCB, such as a development board, a data acquisition board, or the main board of a device, etc., which will not be elaborated here one by one.

[0056] Since the structure and working principle of the integrated circuit included in the radar sensor have been described in detail in the above embodiments, they will not be elaborated here one by one.

[0057] It is not difficult to find that the above embodiments are device embodiments corresponding to the circuit embodiments, and the above embodiments can be implemented in cooperation with the circuit embodiments. The relevant technical details mentioned in the circuit embodiments are still valid in the above embodiments. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to the circuit embodiments.

[0058] The embodiments of the present application provide a terminal device, which may include: a device body; and the above-mentioned radar sensor disposed on the device body; among them, the radar sensor is used for target detection and / or communication to provide measurement information for the operation of the device body.

[0059] In some embodiments, the radar sensor can be disposed outside the device body. In other embodiments, the radar sensor can also be disposed inside the device body. In other embodiments, part of the radar sensor can be disposed inside the device body and part can be disposed outside the device body. The embodiments of the present application do not limit this, and it depends on the specific situation.

[0060] It should be noted that the radar sensor can realize functions such as target detection by transmitting and receiving radio signals, so as to provide the measurement information of the detected target to the device body, and then assist or even control the operation of the device body. Among them, the measurement information includes, for example, at least one of relative distance, relative speed, and relative angle.

[0061] In some embodiments, the above-mentioned device body can be components and products applied in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and healthcare. For example, the device body can be intelligent transportation devices (such as cars, motorcycles, ships, subways, trains, etc.), security devices (such as cameras), liquid level / flow rate detection devices, intelligent wearable devices (such as bracelets, glasses, etc.), smart home devices (such as floor-sweeping robots, door locks, TVs, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), and such as gate barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots), and can also be various instruments for detecting vital sign parameters and various devices equipped with such instruments, such as in-cabin detection of cars, indoor personnel monitoring, intelligent medical devices, consumer electronic devices, etc.

[0062] In some embodiments, when the above-mentioned device body is applied to ADAS, the radar sensor as an in-vehicle sensor can provide guarantees for various functional safety of the ADAS system, such as Autonomous Emergency Braking (AEB), Blind Spot Detection (BSD), Lane Changing Assist (LCA), Rear Cross Traffic Alert (RCTA), etc.

[0063] In addition, the examples mentioned in the above embodiments can be freely combined, and any combination method can be understood as an embodiment. The "embodiment" or "example" appearing at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments.

[0064] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. An integrated circuit, characterized in that: include: A power management circuit, and a signal processor connected to the power management circuit; The signal processor outputs an interrupt signal to the power management circuit; The power management circuit switches the integrated circuit from a low power consumption mode to a normal working mode in response to the interrupt signal; Wherein, in the low power consumption mode, the power management circuit controls the circuit in the integrated circuit to periodically switch between the awake state and the sleep state.

2. The integrated circuit according to claim 1, characterized in that The integrated circuit further includes a first clock circuit and a second clock circuit, the frequency of a first clock signal generated by the first clock circuit is greater than the frequency of a second clock signal generated by the second clock circuit, and the power management circuit is connected to the first clock circuit and the second clock circuit respectively; In the normal operating mode, the power management circuit operates based on the first clock signal.

3. The integrated circuit according to claim 2, characterized in that The first clock circuit includes a crystal oscillator and / or a phase-locked loop circuit; the second clock circuit includes a crystal oscillator or an RC oscillation circuit.

4. The integrated circuit according to claim 2, characterized in that The first clock circuit is connected to the second clock circuit, and the first clock signal is a frequency-multiplied signal of the second clock signal; or the first clock circuit is separate from the second clock circuit.

5. The integrated circuit according to any one of claims 1 to 4, characterized in that: The integrated circuit also includes a main control circuit; The main control circuit is connected to the power management circuit and operates in the awake state or the normal working mode in the low power consumption mode.

6. The integrated circuit according to claim 5, characterized in that In the normal operating mode, the power management circuit responds to an interrupt signal output by the main control circuit to switch the integrated circuit from the normal operating mode to the low power consumption mode.

7. The integrated circuit according to any one of claims 1 to 4, characterized in that: The integrated circuit further includes a first memory connected to the signal processor to store data written by the signal processor in the normal working mode.

8. The integrated circuit according to claim 1, characterized in that It also includes a second memory powered by the sleep state in the low power consumption mode, the second memory is connected to the signal processor and is used to store data written by the signal processor in at least one of the wake-up states.

9. The integrated circuit according to claim 8, characterized in that In the awake state, the signal processor reads data including data stored in the second memory to selectively output an interrupt signal.

10. The integrated circuit according to any one of claims 1 to 4, characterized in that: In response to the interrupt signal, the power management circuit counts the duration of interrupting or resetting the awake state.

11. The integrated circuit according to any one of claims 1 to 4, characterized in that: At least one of the signal processor, the transceiver circuit and the main control circuit in the integrated circuit has a low power consumption mode.

12. A radar chip, characterized in that: include: An integrated circuit as claimed in any one of claims 1 to 11.

13. A radar sensor, characterized in that: include: Carrier; An integrated circuit as claimed in any one of claims 1 to 11, arranged on a carrier; An antenna is arranged on the carrier, or the antenna and the integrated circuit are integrated into one device and arranged on the carrier; The integrated circuit is connected to the antenna and is used to transmit a radio frequency transmission signal and / or receive a radio frequency reception signal.

14. An electronic device, characterized in that: include: Equipment body; The radar sensor according to claim 13, disposed on the device body; Wherein, the radar sensor is used to provide measurement information.

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