Display panel and display device

Abstract

The embodiment of the utility model provides a display panel and a display device, the display panel comprises a substrate and a driving array arranged on one side of the substrate, and the driving array comprises transistors; the display panel further comprises a shielding structure arranged on the side, close to the driving array, of the substrate, the shielding structure comprises at least one shielding substructure, and the shielding substructure and the channel region of the transistor are at least partially overlapped. The shield substructure is connected to the potential signal terminal. By adopting the technical scheme provided by the embodiment of the utility model, the shielding substructures are correspondingly arranged in the channel region of the transistor, the shielding substructures can be connected with potential signal terminals, the shielding substructures connected with potential can effectively reduce the influence of the transistor in different working environments, the working stability of the transistor is effectively ensured, and the reliability of the transistor is improved. And the display effect of the display panel is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of display panels, in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. However, there are still some technical problems in the existing display panels that need to be solved urgently. Summary of the Utility Model

[0003] Embodiments of the utility model provide a display panel and a display device. By connecting a shielding sub-structure to a potential signal, the stability of the transistor operation is effectively guaranteed, and thus the display effect of the display panel is ensured.

[0004] In a first aspect, an embodiment of the utility model provides a display panel, including a substrate and a driving array disposed on one side of the substrate, wherein the driving array includes transistors;

[0005] The display panel further includes a shielding structure disposed on the side of the substrate close to the driving array, the shielding structure includes at least one shielding sub-structure, and the shielding sub-structure at least partially overlaps with the channel region of the transistor;

[0006] The shielding sub-structure is connected to a potential signal terminal.

[0007] In a second aspect, an embodiment of the utility model provides a display device, including the display panel described in the first aspect.

[0008] Embodiments of the utility model provide a display panel. One side of the substrate of the display panel includes a driving array, and the driving array includes transistors. Further, the display panel further includes a shielding structure disposed on the side of the substrate close to the driving array. At the same time, the shielding structure includes at least one shielding sub-structure, and the shielding sub-structure is connected to a potential signal terminal, and the potential signal terminal can provide a potential signal for the shielding sub-structure. The shielding sub-structure connected to the potential is equivalent to a shielding layer, which can effectively reduce the influence on the corresponding transistor in different working environments, such as the case of threshold drift. Therefore, the stability of the transistor operation can be effectively guaranteed, and thus the display effect of the display panel is ensured. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the utility model, the following briefly introduces the drawings required for describing the embodiments. Obviously, the introduced drawings are only the drawings of a part of the embodiments to be described by the utility model, rather than all the drawings. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0010] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 2 It is a circuit element diagram of a driving circuit provided by an embodiment of the present invention;

[0012] Figure 3 It is a circuit element diagram of another driving circuit provided by an embodiment of the present invention;

[0013] Figure 4 It is a circuit element diagram of another driving circuit provided by an embodiment of the present invention;

[0014] Figure 5 It is a circuit element diagram of another driving circuit provided by an embodiment of the present invention;

[0015] Figure 6 is Figure 1 a schematic cross-sectional view along the section line A-A' in

[0016] Figure 7 It is a circuit element diagram of a peripheral driving circuit provided by an embodiment of the present invention;

[0017] Figure 8 is Figure 1 a schematic cross-sectional view along the section line B-B' in

[0018] Figure 9 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 10 It is a schematic film layer structure diagram of a peripheral driving circuit provided by an embodiment of the present invention;

[0020] Figure 11 is Figure 10 a schematic diagram of a part of the structure in

[0021] Figure 12 is Figure 10 a schematic diagram of another part of the structure in

[0022] Figure 13 It is a circuit element diagram of another peripheral driving circuit provided by an embodiment of the present invention;

[0023] Figure 14 is Figure 1 another schematic cross-sectional view along the section line B-B' in

[0024] Figure 15 It is a schematic film layer structure diagram of another peripheral driving circuit provided by an embodiment of the present invention;

[0025] Figure 16 is Figure 15 a schematic diagram of a part of the structure in;

[0026] Figure 17 is Figure 15 a schematic diagram of another part of the structure in;

[0027] Figure 18 is a circuit element diagram of another peripheral drive circuit provided by an embodiment of the present invention;

[0028] Figure 19 is Figure 1 another cross-sectional schematic diagram along the section line B-B' in;

[0029] Figure 20 is Figure 1 another cross-sectional schematic diagram along the section line B-B' in;

[0030] Figure 21 is Figure 9 another cross-sectional schematic diagram along the section line C-C' in;

[0031] Figure 22 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0032] Figure 23 is Figure 22 a cross-sectional schematic diagram along the section line I-I' in;

[0033] Figure 24 is Figure 22 a cross-sectional schematic diagram along the section line K-K' in;

[0034] Figure 25 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0035] Figure 26 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0036] Figure 27 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0037] Figure 28 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0038] Figure 29 is a schematic diagram of the structure of a display module provided by an embodiment of the present invention. Detailed implementation manners

[0039] The present utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present utility model, rather than limiting the present utility model. In addition, it should be noted that for the convenience of description, only the parts related to the present utility model rather than all the structures are shown in the drawings.

[0040] It should be noted that the terms "first", "second", etc. in the description and claims of the present utility model and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a system, product, or device including a series of units does not have to be limited to those units clearly listed, but may include other units not clearly listed or inherent to these products or devices.

[0041] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present utility model, Figure 2 is a circuit element diagram of a driving circuit provided by an embodiment of the present utility model, Figure 3 is a circuit element diagram of another driving circuit provided by an embodiment of the present utility model, Figure 4 is a circuit element diagram of another driving circuit provided by an embodiment of the present utility model, Figure 5 is a circuit element diagram of another driving circuit provided by an embodiment of the present utility model, Figure 6 is Figure 1 a schematic cross-sectional view along the cutting line A-A' in Figure 7 is a circuit element diagram of a peripheral driving circuit provided by an embodiment of the present utility model, Figure 8 is Figure 1 a schematic cross-sectional view along the cutting line B-B' in Figures 1 to 8 As shown in the reference

[0042] Specifically, the display panel 10 includes a driving circuit 200 disposed on one side of the substrate 100. Refer to Figure 1As shown in the figure, the driving array 20 in the figure can be the driving circuit 200 or the peripheral driving circuit 710. The driving circuit 200 is electrically connected to the light-emitting element 400 to drive the light-emitting element 400 to display and emit light. The peripheral driving circuit 710 transmits control signals (such as a scanning signal and a light-emitting control signal) to the driving circuit 200, so as to ensure that the driving circuit 200 provides a driving current for the light-emitting element 200, and further ensure the display effect of the display panel 10.

[0043] Among them, the driving array 20 includes a transistor 210. Exemplarily, with reference to Figures 2 to 6 As shown in the figure, when the driving array 20 is the driving circuit 200, the setting manner of the driving circuit 200 has diversity. The driving circuit 200 includes at least one transistor 210. With reference to Figures 7 to 8 As shown in the figure, when the driving array 20 is the peripheral driving circuit 710, the setting manner of the peripheral driving circuit 710 also has diversity. The peripheral driving circuit 710 includes at least one transistor 210. The number and type of transistors 210 provided in the driving circuit 200 and the peripheral driving circuit 710 can be adaptively adjusted according to actual requirements. The embodiments of the present invention do not specifically limit this.

[0044] Furthermore, in combination with Figure 6 and Figure 8 As shown in the figure, the display panel 10 includes a substrate 100 and a multi-layer active layer, insulating layer, and metal layer alternately arranged on one side of the substrate 100, and the driving circuit 200 is included in the active layer, insulating layer, and metal layer. Exemplarily, the multi-layer insulating layers on one side of the substrate 100 may include a buffer layer 110, a first gate insulating layer 120, a first interlayer insulating layer 130, a second interlayer insulating layer 140, a third interlayer insulating layer 150, etc. Based on the specific number and types of insulating layers provided, it can be adaptively adjusted according to the actual display panel 10. For the transistor 210 in the driving array 20, other structures may also be included, such as an active layer 201, a gate 202, a capacitor layer 203, a source 204, and a drain 205, etc. The structure of the transistor in the peripheral driving circuit 710 is similar, such as an active layer 231, a gate 232, a source 233, and a drain 234, etc. The specific film layer structure of the transistor 210 can be adaptively adjusted according to the actual situation.

[0045] Furthermore, with reference to Figure 6 and Figure 8As shown in the figure, the display panel further includes a shielding structure 300, and the shielding structure 300 is disposed on the side of the substrate 100 close to the driving array 20. Specifically, the shielding structure 300 includes a shielding sub-structure 310, and the shielding sub-structure 310 at least partially overlaps with the channel region of the transistor 210. The channel region is the relative region between the active layer 201 and the gate 202. At the same time, the shielding sub-structure 310 can be connected to some potential signal terminals B, that is, electrically connected to some potential signal terminals B, so as to achieve the effect of electronic shielding. Furthermore, ions on the side of the substrate 100 can be effectively prevented from entering the active layer of the transistor 300, thereby avoiding affecting the operation of the channel region, ensuring the operating stability of the transistor 210, ensuring the operating stability of the driving array 20, being beneficial to improving the situation of residual images and the like in the display panel 10, and ensuring the display effect of the display panel 10.

[0046] In summary, the embodiment of the present invention provides a display panel. The shielding sub-structure is at least partially overlapped with the channel region of the transistor, and the shielding sub-structure is connected to the potential signal terminal, and the potential signal terminal can provide a potential signal for the shielding sub-structure. The shielding sub-structure with an access potential is equivalent to a shielding layer, which can effectively reduce the influence on the corresponding transistor in different working environments, such as the situation of threshold drift. Therefore, the operating stability of the transistor can be effectively ensured, and further the display effect of the display panel can be ensured.

[0047] Figure 9 is a schematic structural diagram of another display panel provided by the embodiment of the present invention. Figure 10 is a schematic diagram of a film layer structure of a peripheral driving circuit provided by the embodiment of the present invention. Figure 11 is Figure 10 a schematic diagram of a part of the structure in Figure 12 is Figure 10 a schematic diagram of another part of the structure in Figures 1 to 12 Referring to

[0048] Specifically, referring to Figure 1As shown, the display area 100A of the display panel 10 is used to set the light-emitting elements 400, the driving circuit 200, etc., mainly to realize the display function of the display panel 10. The non-display area 100B surrounding the display area 100A can be provided with a peripheral driving circuit 710 and some wirings, etc. The peripheral driving circuit 710 transmits a control signal to the driving circuit 200, so as to ensure that the driving circuit 200 drives the light-emitting elements 400 and ensure the display effect of the display panel 10. Specifically, refer to Figure 1 As shown, the display panel 10 is provided with a peripheral circuit group 700 in the non-display area 100B. The peripheral circuit group 700 includes a plurality of cascaded peripheral driving circuits 710, and the plurality of cascaded peripheral driving circuits 710 are arranged along the first direction X.

[0049] Among them, the setting method of the driving circuit 200 has diversity. Refer to Figure 2 and Figure 3 As shown, the driving circuit 200 can be illustrated by "7T1C". Refer to Figure 4 and Figure 5 As shown, the driving circuit 200 can be illustrated by "8T1C". Among them, "T" represents a transistor in the driving circuit 200, and "C" represents a capacitor. Based on the setting method of the driving circuit 200, those skilled in the art can make adaptive adjustments according to requirements.

[0050] Optionally, the type of the transistor 210 in the driving circuit 200 may include a low-temperature poly-silicon transistor (Low Temperature Poly-Silicon, LTPS), and the transistor 210 has advantages such as a high switching speed, a high carrier mobility, and low power. Refer to Figure 2 As shown, the transistors 210 in the driving circuit 200 are all low-temperature poly-silicon transistors. Further, the type of the transistor 210 may also include an oxide transistor (Indium Gallium Zinc Oxide, IGZO), and the transistor 210 has advantages such as a low production cost and low power consumption. Refer to Figures 3 to 5 As shown, when the driving circuit 200 includes both low-temperature poly-silicon transistors and oxide transistors at the same time, that is, LTPO is combined with IGZO, the display panel 10 including the driving circuit 200 is an LTPO (Low Temperature Polycrystalline Oxide, low-temperature polycrystalline oxide). The LTPO display panel 10 not only has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc. of the LTPS display panel, but also has the advantages of low production cost and low power consumption of the IGZO display panel.

[0051] Further, refer to Figure 2As shown, in the embodiment of the present utility model, the driving circuit 200 is exemplified by including "7T1C". The driving circuit 200 includes: a light-emitting control transistor M1, a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, and a storage capacitor Cst. Among them, the first scan signal line SCAN1 controls the on or off of the initialization transistor M5 of the driving circuit, and when the initialization transistor M5 is turned on, the gate potential of the driving transistor M3 is reset, that is, the first reset signal Vref1 is transmitted to the initialization transistor M5 and the connection node (the first node N1) of the driving transistor M3, the initialization transistor M5, the threshold compensation transistor M4, and the storage capacitor Cst is reset. The second scan signal line SCAN2 controls the on and off of the data writing transistor M2 of the driving circuit, and when the data writing transistor M2 is turned on, the data signal Vdata on the data signal line is written to the gate of the driving transistor M3. The second scan signal line SCAN2 controls the on and off of the threshold compensation transistor M4, and when the threshold compensation transistor M4 is turned on, the threshold voltage of the driving transistor M3 is compensated. At the same time, the first scan signal line SCAN1 controls the on and off of the reset transistor M7, and when the reset transistor M7 is turned on, the anode of the light-emitting element 400 connected to the pixel circuit 300 is reset, that is, the second reset signal Vref2 is transmitted to the anode of the light-emitting element 400. The light-emitting control signal Emit controls the on and off of the light-emitting control transistor M1 and the second light-emitting control transistor M6, and when the light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned on, the first power supply signal PVDD is transmitted to the light-emitting element 400, thereby realizing the display and light emission of the light-emitting element 400. Exemplarily, the light-emitting element 400 may be an organic light-emitting diode (OLED), a Mini LED, a Micro LED, a quantum dot light-emitting diode (QLED), etc., and the embodiment of the present utility model does not limit the specific type of the light-emitting element. Further, the light-emitting element may include a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and different color light-emitting elements may have specific multiple different arrangement modes, such as diamond pixel arrangement, standard RGB arrangement, delta pixel arrangement, pearl pixel arrangement, or 2in1 pixel arrangement, etc., and the embodiment of the present utility model does not limit the specific arrangement mode of different color light-emitting elements either.

[0052] Further, referring to Figure 4 andFigure 5 As shown, the driving circuit 200 includes: a light-emitting control transistor M1, a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, a bias transistor M8, and a storage capacitor Cst. Among them, the working process of the driving circuit 200 is similar to the above process, and will not be described repeatedly here. Among them, the control terminal of the bias transistor M8 is connected to a scan signal (shown as Sp* in the figure), which can control the on and off of the bias transistor M8, and when the bias transistor M8 is turned on, a reset signal (shown as DVH in the figure) is written into the bias transistor M8, and the second node N2 is biased and adjusted.

[0053] Specifically, referring to Figure 2 and Figure 6 As shown, there is a shielding sub-structure 310 that at least partially overlaps with the channel region of the transistor 210 in the driving circuit 200. At the same time, the shielding sub-structure 310 can be connected to some potential signals, that is, electrically connected to some potential signal terminals B, which plays an electronic shielding effect, effectively preventing ions on the substrate 100 side from entering the active layer 201 of the transistor 300, that is, avoiding affecting the operation of the channel region, thereby ensuring the working stability of the transistor 210 in the driving circuit 200, which is beneficial to improving the situation of residual images in the display panel 10 and ensuring the display effect of the display panel 10. Further, if the active layer 201 of the transistor 210 is affected by light irradiation and its working stability is affected, for example, when the transistor 210 is an oxide transistor (Indium Gallium Zinc Oxide, IGZO), the shielding structure 300 can also play a role in blocking light, avoiding the situation of threshold drift of the transistor 210.

[0054] Optionally, shielding sub-structures 310 can be provided in the channel regions of the transistors 210 connected to different control signal terminals, and different shielding sub-structures 310 are connected to different potential signal terminals B ( Figure 2 different potential signal terminals in it are shown as B1 and B2). Specifically, the transistors 210 connected to different control signal terminals can operate in different working modes. Different working modes can refer to the on time, off time, different signals input when turned on, etc. of the transistor 210, which can be specifically defined according to the actual type of the transistor 210. The embodiments of the present invention do not specifically define this here. Based on the different working modes of the transistor 210, the shielding effect required by the shielding structure 300 will also be different, that is, by connecting different shielding sub-structures 310 to different potential signal terminals, the working stability of each transistor 210 is ensured, and thus the overall display effect of the display panel 10 is ensured.

[0055] Among them, the peripheral driving circuit 710 transmits control signals (such as scan signals and light emission control signals, etc.) to the transistor 210 of the driving circuit 200, and adjusts the working state of the transistor 210 through the control signals. With the diversity of the types and uses of the transistors 210 in the driving circuit 200, the control signals required by different transistors 210 in the driving circuit 200 will also be adjusted, that is, the types of the peripheral driving circuit 710 also have diversity. Exemplarily, referring to Figure 2 As shown, when the control signal input to the light emission control transistor M1 is the light emission control signal Emit, there is a type of peripheral driving circuit 710 that outputs the light emission control signal Emit to the driving circuit 200; when the control signal input to the data writing transistor M2 is the second scan signal line SCAN2, there is a type of peripheral driving circuit 710 that outputs the second scan signal line SCAN2 to the driving circuit 200, that is, different transistors 210 in the driving circuit 200 can have different working processes, and thus different control signals need to be input, so there are corresponding different types of peripheral driving circuit 710. Further, when combining different types of transistors 210 in the driving circuit 200, that is, including low-temperature polysilicon transistors and oxide transistors, since the enable levels for controlling these different types of transistors 210 are different, different peripheral driving circuits 710 are required to provide different types of control signals to different transistors 210. Thus, it reflects the diversity of the setting of the peripheral driving circuit 710.

[0056] Exemplarily, the specific setting methods of the peripheral driving circuit 710 can include "8T2C", "12T3C" or "15T4C", etc., where "T" represents the first transistor 230 in the peripheral driving circuit 710, and "C" represents a capacitor. Exemplarily, Figure 7 "12T3C" is taken as an example for illustration. Based on the setting method of the peripheral driving circuit 710, those skilled in the art can make adaptive adjustments according to requirements.

[0057] Specifically, referring to Figure 1 、 Figure 7 and Figure 8 As shown, the shielding sub-structure 310 further includes a plurality of peripheral shielding sub-structures 330. The transistors 210 in the driving array include the first transistors 230 in a plurality of peripheral driving circuits 710. The peripheral shielding sub-structure 330 at least partially overlaps with the channel regions of the first transistors 230 in the peripheral driving circuit 710. At the same time, the peripheral shielding sub-structure 330 can access some potential signals, that is, be connected to some potential signal terminals B( Figure 8is electrically connected (shown as B3 in the figure), achieving an electronic shielding effect, effectively preventing ions on the substrate 100 side from entering the active layer of the first transistor 230, that is, avoiding affecting the operation of the channel region, thereby ensuring the working stability of the peripheral driving circuit 710, being conducive to ensuring the stability and reliability of the signals output by the peripheral driving circuit 710, and thus ensuring the driving effect of the driving circuit 200 on the light-emitting element 400, that is, ensuring the display effect of the display panel 10. Further, the peripheral driving circuit 710 includes multiple first transistors 230, and the shielding sub-structure 310 also includes multiple peripheral shielding sub-structures 330. In the peripheral driving circuit 710, the channel region of each first transistor 230 can be correspondingly provided with a peripheral shielding sub-structure 330 and overlap with it, so as to better ensure the working stability of the peripheral driving circuit 710 and further ensure the display effect of the display panel 10.

[0058] Specifically, referring to Figures 10 to 12 as shown, Figure 10 Region C1 in the figure shows a schematic diagram of the overall film layer of a peripheral driving circuit 710, Figure 11 Region D1 in the figure and Figure 12 Region E1 in the figure are Figure 10 schematic diagrams of the structure of partial film layers of the peripheral driving circuit 710 in Region C1 in the figure. Among them, Figure 11 Region D1 in the figure shows the active layers 233 of multiple first transistors 230, Figure 12 Region E1 in the figure shows multiple peripheral shielding sub-structures 330; Figure 10 Region C2 in the figure shows another schematic diagram of the overall film layer of the peripheral driving circuit 710, Figure 11 Region D2 in the figure and Figure 12 Region E2 in the figure are Figure 10 schematic diagrams of the structure of partial film layers of the peripheral driving circuit 710 in Region C1 in the figure. Among them, Figure 11 Region D2 in the figure shows the active layers 233 of multiple first transistors 230, Figure 12 Region E2 in the figure shows multiple peripheral shielding sub-structures 330. Combining Figures 10 to 12 it can be known that the peripheral shielding sub-structure 300 is correspondingly arranged with the active layer 233, which can ensure that the peripheral shielding sub-structure 330 acts as a blocking film layer to effectively prevent ions on the substrate 100 side from entering the active layer 233 of the first transistor 230, that is, avoiding affecting the operation of the channel region, ensuring the stable and reliable control signals output by the peripheral driving circuit 710, and thus ensuring the working stability of the driving circuit 200 and the display effect of the display panel 10. It should be noted that Figures 10 to 12 only shows a schematic diagram of a structure, and the setting methods of the peripheral driving circuit 710 in different display panels 10 are diverse, and will not be exemplified one by one here.

[0059] Continuing to refer toFigure 1 , Figures 7 to 12 As shown in Figures 7 to 12 , in the same peripheral driving circuit 710, electrical connections are made between multiple peripheral shielding sub-structures 330 that at least partially overlap with the channel regions of multiple first transistors 230.

[0060] Specifically, referring to Figure 1 and Figure 7 shown in Figure 7 , the number of first transistors 230 provided in the peripheral driving circuit 710 has diversity. Figure 7 Taking the peripheral driving circuit 710 including 12 first transistors 230 as an example for illustration.

[0061] Among them, corresponding to Figure 7 the specific film layer structure of the peripheral driving circuit 710 shown in Figure 7 , reference can be made to Figure 10 region C1 in Figure 10 . Further, referring to Figure 10 and Figure 12 shown in Figure 12 , in the same peripheral driving circuit 710, multiple peripheral shielding sub-structures 330 are included, and electrical connections are made between the multiple peripheral shielding sub-structures 330. When the peripheral shielding sub-structures 330 are connected to a potential signal, the peripheral shielding sub-structures 330 can act as a shielding layer to provide electrical shielding protection for the first transistors 230, thereby ensuring the working stability of the peripheral driving circuit 710. And by making electrical connections between multiple peripheral shielding sub-structures 330 that at least partially overlap with the channel regions of multiple first transistors 230 in the same peripheral driving circuit 710, the potential signals accessed by the peripheral shielding sub-structures 330 in the same peripheral driving circuit 710 are the same, which can reduce the number of potential signal terminals B and simplify the electrical connection method of the multiple peripheral shielding sub-structures 330. Furthermore, the process preparation cost of the display panel 10 can be reduced, and the feasibility of the display panel 10 provided by the embodiments of the present invention can be improved.

[0062] Figure 13 is a circuit element diagram of another peripheral driving circuit provided by the embodiments of the present invention. Figure 14 is Figure 1 another cross-sectional schematic diagram along the section line B - B' in Figure 1 . Figure 15 is a schematic diagram of the film layer structure of another peripheral driving circuit provided by the embodiments of the present invention. Figure 16 is Figure 15 a schematic diagram of a part of the structure in Figure 15 . Figure 17 is Figure 15 a schematic diagram of another part of the structure in Figure 15 . Referring to Figure 1 , Figures 13 to 17As shown, the peripheral driving circuit 710 further includes at least one second transistor 240; the second transistor 240 includes an active layer 241, a bottom gate 242, and a top gate 243; the bottom gate 242 is located between the active layer 241 and the substrate 100, and the top gate 243 is located on a side of the active layer 241 away from the substrate 100. In the same second transistor 240, the bottom gate 242 is electrically connected to the top gate 243; the bottom gate 242 is formed on the same layer as the peripheral shielding sub-structure 330, and the bottom gate 242 is insulated from the peripheral shielding sub-structure 330.

[0063] Among them, the peripheral driving circuit 710 may further include at least one second transistor 240. Refer to Figure 14 As shown, the second transistor 240 includes an active layer 241, a bottom gate 242, a top gate 243, a source electrode 244, and a drain electrode 245. Among them, the bottom gate 242 is located between the active layer 241 and the substrate 100, and the top gate 243 is located on a side of the active layer 241 away from the substrate 100. It can be understood that the second transistor 240 is a top-bottom dual-gate transistor. Specifically, refer to Figure 14 As shown, in the same second transistor 240, the bottom gate 242 is electrically connected to the top gate 243, which can ensure the efficiency of adjusting the switching state of the second transistor 240.

[0064] Furthermore, refer to Figure 14 As shown, the bottom gate 242 of the second transistor 240 may be arranged on the same layer as the peripheral shielding sub-structure 330. In this way, the number of film layers of the entire display panel 10 can be shown, which is conducive to realizing the thin-film design of the display panel 10 and reducing the process preparation cost of the display panel 10. Further, since the bottom gate 242 is electrically connected to the top gate 243, the signals transmitted in the bottom gate 242 and the top gate 243 are the same. And the peripheral shielding sub-structure 330 is electrically connected to the potential signal terminal B. Although the bottom gate 242 and the peripheral shielding sub-structure 330 are arranged on the same layer, the insulation setting relationship between the peripheral shielding sub-structure 330 and the bottom gate 242 should be ensured, so as to ensure the stable transmission of signals in the peripheral driving circuit 710 and ensure the overall display effect of the display panel 10.

[0065] Specifically, refer to Figures 15 to 17 As shown, Figure 15 Region F in shows an overall film layer schematic diagram of a peripheral driving circuit 710. Figure 16 Region G in and Figure 17 Region H in are Figure 10 structural schematic diagrams of partial film layers of the peripheral driving circuit 710 in region F in. Among them, Figure 15 the active layers 233 of a plurality of first transistors 230 are shown in region G in. Figure 17 a plurality of peripheral shielding sub-structures 330 are shown in region H in. Among them, refer to Figure 17 As shown, Figure 12Multiple peripheral shielding sub-structures 330 are shown in the middle region E2. In combination with Figures 10 to 12 it can be seen that the bottom gate 242 and the peripheral shielding sub-structures 330 are arranged on the same layer. In this way, the number of film layers of the entire display panel 10 can be shown, which is beneficial to the realization of the thinning design of the display panel 10, while reducing the process preparation cost of the display panel 10. Moreover, the peripheral shielding sub-structures 330 also act as a barrier film layer to effectively prevent ions on the substrate 100 side from entering the active layer 233 of the first transistor 230, that is, to avoid affecting the operation of the channel region, ensure the stable and reliable control signal output by the peripheral driving circuit 710, thereby ensuring the working stability of the driving circuit 200 and the display effect of the display panel 10. It should be noted that Figures 15 to 17 only a schematic structural diagram is shown, and the setting methods of the peripheral driving circuit 710 in different display panels 10 are diverse, and no examples will be given one by one here.

[0066] Figure 18 is a circuit element diagram of another peripheral driving circuit provided by an embodiment of the present invention; Figure 19 is Figure 1 another cross-sectional schematic diagram along the section line B-B' in Figure 1 , Figure 3 , Figure 9 , Figure 13 , Figure 18 and Figure 19 shown, the peripheral driving circuit 710 includes a first scan driving circuit 710b and a second scan driving circuit 710c, and the transistors 210 in the driving array include a first scan transistor 251 and a second scan transistor 252 in the driving circuit 200; the first scan driving circuit 710b is connected to the control end of the first scan transistor 251 through a first scan signal line s1, and the second scan driving circuit 710c is connected to the control end of the second scan transistor 252 through a second scan signal line s2; the peripheral shielding sub-structures 330 include a first peripheral shielding sub-structure 330a corresponding to the first scan driving circuit 710b and a second peripheral shielding sub-structure 330b corresponding to the second scan driving circuit 710c; the first peripheral shielding sub-structure 330a and the second peripheral shielding sub-structure 330b are connected to different potential signal terminals B.

[0067] Specifically, the transistors 210 in the driving circuit 200 may include a first scan transistor 251 and a second scan transistor 252, and the difference between the first scan transistor 251 and the second scan transistor 252 may be the difference in transistor types. For example, the first scan transistor 251 is an oxide transistor, and the second scan transistor 252 is a low-temperature polysilicon transistor. Exemplarily, in combination with Figure 3 and Figure 9As shown, the first scan transistor 251 may be a threshold compensation transistor M4 and / or an initialization transistor M5, etc., and the second scan transistor 252 may be a data writing transistor M2, etc. Based on the specific settings of the first scan transistor 251 and the second scan transistor 252, it can be adaptively adjusted according to different driving circuits 200, and the embodiments of the present invention do not specifically limit this. It should be noted that in this embodiment, the first scan signal line s1 refers to the scan line for electrically connecting the first scan driving circuit 710b and the first scan transistor 251, and the second scan signal line s2 refers to the scan line for electrically connecting the second scan driving circuit 710c and the second scan transistor 252.

[0068] Furthermore, the display panel 10 includes a plurality of peripheral driving circuits 710, and the control signals output by different peripheral driving circuits 710 may be different. Specifically, the peripheral driving circuit 710 includes a first scan driving circuit 710b and a second scan driving circuit 710c. The first scan driving circuit 710b transmits the output control signal to the first scan transistor 251, and the second scan driving circuit 710c transmits the output control signal to the second scan transistor 252, so as to ensure that the peripheral driving circuit 710 controls the driving circuit 200 and drives the light-emitting element 400 to ensure the display effect of the display panel 10.

[0069] Exemplarily, in combination with Figure 3 、 Figure 9 、 Figure 13 、 Figure 18 and Figure 19 as shown, the first scan driving circuit 710b is connected to the control terminal of the first scan transistor 251 (exemplified by the initialization transistor M5 in Figure 3 ) through the first scan signal line s1 (exemplified by SCAN1 in Figure 3 ), and the second scan driving circuit 710c is connected to the control terminal of the second scan transistor 252 (exemplified by the data writing transistor M2 in Figure 3 ) through the second scan signal line s2 (exemplified by Sp in Figure 3 ).

[0070] Furthermore, the peripheral shielding sub-structure 330 may include a first peripheral shielding sub-structure 330a and a second peripheral shielding sub-structure 330b, wherein the first peripheral shielding sub-structure 330a overlaps with the channel region of the transistor in the first scan driving circuit 710b, and the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scan driving circuit 710c. Exemplarily, referring to Figure 19 as shown, Figure 19The cross-sectional views of the first scan driving circuit 710b and the second scan driving circuit 710c are placed in one figure for easy observation.

[0071] Furthermore, referring to Figure 19 as shown, the first peripheral shielding sub-structure 330a and the second peripheral shielding sub-structure 330b are respectively disposed in different peripheral driving circuits 710, then the first peripheral shielding sub-structure 330a and the second peripheral shielding sub-structure 330b can be connected to different potential signal terminals ( Figure 19 the different potential signal terminals in are shown as B4 and B5). Specifically, the control signals output by different peripheral driving circuits 710 are different, and specific limitations are made in combination with the type of the actual peripheral driving circuit 710. Generally speaking, according to the differences of the peripheral driving circuits 710, the potential signals accessed by the peripheral shielding sub-structures 330 disposed in the peripheral driving circuits 710 are set differently, which can better ensure the reliability and stability of the signals output by the peripheral driving circuits 710, and further ensure the overall display effect of the display panel 10.

[0072] Optionally, in the same peripheral driving circuit 710, there are multiple first transistors 230, and there are multiple peripheral shielding sub-structures 330 overlapping with the channel regions of the first transistors 230. As mentioned above, for multiple different peripheral driving circuits 710, the potential signals accessed by the peripheral shielding sub-structures 330 disposed in different peripheral driving circuits 710 can be different. Thus, it can also be considered that in the same peripheral driving circuit 710, the different peripheral shielding sub-structures 330 correspondingly disposed for the channel regions of different first transistors 230 can also access different potential signals, further ensuring the reliability and stability of the signals output by the driving circuit 710.

[0073] Continuing to refer to Figure 1 、 Figure 3 、 Figure 9 、 Figure 13 、 Figure 18 and Figure 20 as shown, the first scan transistor 251 includes an initialization transistor M5, the second scan transistor 252 includes a data writing transistor M2; the potential signal of the second peripheral shielding sub-structure 330b is greater than the potential signal of the first peripheral shielding sub-structure 330a.

[0074] Among them, referring to Figure 3As shown, in the driving circuit 200, the first scanning transistor 251 may be the initialization transistor M5, and the second scanning transistor 252 may be the data writing transistor M2. Based on the differences between the first scanning transistor 251 and the second scanning transistor 252 in the driving circuit 200, the magnitude of the potential signal of the corresponding peripheral shielding sub-structure 330 provided in the peripheral driving circuit 710 can be adjusted accordingly. Specifically, the first peripheral shielding sub-structure 330a overlaps with the channel region of the transistor in the first scanning driving circuit 710b, and the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scanning driving circuit 710c. The potential signal of the second peripheral shielding sub-structure 330b can be adjusted to be greater than the potential signal of the first peripheral shielding sub-structure 330a, so as to ensure that the peripheral driving circuits 710 of the entire display panel 10 can output stable control signals and ensure the display effect of the display panel 10.

[0075] Figure 20 is Figure 1 Another cross-sectional schematic diagram along the section line B-B' in, refer to Figure 1 、 Figure 3 、 Figure 7 、 Figure 9 Figure 18 and Figure 20 As shown, the peripheral driving circuit includes a second scanning driving circuit 710c and a light-emitting control driving circuit 710a. The driving circuit 200 includes a second scanning transistor 252 and a light-emitting control transistor 253. The second scanning driving circuit 710c is connected to the control end of the second scanning transistor 252 through the second scanning signal line s2, and the light-emitting control driving circuit 710a is connected to the control end of the light-emitting control transistor 253 through the light-emitting control signal line Emit. The peripheral shielding sub-structure 330 includes a second peripheral shielding sub-structure 330b corresponding to the second scanning driving circuit 710c and a third peripheral shielding sub-structure 330c corresponding to the light-emitting control driving circuit 710a. The second peripheral shielding sub-structure 330b and the third peripheral shielding sub-structure 330c are connected to different potential signal terminals B.

[0076] Specifically, the driving circuit 200 may include a second scanning transistor 252 and a light-emitting control transistor 253. The difference between the second scanning transistor 252 and the light-emitting control transistor 253 may be the difference in the transistor working process. For example, the second scanning transistor 252 works in the data writing stage of the driving circuit 200, and the light-emitting control transistor 253 works in the light-emitting control stage of the driving circuit 200. Exemplarily, in combination with Figure 3As shown, the second scanning transistor 252 may be a data writing transistor M2 or the like, and the light emission control transistor 253 may be the light emission control transistor M1 and / or the second light emission control transistor M6. Based on the specific settings of the light emission control transistor 253 and the second scanning transistor 252, it can be adaptively adjusted according to different driving circuits 200, and the embodiments of the present invention do not specifically limit this.

[0077] Furthermore, the display panel 10 includes a plurality of peripheral driving circuits 710, and the control signals output by different peripheral driving circuits 710 may be different. Specifically, the peripheral driving circuit 710 includes a second scanning driving circuit 710c and a light emission control driving circuit 710a. The second scanning driving circuit 710c transmits the output control signal to the second scanning transistor 252, and the light emission control driving circuit 710a transmits the output control signal to the light emission control transistor 253, so as to ensure that the peripheral driving circuit 710 controls the driving circuit 200 and drives the light emitting element 400 to ensure the display effect of the display panel 10.

[0078] Exemplarily, in combination with Figure 3 、 Figure 7 、 Figure 9 、 Figure 18 and Figure 20 as shown, the second scanning driving circuit 710c is connected to the control end of the second scanning transistor 252 (exemplified by the data writing transistor M2 in Figure 3 ) through the second scanning signal line s2 (exemplified by Sp in Figure 3 ). The light emission control driving circuit 710a is connected to the control end of the light emission control transistor 253 (exemplified by the light emission control transistor M1 in Figure 3 ) through the light emission control signal line Emit (exemplified by Emit in Figure 3 ).

[0079] Furthermore, the peripheral shielding sub-structure 330 may include a second peripheral shielding sub-structure 330b and a third peripheral shielding sub-structure 330c, where the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scanning driving circuit 710c, and the third peripheral shielding sub-structure 330c overlaps with the channel region of the transistor in the light emission control driving circuit 710a. Exemplarily, referring to Figure 20 as shown, Figure 20 in

[0080] the cross-sectional views of the second scanning driving circuit 710c and the third scanning driving circuit 710a are placed in one figure for easy observation. Figure 20As shown, the second peripheral shielding sub-structure 330b and the third peripheral shielding sub-structure 330c are respectively disposed in different peripheral driving circuits 710, and the connection of the second peripheral shielding sub-structure 330b and the third peripheral shielding sub-structure 330c to different potential signal terminals can be adjusted ( Figure 20 the different potential signal terminals in are shown as B5 and B6). Specifically, the control signals output by different peripheral driving circuits 710 are different, and specific limitations are made in combination with the type of the actual peripheral driving circuit 710. Generally speaking, according to the differences of the peripheral driving circuits 710, the potential signals accessed by the peripheral shielding sub-structures 330 disposed in the peripheral driving circuits 710 are differentially set, which can better ensure the reliability and stability of the signals output by the peripheral driving circuits 710, and further ensure the overall display effect of the display panel 10.

[0081] Continue to refer to Figure 1 、 Figure 3 、 Figure 7 、 Figure 9 、 Figure 18 and Figure 20 shown, the second scanning transistor 252 includes a data writing transistor M2; the potential signal of the third peripheral shielding sub-structure 330c is greater than the potential signal of the second peripheral shielding sub-structure 330b.

[0082] Among them, referring to Figure 3 shown, in the driving circuit 200, the second scanning transistor 252 can be a data writing transistor M2, and the light emitting control transistor 253 can be a light emitting control transistor M1. Based on the differences between the second scanning transistor 252 and the light emitting control transistor 253 in the driving circuit 200, the magnitude of the potential signals of the peripheral shielding sub-structures 330 correspondingly arranged in the peripheral driving circuit 710 can be adjusted accordingly. Specifically, the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scanning driving circuit 710c, and the third peripheral shielding sub-structure 330c overlaps with the channel region of the transistor in the light emitting control driving circuit 710a. The potential signal of the third peripheral shielding sub-structure 330c can be adjusted to be greater than the potential signal of the second peripheral shielding sub-structure 330b, so as to ensure that the peripheral driving circuits 710 of the entire display panel 10 can output stable control signals and ensure the display effect of the display panel 10.

[0083] Figure 21 is Figure 9 another cross-sectional schematic diagram along the section line C-C' in, referring to Figure 1 、 Figure 3 、 Figure 7 、 Figures 9 to 18 、 Figure 21As shown, the peripheral driving circuit 710 further includes a first scan driving circuit 710b, the driving circuit 200 further includes a first scan transistor 251, and the first scan driving circuit 710b is connected to the control terminal of the first scan transistor 251 through a first scan signal line s1; the peripheral shielding sub-structure 330 further includes a first peripheral shielding sub-structure 330a corresponding to the first scan driving circuit 710b; the first peripheral shielding sub-structure 330a and the third peripheral shielding sub-structure 330c are connected to different potential signals.

[0084] Specifically, the driving circuit 200 may include a first scan transistor 251, a second scan transistor 252, and a light-emitting control transistor 253, and the corresponding peripheral driving circuit 710 may correspondingly include a first scan driving circuit 710b, a second scan driving circuit 710c, and a light-emitting control driving circuit 710a.

[0085] Further, the peripheral shielding sub-structure 330 may include a first peripheral shielding sub-structure 330a, a second peripheral shielding sub-structure 330b, and a third peripheral shielding sub-structure 330c, wherein the first peripheral shielding sub-structure 330a overlaps with the channel region of the transistor in the first scan driving circuit 710b, the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scan driving circuit 710c, and the third peripheral shielding sub-structure 330c overlaps with the channel region of the transistor in the light-emitting control driving circuit 710a. Exemplarily, referring to Figure 21 as shown, Figure 21 the cross-sectional views of the first scan driving circuit 710b, the second scan driving circuit 710c, and the third scan driving circuit 710a are placed in one figure for easy observation. And in combination with Figures 10 to 12 or Figures 15 to 17 as shown, the film layer structure shows three different peripheral driving circuits 710.

[0086] Further, referring to Figure 21 as shown, if the first peripheral shielding sub-structure 330a, the second peripheral shielding sub-structure 330b, and the third peripheral shielding sub-structure 330c are respectively placed in different peripheral driving circuits 710, then the potential signal terminals to which the first peripheral shielding sub-structure 330a, the second peripheral shielding sub-structure 330b, and the third peripheral shielding sub-structure 330c are connected can be adjusted ( Figure 21The different potential signal terminals are shown as B4, B5, and B6). Specifically, the control signals output by different peripheral driving circuits 710 are different, and specific limitations are made in combination with the type of the actual peripheral driving circuit 710. Generally speaking, according to the differences of the peripheral driving circuit 710, the potential signals accessed by the peripheral shielding sub-structure 330 arranged in the peripheral driving circuit 710 are set differently, which can better ensure the reliability and stability of the signals output by the peripheral driving circuit 710, and further ensure the overall display effect of the display panel 10.

[0087] Continue to refer to Figure 1 、 Figure 3 、 Figures 8 to 18 、 Figure 21 As shown, the potential signal of the second peripheral shielding sub-structure 330b is greater than or equal to the potential signal of the first peripheral shielding sub-structure 330a.

[0088] Among them, referring to Figure 3 As shown, in the driving circuit 200, the first scanning transistor 251 can be the initialization transistor M5, the second scanning transistor 252 can be the data writing transistor M2, and the light emission control transistor 253 can be the light emission control transistor M1. Based on the differences of the first scanning transistor 251, the second scanning transistor 252, and the light emission control transistor 253 in the driving circuit 200, the magnitude of the potential signal of the corresponding peripheral shielding sub-structure 330 arranged in the peripheral driving circuit 710 can be correspondingly adjusted. Specifically, the first peripheral shielding sub-structure 330a overlaps with the channel region of the transistor in the first scanning driving circuit 710b, the second peripheral shielding sub-structure 330b overlaps with the channel region of the transistor in the second scanning driving circuit 710c, and the third peripheral shielding sub-structure 330c overlaps with the channel region of the transistor in the light emission control driving circuit 710a. The potential signal of the third peripheral shielding sub-structure 330c can be adjusted to be greater than the potential signal of the second peripheral shielding sub-structure 330b. At the same time, the potential signal of the second peripheral shielding sub-structure 330b is greater than or equal to the potential signal of the first peripheral shielding sub-structure 330a, so as to ensure that the overall peripheral driving circuit 710 of the display panel 10 can output stable control signals and ensure the display effect of the display panel 10.

[0089] Figure 22 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 3 、 Figure 18 and Figure 22As shown, the non-display area 100B includes a first non-display area 100B1 and a second non-display area 100B2 located on opposite sides of the display area 100A; the peripheral circuit group 700 further includes two second scan driver circuit groups, and one of the second scan driver circuit groups 720 is located in the first non-display area 100B1, and the other second scan driver circuit group 720 is located in the second non-display area 100B2. Each second scan driver circuit group 720 includes a plurality of second scan driver circuits 710c arranged in the first direction X and cascaded; the driver circuit 200 includes a second scan transistor 252. The second scan driver circuit 710c is connected to the control end of the second scan transistor 252 through a second scan signal line s2, and one end of the second scan signal line s2 is connected to the second scan driver circuit 710c located in the first non-display area 100A1, and the other end is connected to the second scan driver circuit 710c located in the second non-display area 100B2.

[0090] Specifically, referring to Figure 22 As shown, the display panel 10 includes a first non-display area 100B1 and a second non-display area 100B2 in the non-display area 100B, and the first non-display area 100B1 and the second non-display area 100B2 are located on both sides of the display area 100A.

[0091] Furthermore, the peripheral circuit group 700 may include a second scan driver circuit 720, and the second scan driver circuit group 720 includes a plurality of second scan driver circuits 710c arranged in the first direction X and cascaded. Referring to Figure 22 As shown, the peripheral circuit group 700 may include two second scan driver circuits 720, and the two second scan driver circuits 720 are respectively located in the first non-display area 100B1 and the second non-display area 100B2. It can be understood that the second scan driver circuit 710c is a peripheral driver circuit with bilateral drive, which ensures the driving effect of the second scan driver circuit 710c and the display effect of the display panel 10.

[0092] Specifically, the driver circuit 200 in the display area 100A includes a second scan transistor 252. The second scan driver circuit 710c located in the first non-display area 100B1 can be connected to the control end of the second scan transistor 252 through a second scan signal line s2, and at the same time, the second scan driver circuit 710c located in the second non-display area 100B2 can also be connected to the control end of the second scan transistor 252 through a second scan signal line s2, so as to ensure that the driving effect on the driver circuit 200 is more stable.

[0093] Figure 23 is Figure 22 a schematic cross-sectional view along the section line I-I' in Figure 24 is Figure 22A schematic cross-sectional view along the section line K-K', refer to Figures 22 to 24 As shown, the peripheral shielding sub-structure 330 includes a second peripheral shielding sub-structure 330b corresponding to the second scan driving circuit 710c; the second peripheral shielding sub-structure 330b located in the first non-display area 100B1 and the second peripheral shielding sub-structure 330b located in the second non-display area 100B2 are connected to different potential signal terminals.

[0094] Specifically, refer to Figures 22 to 24 As shown, the second scan driving circuit 710c exists in the first non-display area 100B1 and the second non-display area 100B2. At the same time, the peripheral shielding sub-structure 330 includes a second peripheral shielding sub-structure 330b corresponding to the second scan driving circuit 710c. That is, a second peripheral shielding sub-structure 330b is correspondingly provided in the second scan driving circuit 710c in both the first non-display area 100B1 and the second non-display area 100B2. Thereby ensuring the driving stability of the second scan driving circuit 710c at each position and ensuring the display effect of the display panel 10.

[0095] Furthermore, there will be differences between the second scan driving circuits 710c located in the first non-display area 100B1 and the second display area 100B2, such as differences in setting positions, or differences in the total number of settings, etc. The embodiments of the present invention do not specifically limit this. It is possible to adjust the second peripheral shielding sub-structure 330b located in the first non-display area 100B1 and the second peripheral shielding sub-structure 330b located in the second non-display area 100B2 to be connected to different potential signal terminals (refer to B5' in Figure 23 and B5" in Figure 24 ). In this way, according to the differential settings of different third scan driving circuits 710b, the corresponding second peripheral shielding sub-structure 330b can be adaptively adjusted to access differential potential signals, thereby better ensuring the driving effect of the peripheral driving circuit 710 and ensuring the overall display effect of the display panel 10.

[0096] Figure 25 is a schematic structural view of another display panel provided by the embodiments of the present invention, refer to Figure 25As shown, the peripheral circuit group 700 further includes a first scan driving circuit group 730 located in the first non-display area 100B1. The first scan driving circuit group 730 includes a plurality of first scan driving circuits 710b arranged along the first direction X and cascaded. The driving circuit 200 includes a first scan transistor 251. The first scan driving circuit 710b is connected to the control end of the first scan transistor 251 through a first scan signal line s1. The potential signal of the second peripheral shielding sub-structure 330b located in the second non-display area 100B2 is greater than the potential signal of the second peripheral shielding sub-structure 330b located in the first non-display area 100B1.

[0097] Further, the peripheral circuit group 700 may further include a first scan driving circuit group 730. The first scan driving circuit group 730 includes a plurality of first scan driving circuits 710b arranged along the first direction X and cascaded. Refer to Figure 25 As shown, the first scan driving circuit group 730 may be located in the first non-display area 100B1. It can be understood that the first scan driving circuit 710b is a peripheral driving circuit with single-sided driving. Thus, refer to Figure 25 As shown, the first scan driving circuit group 730 and the second scan driving circuit group 720 are included in the first non-display area 100B1, while only the second scan driving circuit group 720 is included in the second non-display area 100B2. Therefore, in different non-display areas 100B of the display panel 10, the settings of the peripheral driving circuit 710 are different.

[0098] Further, the driving circuit 200 in the display area 100A further includes a first scan transistor 251. The first scan driving circuit 710b located in the first non-display area 100B1 can be connected to the control end of the first scan transistor 251 through a first scan signal line s1, so as to realize the driving of the driving circuit 200.

[0099] Among them, refer to Figure 25 As shown, if the first scan driving circuit 710a is only located at the first non-display area 100B1, then the driving effect of the first scan driving circuit 710b on the driving circuit 200 in the display area 100A will gradually weaken due to the increase of the load. The driving effect of the driving circuit 200 close to the first scan driving circuit 710b will be better than that of the driving circuit 200 far from the first scan driving circuit 710b. Further, refer to Figure 25As shown, the second scan driving circuit 710c can be present in both the first non-display area 100B1 and the second non-display area 100B2, and the peripheral shielding sub-structure 330 includes a second peripheral shielding sub-structure 330b corresponding to the second scan driving circuit 710c. That is, the second peripheral shielding sub-structure 330b is correspondingly arranged in the second scan driving circuit 710c located in both the first non-display area 100B1 and the second non-display area 100B2. In this way, the potential signal of the second peripheral shielding sub-structure 330b located in the second non-display area 100B2 can be adjusted to be greater than the potential signal of the second peripheral shielding sub-structure 330b located in the first non-display area 100B1, ensuring the driving effect of the overall peripheral driving circuit 710 on the driving circuit 200.

[0100] It can be understood that the first scan driving circuit 710b is included in the first non-display area 100B1, while the first scan driving circuit 710b is not provided in the second non-display area 100B2. Therefore, the driving effect of the first scan driving circuit 710b on the driving circuit 200 in the display area 100A will gradually weaken due to the increase in load. The second scan driving circuit 710c is provided in both the first non-display area 100B1 and the second non-display area 100B2, and the potential signal of the second peripheral shielding sub-structure 330b corresponding to the second scan driving circuit 710c in the second non-display area 100B2 is adjusted to be slightly larger, which is equivalent to compensating for the insufficient driving caused by the load problem of the first scan driving circuit 710b and improving the driving effect. In this way, the driving effect of the overall peripheral driving circuit 710 on the driving circuit 200 can be balanced, ensuring the display effect of the display panel 10.

[0101] It should be noted that the setting positions of the first scan driving circuit 710b and the second scan driving circuit 710c in the first non-display area 100B1 of the display panel 10 can be adjusted adaptively, and the embodiments of the present invention do not specifically limit this.

[0102] Optionally, the potential signal accessed by the peripheral shielding sub-structure 330 is V, where 0 < V ≤ 4.6v.

[0103] Specifically, the potential signal accessed by the peripheral shielding sub-structure 330 can be between 0 and 4.6v. For example, the potential signal can be 1v, 2v, 2.5v, 3v, or 4v, etc. The specific potential signal accessed by the peripheral shielding sub-structure 330 can be adjusted adaptively according to the actual situation.

[0104] Figure 26 is a schematic structural diagram of another display panel provided by the embodiments of the present invention. Refer to Figure 26As shown, the non-display area 100B further includes a bonding area 100C. The bonding area 100C is located in the lower border area of the display panel 10, and at least one potential signal terminal B is provided in the bonding area 100C; the peripheral shielding sub-structure 330 is connected to the potential signal terminal B through a first signal line 800.

[0105] Among them, referring to Figure 26 As shown, the non-display area 100B further includes a bonding area 100C. At least one potential signal terminal B is provided in the bonding area 100C, and the potential signal terminal B is used to provide a potential signal. Specifically, referring to Figure 26 As shown, the potential signal terminal B in the bonding area 100C can transmit the potential signal to the peripheral shielding sub-structure 330 through the first signal line 800, so as to ensure that the shielding sub-structure 330 has a potential signal, which can play the role of electrical signal shielding, ensure the working stability of the peripheral driving circuit 710, and ensure the display effect of the display panel 10. Based on the electrical connection method between the shielding sub-structure 330 and the potential signal terminal B, there can be diversity, that is, the setting of the first signal line 800 has diversity.

[0106] Continue to refer to Figure 26 As shown, the peripheral circuit group 700 includes the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j). The i-th peripheral driving circuit 710(i) is located on the side of the j-th peripheral driving circuit 710(j) close to the bonding area 100C; the peripheral shielding sub-structure 330 includes the x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y). The x-th peripheral shielding sub-structure 330(x) at least partially overlaps with the channel region of the first transistor 230 in the i-th peripheral driving circuit 710(i), and the y-th peripheral shielding sub-structure 330(y) at least partially overlaps with the channel region of the first transistor 330 in the j-th peripheral driving circuit 710(j); the x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y) are respectively connected to the first signal line 800 through a patch cord 900; among them, the first signal line 800 extends along the first direction X, the patch cord 900 extends along the second direction Y, the second direction Y intersects with the first direction X, and the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A.

[0107] Specifically, referring to Figure 26 As shown, a peripheral circuit group 700 may include a plurality of peripheral driving circuits 710 arranged along the first direction X and cascaded. Combining Figure 26As shown, the peripheral circuit group 700 includes the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j), and the position of the i-th peripheral driving circuit 710(i) is closer to the bonding area 100C than the position of the j-th peripheral driving circuit 710(j).

[0108] Furthermore, the peripheral shielding sub-structure 330 includes the x-th peripheral shielding sub-structure 330(x) that at least partially overlaps with the channel region of the first transistor 230 in the i-th peripheral driving circuit 710(i), and also includes the y-th peripheral shielding sub-structure 330(y) that at least partially overlaps with the channel region of the first transistor 330 in the j-th peripheral driving circuit 710(j). Considering the positional relationship between the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j), it can be known that the x-th peripheral shielding sub-structure 330(x) is located on the side closer to the bonding area 100C of the y-th peripheral shielding sub-structure 330(y).

[0109] Furthermore, referring to Figure 26 As shown, the display panel 10 includes a first signal line 800 extending along the first direction X. The first signal line 800 is electrically connected to the potential signal terminal B, that is, the electrical signal provided by the potential signal terminal B is transmitted in the first signal line 800. If it is necessary to access the potential signal provided by the potential signal terminal B in the peripheral shielding sub-structure 330, then adjust the electrical connection relationship between the peripheral shielding sub-structure 330 and the first signal line 800. Specifically, referring to Figure 26 As shown, the peripheral shielding sub-structure 330 is electrically connected to the first signal line 800 through a jumper wire 900 extending along the second direction Y. Among them, the x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y) are respectively connected to the first signal line 800 through a jumper wire 900. That is, it can be understood that the peripheral shielding sub-structures 330 located in different peripheral driving circuits 710 are respectively electrically connected to the first signal line 800 through the conversion wire 900. In this way, the voltage drop of the electrical signal provided by the potential signal terminal B on the transmission path of the first signal line 800 is small, which can ensure that the potential signals received by different peripheral shielding sub-structures 330 are the same or similar, ensure the shielding effect of the peripheral shielding sub-structure 330, ensure the working stability of the peripheral driving circuit 710, and further ensure the display effect of the display panel 10.

[0110] It should be noted that the peripheral driving circuit 710 may include multiple first transistors 230. Therefore Figure 26 the area where the corresponding peripheral shielding sub-structure 330 is shown for each peripheral driving circuit 710 can be understood as all the peripheral shielding sub-structures 330 corresponding to the peripheral driving circuit 710.

[0111] Figure 27It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 28 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 27 and Figure 28 As shown, the peripheral circuit group 700 includes the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j). The i-th peripheral driving circuit 710(i) is located on the side of the j-th peripheral driving circuit 710(j) close to the bonding area 100C; the peripheral shielding sub-structure 330 includes the x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y). The x-th peripheral shielding sub-structure 330(x) at least partially overlaps with the channel region of the first transistor 230 in the i-th peripheral driving circuit 710(i), and the y-th peripheral shielding sub-structure 330(y) at least partially overlaps with the channel region of the first transistor 330 in the j-th peripheral driving circuit 710(j); each peripheral shielding sub-structure 330 includes a main structure 331 and a plurality of sub-structures 332 connected to the main structure 331. Each sub-structure 332 at least partially overlaps with the channel region of the first transistor 230. The x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y) are connected through the main structure 331 and are connected to the first signal line 800 through the main structure 331.

[0112] Furthermore, refer to Figure 27 and Figure 28 As shown, the peripheral shielding sub-structure 330 includes a main structure 331 and a sub-structure 332, wherein the sub-structure 332 at least partially overlaps with the channel region of the first transistor 230. Refer to Figure 27 and Figure 28 As shown, the x-th peripheral shielding sub-structure 330(x) and the y-th peripheral shielding sub-structure 330(y) can be understood as the sub-structures 332 in the peripheral shielding sub-structure 330. Furthermore, the sub-structure 332 and the main structure 331 are in an electrically connected relationship. Combining Figure 27 and Figure 28 As shown, the main structure 331 can be understood as a bridge connecting two adjacent sub-structures 332. Thus, in the peripheral circuit group 700, the multiple peripheral driving circuits 710 are arranged in a cascaded relationship, and the peripheral shielding sub-structures 330 corresponding to each peripheral driving circuit 710 are in an electrically connected relationship. On this basis, if a potential signal needs to be provided to the peripheral shielding sub-structure 330, it can be provided only to the main structure 331 to ensure that the entire peripheral shielding sub-structure 330 has a potential signal, achieving the shielding effect and ensuring the working stability of the peripheral driving circuit 710, and further ensuring the display effect of the display panel 10.

[0113] Specifically, refer to Figure 27As shown, the main structure 331 is electrically connected to the first signal line 800, and the first signal line 800 is electrically connected to the potential signal terminal B, so as to ensure that the main structure 331 obtains the potential signal, and then the entire peripheral shielding sub-structure 330 obtains the potential signal. With this setting method, there is no need to set extra traces at each peripheral shielding sub-structure 330 to maintain electrical connection with the first signal line 800, reducing the space of the non-display area 100B occupied by the traces, which is beneficial to realizing the narrow-bezel display panel 10, and at the same time saving the process preparation cost of the display panel 10.

[0114] Continue to refer to Figure 27 and Figure 28 As shown, the first signal line 800 is located between the peripheral driving circuit 710 and the bonding area 100C; alternatively, the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A and extends along the first direction X, and the main structure 331 is connected to one end of the first signal line 800 away from the bonding area 100C.

[0115] Further, refer to Figure 27 As shown, the first signal line 800 is located between the peripheral driving circuit 710 and the bonding area 100C, that is, the first signal line 800 is electrically connected to the peripheral shielding sub-structure 330 through the main structure 331 near the bonding area 100C. In this way, the extension length of the first trace 800 can be reduced, which is beneficial to saving the space occupied by the trace in the non-display area 100B, beneficial to realizing the narrow-bezel design of the display panel 10, and at the same time reducing the process preparation cost of the display panel 10. Or refer to Figure 28 As shown, the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A and extends along the first direction X, and the main structure 331 is connected to one end of the first signal line 800 away from the bonding area 100C, that is, the first signal line 800 is electrically connected to the peripheral shielding sub-structure 330 through the main structure 331 away from the bonding area 100C, reflecting the flexibility of the routing setting of the first signal line 800, which can be adaptively adjusted according to the requirements of different display panels 10.

[0116] Based on the same concept, the embodiment of the present invention also provides a display device. Figure 29 It is a schematic structural diagram of a display device provided by the embodiment of the present invention. As Figure 29 shown, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided by the embodiment of the present invention has the corresponding beneficial effects in the above embodiments, which will not be elaborated here. Exemplarily, the display device 1 may be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, etc., and the embodiment of the present invention does not limit this.

[0117] Note that the above is only the preferred embodiment of the present utility model and the applied technical principles. Those skilled in the art will understand that the present utility model is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present utility model. Therefore, although the present utility model has been described in detail through the above embodiments, the present utility model is not limited to the above embodiments. Without departing from the concept of the present utility model, more other equivalent embodiments can be included, and the scope of the present utility model is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: It includes a substrate and a driving array arranged on one side of the substrate, wherein the driving array includes transistors; The display panel further comprises a shielding structure disposed on a side of the substrate close to the driving array, the shielding structure comprising at least one shielding substructure, and the shielding substructure at least partially overlaps with a channel region of the transistor; The shielding substructure is connected to the potential signal terminal; The display panel comprises a display area and non-display areas located on both sides of the display area; The driving array includes a driving circuit located in the display area and a peripheral circuit group located in the non-display area, the peripheral circuit group includes a plurality of peripheral driving circuits arranged in a first direction and cascaded, and the peripheral driving circuit includes a plurality of first transistors; The shielding substructures include a plurality of peripheral shielding substructures, the peripheral shielding substructures at least partially overlapping a channel region of the first transistor; The first direction is parallel to the plane where the substrate is located.

2. The display panel according to claim 1, characterized in that: In the same peripheral driving circuit, a plurality of peripheral shielding substructures at least partially overlapping with the channel regions of a plurality of the first transistors are electrically connected to each other.

3. The display panel according to claim 2, characterized in that: The peripheral driving circuit further includes at least one second transistor; The second transistor comprises an active layer, a bottom gate and a top gate; the bottom gate is located between the active layer and the substrate, the top gate is located on a side of the active layer away from the substrate, and the bottom gate is electrically connected to the top gate in the same second transistor; The bottom gate is formed in the same layer as the peripheral shielding substructure, and the bottom gate is insulated from the peripheral shielding substructure.

4. The display panel according to claim 1, characterized in that: The peripheral driving circuit includes a first scanning driving circuit and a second scanning driving circuit, and the driving circuit includes a first scanning transistor and a second scanning transistor; The first scan driving circuit is connected to the control end of the first scan transistor through a first scan signal line, and the second scan driving circuit is connected to the control end of the second scan transistor through a second scan signal line; The peripheral shielding substructure comprises a first peripheral shielding substructure arranged corresponding to the first scan driving circuit and a second peripheral shielding substructure arranged corresponding to the second scan driving circuit; The first perimeter shielding substructure and the second perimeter shielding substructure are connected to different potential signal terminals.

5. The display panel according to claim 4, characterized in that: The first scanning transistor includes an initialization transistor, and the second scanning transistor includes a data writing transistor; The potential signal of the second peripheral shielding substructure is greater than the potential signal of the first peripheral shielding substructure.

6. The display panel according to claim 1, characterized in that: The peripheral driving circuit includes a second scanning driving circuit and a light emitting control driving circuit, and the driving circuit includes a second scanning transistor and a light emitting control transistor; The second scan drive circuit is connected to the control end of the second scan transistor through a second scan signal line, and the light emission control drive circuit is connected to the control end of the light emission control transistor through a light emission control signal line; The peripheral shielding substructure comprises a second peripheral shielding substructure arranged corresponding to the second scanning driving circuit and a third peripheral shielding substructure arranged corresponding to the light emitting control driving circuit; The second perimeter shielding substructure and the third perimeter shielding substructure are connected to different potential signal terminals.

7. The display panel according to claim 6, characterized in that: The second scanning transistor includes a data writing transistor; The potential signal of the third peripheral shielding substructure is greater than the potential signal of the second peripheral shielding substructure.

8. The display panel according to claim 6 or 7, characterized in that: The peripheral driving circuit further includes a first scanning driving circuit, the driving circuit further includes a first scanning transistor, and the first scanning driving circuit is connected to the control end of the first scanning transistor through a first scanning signal line; The peripheral shielding substructure further includes a first peripheral shielding substructure arranged corresponding to the first scan driving circuit; The first perimeter shielding substructure and the third perimeter shielding substructure are connected to different potential signal terminals.

9. The display panel according to claim 8, characterized in that: The potential signal of the second peripheral shielding substructure is greater than or equal to the potential signal of the first peripheral shielding substructure.

10. The display panel according to claim 1, characterized in that: The non-display area includes a first non-display area and a second non-display area located at opposite sides of the display area; The peripheral circuit group further includes two second scan drive circuit groups, one of which is located in the first non-display area, and the other is located in the second non-display area, each of which includes a plurality of second scan drive circuits arranged in a first direction and cascaded; The driving circuit includes a second scanning transistor, which is connected to the control end of the second scanning transistor through a second scanning signal line, and one end of the second scanning signal line is connected to the second scanning driving circuit located in the first non-display area, and the other end is connected to the second scanning driving circuit located in the second non-display area.

11. The display panel according to claim 10, characterized in that: The peripheral shielding substructure includes a second peripheral shielding substructure arranged corresponding to the second scan driving circuit; The second peripheral shielding substructure located in the first non-display area and the second peripheral shielding substructure located in the second non-display area are connected to different potential signal terminals.

12. The display panel according to claim 11, characterized in that: The peripheral circuit group further includes a first scan driving circuit group located in the first non-display area, the first scan driving circuit group including a plurality of first scan driving circuits arranged in cascade along the first direction; The drive circuit includes a first scan transistor, and the first scan drive circuit is connected to a control terminal of the first scan transistor through a first scan signal line; A potential signal of the second peripheral shielding substructure located in the second non-display area is greater than a potential signal of the second peripheral shielding substructure located in the first non-display area.

13. The display panel according to claim 1, characterized in that: The potential signal connected to the peripheral shielding substructure is V, Among them, 0<V≤4.6v.

14. The display panel according to claim 1, characterized in that: The non-display area further includes a binding area, the binding area is located in the lower frame area of ​​the display panel, and the binding area is provided with at least one potential signal terminal; The peripheral shielding substructure is connected to the potential signal terminal through a first signal line.

15. The display panel according to claim 14, characterized in that: The peripheral circuit group includes an i-th peripheral driving circuit and a j-th peripheral driving circuit, and the i-th peripheral driving circuit is located on a side of the j-th peripheral driving circuit close to the binding area; The peripheral shielding substructure includes an xth peripheral shielding substructure and a yth peripheral shielding substructure, the xth peripheral shielding substructure at least partially overlaps with the channel region of the first transistor in the i-th peripheral driving circuit, and the yth peripheral shielding substructure at least partially overlaps with the channel region of the first transistor in the j-th peripheral driving circuit; The xth peripheral shielding substructure and the yth peripheral shielding substructure are respectively connected to the first signal line via a patch cord; The first signal line extends along the first direction, the adapter line extends along a second direction, the second direction intersects the first direction, and the first signal line is located on a side of the peripheral driving circuit away from the display area.

16. The display panel according to claim 14, characterized in that: The peripheral circuit group includes an i-th peripheral driving circuit and a j-th peripheral driving circuit, and the i-th peripheral driving circuit is located on a side of the j-th peripheral driving circuit close to the binding area; The peripheral shielding substructure includes an xth peripheral shielding substructure and a yth peripheral shielding substructure, the xth peripheral shielding substructure at least partially overlaps with the channel region of the first transistor in the i-th peripheral driving circuit, and the yth peripheral shielding substructure at least partially overlaps with the channel region of the first transistor in the j-th peripheral driving circuit; Each of the peripheral shielding substructures includes a main structure and multiple substructures connected to the main structure, each of the substructures at least partially overlaps with the channel region of the first transistor, the x-th peripheral shielding substructure and the y-th peripheral shielding substructure are connected through the main structure, and are connected to the first signal line through the main structure.

17. The display panel according to claim 16, characterized in that: The first signal line is located between the peripheral driving circuit and the binding area; or, The first signal line is located at a side of the peripheral driving circuit away from the display area and extends along the first direction, and the main structure is connected to an end of the first signal line away from the binding area.

18. A display device, characterized in that: A display panel comprising any one of claims 1-17.

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