Double-gear peak detection circuit for gain control

Abstract

The utility model relates to the technical field of measuring range control, in particular to a double-gear peak detection circuit for gain control. The circuit comprises a filter circuit, a comparison circuit and a level output circuit. Four paths of signals are output after sampling signals pass through the filter circuit and are respectively connected with the input end of the comparison circuit; the comparison circuit comprises a reference voltage module and a U1 module, the input end of the U1 module is connected with four paths of signals of the corresponding comparison circuit, and two paths of signals of the reference voltage module and two paths of signals output by the U1 module are respectively connected with the input end of the level output circuit; a first group of levels of the level output circuit output peak analog signals; a second set of levels of the level output circuit output a peak digital signal. Two groups of different signal characteristics are compared with voltage through the filter circuit, the comparison circuit and the level output circuit, peak-to-peak value judgment of various signals can be dealt with, and a digital system is helped to control gain to a proper gear.

Description

Technical Field

[0001] The utility model relates to the technical field of range control, and particularly relates to a dual-range peak detection circuit for gain control. Background Art

[0002] Measuring instruments need to ensure that the amplitude of the sampled signal is within an appropriate range to prevent analog conversion overflow and ensure accurate conversion. Gain control is crucial and includes analog, digital, and hybrid control strategies. Facing complex requirements, a single mode is difficult to meet both high performance and low complexity. Chinese Patent CN218445799U proposes a multi-channel peak detection scheme based on ZYNQ, integrating filtering, conditioning, comparison, and ZYNQ chips to improve the system adaptability. However, analog control is complex and digital response is slow, so it is necessary to explore a digital-analog hybrid scheme to balance simplicity and response speed to achieve more efficient gain control. Content of the Utility Model

[0003] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide a dual-range peak detection circuit for gain control.

[0004] The technical scheme adopted by the utility model is as follows:

[0005] A dual-range peak detection circuit for gain control includes a filtering circuit, a comparison circuit, and a level output circuit; the sampled signal outputs four signals after passing through the filtering circuit, which are respectively connected to the input ends of the comparison circuit; the comparison circuit includes a reference voltage module and a U1 module, the input end of the reference voltage module is connected to the reference voltages -5V and +5V, and the output end of the reference voltage module is connected to the U1 module; the input end of the U1 module is connected to the four signals of the corresponding comparison circuit and the two signals of the reference voltage module, and the U1 module outputs two signals, which are respectively connected to the input ends of the level output circuit; the first group of the level output circuit outputs an analog signal of the peak value; the second group of the level output circuit outputs a digital signal of the peak value.

[0006] This technical solution realizes a gain control scheme with low cost and high-speed response in the way of combining signal feature extraction circuit and digital signal processing. It can hand over the peak-to-peak feature of the sampling signal to the digital system for processing, and the digital system controls the gain amplification to make the sampling signal within the effective range of analog conversion. This technical solution detects the peak-to-peak value of the signal through a filter circuit, a comparison circuit and a level output circuit and converts it into a digital signal to help the digital system achieve gain control. Specifically, the U1 module is an integrated circuit with multiple comparators. Each comparator is responsible for comparing a filtered signal with a reference voltage. By adjusting the reference voltage or the threshold of the comparator, different peak detection gears can be set. The first group outputs an analog signal of the peak value, which is selected from the output of the comparison circuit through an analog multiplexer and represents the analog representation of the actually detected peak value. The second group outputs a digital signal of the peak value, and the result of converting the analog signal into a digital signal is realized through an analog-to-digital converter (ADC), which converts the output of the comparison circuit into a digital signal.

[0007] In addition, the dual-gear peak detection circuit for gain control proposed above according to the present utility model may further have the following additional technical features:

[0008] According to an embodiment of the present utility model, the filter circuit adopts an RC filter circuit. The sampling signal is connected to R5 and C1 after passing through R1, and the other ends of R5 and C1 are connected to GND to form a filter.

[0009] In this technical solution, the RC filter circuit realizes filtering through the charging and discharging process of the capacitor C1. When the sampling signal passes through R1, most of the high-frequency signals are bypassed to the ground due to the "short-circuit" effect of the capacitor C1, while the low-frequency signals can pass through the network composed of R5 and C1 more because of the higher impedance of the capacitor, thus achieving the effect of low-pass filtering. The cut-off frequency (fc) of the filter is the key parameter for distinguishing high- and low-frequency signals, which is jointly determined by the values of R5 and C1. According to the formula fc = 1 / (2πR5C1), the cut-off frequency can be changed by adjusting the value of R5 or C1. Signals below the cut-off frequency can pass through the filter relatively completely, while signals above the cut-off frequency will be greatly attenuated. While filtering, the RC filter will also introduce a phase delay because the capacitor C1 requires a certain amount of time during the charging and discharging process, resulting in a certain time lag of the output signal relative to the input signal.

[0010] According to an embodiment of the present utility model, the output terminals of the filter are respectively connected to pins 5, 6, 9, and 10 of the U1 module.

[0011] This technical solution realizes the specific distribution of the filtered signal to the U1 module by connecting the output terminals of the filter to pins 5, 6, 9, and 10 of the U1 module respectively, providing multiple inputs for subsequent peak detection or signal processing.

[0012] According to an embodiment of the present utility model, the U1 module uses a UPC339 chip. The reference voltages of -5V and +5V are respectively connected to pins 4 and 7. The reference voltage of -5V is connected to pins 8 of R8, C2 and U1 after passing through R7. The other ends of R8 and C2 are connected to GND. The reference voltage of +5V is connected to pins 11 of R13, C13 and U1 after passing through R12. The other ends of R13 and C11 are connected to GND.

[0013] This technical solution uses a UPC339 chip as the U1 module, and connects the reference voltages of -5V and +5V to the specified pins (4, 7, 8, 11) of the chip through a specific resistor and capacitor network, constructing a stable reference voltage source. Through filtering processing, the stability and accuracy of the reference voltage are ensured, providing a benchmark for the comparison and detection functions in the circuit.

[0014] According to an embodiment of the present utility model, a group of pins 1 and 2 in the U1 module are connected to the base of R3 and Q1 after passing through R4. The other end of R3 is connected to the reference voltage of +5V. The reference voltage of +5V is connected to the emitter of R6 and Q1 after passing through R2, which is the first group of level outputs.

[0015] This technical solution connects a group of pins 1 and 2 in the U1 module to the base of the resistor R4, R3 and the transistor Q1, constructing a driving circuit for the first group of level outputs. The reference voltage of +5V provides a bias for the emitter of Q1 through R2 and R6, realizing the level conversion and amplification of the output signal based on the U1 module, and providing the necessary driving ability for the first group of level outputs.

[0016] According to an embodiment of the present utility model, a group of pins 13 and 14 in the U1 module are connected to the base of R10 and Q2 after passing through R11. The other end of R10 is connected to the reference voltage of +5V. The reference voltage of +5V is connected to the emitter of R14 and Q2 after passing through R9. The other end of R14 is connected to the collector of Q2 and GND, which is the second group of level outputs.

[0017] This technical solution connects another group of pins 13 and 14 in the U1 module to the base of the resistor R11, R10 and the transistor Q2, constructing a driving circuit for the second group of level outputs. Similar to the first group, the reference voltage of +5V provides a bias and loop for the emitter and collector of Q2 through R9 and R14, realizing the level conversion and amplification of another output signal based on the U1 module, and providing an independent driving path for the second group of level outputs.

[0018] Compared with the prior art, the present utility model has the following beneficial effects:

[0019] (1) Use the analog-digital hybrid method to avoid circuit complexity and have a fast control response. After the analog part judges the peak value, it converts the peak detection situation into a digital signal output;

[0020] (2) Compare the voltage of two different signal characteristics through a filter circuit, a comparison circuit, and a level output circuit, which can handle the peak-to-peak value judgment of multiple signals and help the digital system control the gain to an appropriate level. Brief Description of the Drawings

[0021] Figure 1 is the electrical connection diagram of the present utility model.

[0022] Figure 2 is the signal output curve diagram of the present utility model. Detailed Embodiment

[0023] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0024] Embodiment 1

[0025] As Figure 1 shown, this embodiment provides a two-stage peak detection circuit for gain control, including a filter circuit, a comparison circuit, and a level output circuit; the sampling signal outputs four signals after passing through the filter circuit, which are respectively connected to the input ends of the comparison circuit; the comparison circuit includes a reference voltage module and a U1 module, the input end of the reference voltage module is connected to the reference voltages -5V and +5V, and the output end of the reference voltage module is connected to the U1 module; the input end of the U1 module is connected to the four signals of the corresponding comparison circuit and the two signals of the reference voltage module, and the U1 module outputs two signals, which are respectively connected to the input ends of the level output circuit; the first group of the level output circuit outputs an analog signal of the peak value; the second group of the level output circuit outputs a digital signal of the peak value.

[0026] This technical solution realizes a gain control scheme with low cost and high-speed response by combining a signal feature extraction circuit and digital signal processing. The peak-to-peak feature of the sampled signal can be processed by the digital system, and the digital system controls the gain amplification to keep the sampled signal within the effective range of analog conversion. This technical solution detects the peak-to-peak value of the signal through a filter circuit, a comparison circuit, and a level output circuit and converts it into a digital signal to help the digital system achieve gain control. Specifically, the U1 module is an integrated circuit with multiple comparators. Each comparator is responsible for comparing a filtered signal with a reference voltage. By adjusting the reference voltage or the threshold of the comparator, different peak detection gears can be set; as Figure 2 shown, the first group of level outputs the analog signal of the peak value, which is selected from the output of the comparison circuit through an analog multiplexer and represents the analog representation of the actually detected peak value; the second group of level outputs the digital signal of the peak value, and the result of converting the analog signal into a digital signal is achieved through an analog-to-digital converter (ADC), which converts the output of the comparison circuit into a digital signal.

[0027] In addition, according to the above-mentioned dual-gear peak detection circuit for gain control proposed by the present invention, it may also have the following additional technical features:

[0028] According to an embodiment of the present invention, the filter circuit adopts an RC filter circuit. The sampled signal is connected to R5 and C1 after passing through R1, and the other ends of R5 and C1 are connected to GND to form a filter.

[0029] In this technical solution, the RC filter circuit realizes filtering through the charging and discharging process of the capacitor C1. When the sampled signal passes through R1, most of the high-frequency signals are bypassed to the ground due to the "short-circuit" effect of the capacitor C1, while the low-frequency signals can pass through the network composed of R5 and C1 more because of the higher impedance of the capacitor, thus achieving the effect of low-pass filtering. The cut-off frequency (fc) of the filter is the key parameter for distinguishing high-frequency and low-frequency signals, which is jointly determined by the values of R5 and C1. According to the formula fc = 1 / (2πR5C1), the cut-off frequency can be changed by adjusting the value of R5 or C1. Signals below the cut-off frequency can pass through the filter relatively completely, while signals above the cut-off frequency will be greatly attenuated. While filtering, the RC filter will also introduce a phase delay because the capacitor C1 requires a certain amount of time during the charging and discharging process, resulting in a certain time lag of the output signal relative to the input signal.

[0030] According to an embodiment of the present invention, the output terminals of the filter are respectively connected to pins 5, 6, 9, and 10 of the U1 module.

[0031] This technical solution realizes the specific distribution of the filtered signal to the U1 module by connecting the output terminals of the filter to pins 5, 6, 9, and 10 of the U1 module respectively, providing multiple inputs for subsequent peak detection or signal processing.

[0032] According to an embodiment of the present invention, the U1 module uses a UPC339 chip. The reference voltages -5V and +5V are connected to pins 4 and 7 respectively. The reference voltage -5V is connected to pins 8 of R8, C2, and U1 through R7 after passing through R7. The other ends of R8 and C2 are connected to GND; the reference voltage +5V is connected to pins 11 of R13, C13, and U1 through R12 after passing through R12. The other ends of R13 and C11 are connected to GND.

[0033] This technical solution constructs a stable reference voltage source by using a UPC339 chip as the U1 module and connecting the reference voltages -5V and +5V to the specified pins (4, 7, 8, 11) of the chip through a specific resistor and capacitor network, and ensures the stability and accuracy of the reference voltage through filtering processing, providing a benchmark for the comparison and detection functions in the circuit.

[0034] According to an embodiment of the present invention, a group of pins 1 and 2 in the U1 module are connected to the base of R3 and Q1 through R4 after passing through R4. The other end of R3 is connected to the reference voltage +5V; the reference voltage +5V is connected to the emitter of R6 and Q1 through R2 after passing through R2, serving as the first group of level outputs.

[0035] This technical solution constructs a driving circuit for the first group of level outputs by connecting a group of pins 1 and 2 in the U1 module to the base of resistor R4, R3, and transistor Q1. The reference voltage +5V provides a bias for the emitter of Q1 through R2 and R6, realizing the level conversion and amplification of the output signal based on the U1 module, and providing the necessary driving ability for the first group of level outputs.

[0036] According to an embodiment of the present invention, a group of pins 13 and 14 in the U1 module are connected to the base of R10 and Q2 through R11 after passing through R11. The other end of R10 is connected to the reference voltage +5V; the reference voltage +5V is connected to the emitter of R14 and Q2 through R9 after passing through R9. The other end of R14 is connected to the collector and GND of Q2, serving as the second group of level outputs.

[0037] This technical solution constructs a driving circuit for the second group of level outputs by connecting another group of pins 13 and 14 in the U1 module to the base of resistor R11, R10, and transistor Q2. Similar to the first group, the reference voltage +5V provides a bias and loop for the emitter and collector of Q2 through R9 and R14, realizing the level conversion and amplification of another output signal based on the U1 module, and providing an independent driving path for the second group of level outputs.

[0038] Although the present utility model has been described in detail by referring to the accompanying drawings and in conjunction with the preferred embodiments, the present utility model is not limited thereto. Without departing from the spirit and essence of the present utility model, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present utility model, and these modifications or substitutions should all be within the scope covered by the present utility model. / Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of changes or substitutions, and all should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the said claims.

Claims

1. A dual-level peak detection circuit for gain control, characterized in that: It includes a filtering circuit, a comparison circuit and a level output circuit; the sampling signal outputs four signals after passing through the filtering circuit, which are respectively connected to the input end of the comparison circuit; the comparison circuit includes a reference voltage module and a U1 module, the input end of the reference voltage module is connected to the reference voltage -5V and +5V, and the output end of the reference voltage module is connected to the U1 module; The input end of the U1 module is connected to the four signals of the corresponding comparison circuit and the two signals of the reference voltage module. The U1 module outputs two signals, which are respectively connected to the input end of the level output circuit; the first group of level outputs of the level output circuit outputs the analog signal of the peak value; the second group of level outputs of the level output circuit outputs the digital signal of the peak value.

2. The dual-level peak detection circuit for gain control according to claim 1, characterized in that: The filter circuit adopts an RC filter circuit. The sampling signal passes through R1 and then connects to R5 and C1. The other ends of R5 and C1 are connected to GND to form a filter.

3. The dual-level peak detection circuit for gain control according to claim 2, characterized in that: The output ends of the filter are respectively connected to pins 5, 6, 9, and 10 of the U1 module.

4. The dual-level peak detection circuit for gain control according to claim 1, characterized in that: The U1 module adopts the UPC339 chip, and the reference voltages -5V and +5V are connected to pins 4 and 7 respectively. The reference voltage -5V is connected to R8, C2 and pin 8 of U1 after passing through R7, and the other ends of R8 and C2 are connected to GND; the reference voltage +5V is connected to R13, C13 and pin 11 of U1 after passing through R12, and the other ends of R13 and C11 are connected to GND.

5. The dual-level peak detection circuit for gain control according to claim 4, characterized in that: A group of pins 1 and 2 in the U1 module are connected to R3 and the base of Q1 through R4, and the other end of R3 is connected to the reference voltage +5V; the reference voltage +5V is connected to R6 and the emitter of Q1 through R2, which is the first group of level outputs.

6. The dual-level peak detection circuit for gain control according to claim 5, characterized in that: A group of pins 13 and 14 in the U1 module are connected to R10 and the base of Q2 through R11, and the other end of R10 is connected to the reference voltage +5V; the reference voltage +5V is connected to R14 and the emitter of Q2 through R9, and the other end of R14 is connected to the collector of Q2 and GND, which is the second group of level outputs.

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