Semiconductor device

Abstract

The present disclosure describes a semiconductor device that can provide improved trench filling. A semiconductor device may include a conductive feature disposed on a first layer separated by a distance and a layer disposed over the conductive feature and the first layer. The layers may include a triangular peak over each of the conductive features and a valley region over the first layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide semiconductor devices. Background Art

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is constantly increasing. To meet these demands, the semiconductor industry continues to reduce the size of semiconductor devices such as interconnect structures. This scaling down increases the complexity of semiconductor manufacturing processes and the difficulty of defect control in semiconductor devices. Summary of the Utility Model

[0003] Some embodiments of the present disclosure provide a semiconductor device, including: a first layer, a plurality of conductive features, and a second layer. The plurality of conductive features are disposed on the first layer. The second layer is disposed above these conductive features and the first layer, wherein the second layer includes a first triangular peak corresponding to a first conductive feature, a second triangular peak corresponding to a second conductive feature, and a valley region between the first triangular peak and the second triangular peak, wherein the valley region includes a height above the first layer, and this height is less than the heights of the first triangular peak and the second triangular peak above the first layer.

[0004] Some embodiments of the present disclosure provide a semiconductor device, including: a first layer, a plurality of conductive features, and a second layer. The plurality of conductive features are located on the first layer, and these conductive features have a height above the first layer and a distance between each of these conductive features. The second layer is located above these conductive features and the first layer, and the second layer includes a first height above these conductive features and a second height above the first layer, wherein the second layer includes a first triangular peak above the first conductive feature, a second triangular peak above the second conductive feature, and a valley region between the first triangular peak and the second triangular peak, wherein the peak-to-peak distance between the first triangular peak and the second triangular peak is greater than the distance between the first conductive feature and the second conductive feature.

[0005] Some embodiments of the present disclosure provide a semiconductor device, including: a plurality of conductive features, a first triangular peak, a second triangular peak, and a valley region. The plurality of conductive features are disposed on the first layer. The first triangular peak corresponds to a first conductive feature. The second triangular peak corresponds to a second conductive feature. The valley region is located between the first triangular peak and the second triangular peak. The first triangular peak, the second triangular peak, and the valley region are disposed above these conductive features and the first layer, wherein the valley region includes a height above the first layer, and this height is less than the heights of the first triangular peak and the second triangular peak above the first layer and greater than the height of each conductive feature. Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figures 1 to 4 FIG. is a cross-sectional view of a semiconductor device with improved trench fill according to some embodiments;

[0008] Figures 5 to 7 FIG. is a flowchart of a method for improving trench fill of semiconductor device features according to some embodiments;

[0009] Figures 8 to 22 FIG. is a cross-sectional view of a semiconductor device with improved trench fill according to some embodiments.

[0010] Exemplary embodiments will now be described with reference to the drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar components.

[0011]

Reference Signs

[0012] 100, 200: Semiconductor packaging device

[0013] 110, 430, 1210: Interconnect

[0014] 115: Bond wire

[0015] 120, 215, 230, 340, 1220: Solder bump

[0016] 125, 210, 1700, 1800, 1900, 2000, 2200: Semiconductor device

[0017] 130: First film

[0018] 135, 280: Triangular structure

[0019] 140: Second film

[0020] 145, 260, 440, 820, 920, 1030, 1130, 1320, 1410, 1510, 1610, 1710, 1820, 1930, 2030, 2240: Conductive feature

[0021] 220, 410: Substrate

[0022] 240: Interconnect solder bump

[0023] 250: Underfill / molding

[0024] 270: Material film

[0025] 300: Wafer bonding structure

[0026] 310: Wafer 1

[0027] 320: Wafer 2

[0028] 330: Wafer 3

[0029] 400: Three - dimensional integrated circuit packaging structure

[0030] 405: Second semiconductor device wafer

[0031] 415: Metal feature

[0032] 420, 1170, 2220: Through - hole

[0033] 425, 940: First layer

[0034] 435, 840, 1160: Trench

[0035] 460, 810, 1520, 1620, 1730, 1810, 1920, 2020, 2110, 2230: Second layer

[0036] 470, 1540, 1630, 1740, 2010, 2120, 2210: Third layer

[0037] 480, 930: Triangle peak / peak

[0038] 490, 950, 1140, 1350, 1840, 1950, 2050, 2260: Valley region

[0039] 500, 600, 700: Method

[0040] 510, 520, 530, 540, 550, 560, 570, 610, 620, 630, 640, 650, 660, 670, 670, 710, 720, 730, 740, 750, 760, 770, 780, 790: Operation

[0041] 830: Pinch point

[0042] 900, 1000, 1100, 1200, 1300, 1500, 1750: Film surface profile

[0043] 910, 1010, 1110, 1330, 1420: Material layer

[0044] 930, 1150, 1340, 1530, 1760, 1830, 1940, 2040, 2250: Peak

[0045] 1020, 1120: Apex angle

[0046] 1040: Low aspect ratio trench

[0047] 1110: Plasma etch-back material layer

[0048] 1310, 1425, 1720, 1910: Etch stop layer

[0049] 1400, 1600: Surface profile

[0050] 1430, 1640: Opening

[0051] 1850, 1960, 2060, 2270: Dashed line

[0052] 1860, 1970: Plateau

[0053] 2130: Point

[0054] A, B, C, D, E: Dimension

[0055] F: Angle

[0056] G: Difference

[0057] x: x-axis

[0058] y: y-axis

[0059] z: z-axis Detailed implementation manners

[0060] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. As used herein, the formation of a first feature on a second feature means that the first feature and the second feature are formed in direct contact. Additionally, this disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0061] In addition, for ease of description, spatial relative terms (such as "below", "beneath", "bottom", "above", "upper", and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptors used herein may be interpreted accordingly.

[0062] It should be noted that references in the specification to "one embodiment", "an embodiment", "example embodiments", "exemplary", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementation of this feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described, is within the knowledge of those skilled in the art.

[0063] It is to be understood that the language or terminology herein is for the purpose of description and not of limitation, such that the terminology or language of this specification will be interpreted by those skilled in the relevant art in light of the teachings herein.

[0064] In some embodiments, the terms "about" and "substantially" may indicate a given value that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the value as interpreted by those skilled in the relevant art in light of the teachings herein.

[0065] As the demand for lower power consumption, higher performance, and smaller semiconductor devices increases, the size of semiconductor devices continues to shrink. Based on the continuous shrinkage of device size and the increasing demand for device performance, various processes and materials may need to be improved, which may pose multiple challenges. For example, a semiconductor device may include several device features that extend upward from a substrate and / or a first layer (e.g., a conductive first layer, metal interconnects, transistor gate structures, mandrels, bonding pads, conductive materials, etc.) and produce a surface topography with various feature heights. In some embodiments, as the layer-by-layer fabrication progresses, a film may be deposited over the device features. In some embodiments, during the deposition of a film over the device features, the film may accumulate on top of the device features and extend outward from the top of the device feature spaces. In some embodiments where the device features are adjacent to each other, the outward growth of one device feature may extend and contact the outward growth of another device feature. In some embodiments, the unwanted contact from two adjacent device features creates a pinch point, thereby sealing the trench between the device features. This sealing may prevent the filling of the trench between the device features. In some embodiments, for various reasons, it is desirable to fill the trench, such as to prevent electrical connectivity between features, to prevent air and / or oxygen from being trapped in the trench, to prevent the creation of a vacuum in the trench (which can damage the device when air and / or oxygen are removed during a vacuum process), or to facilitate downstream processing, including chemical mechanical planarization.

[0066] Figure 1 Cross-sectional view of a semiconductor package device 100 having a semiconductor device 125 according to some embodiments, where the semiconductor device 125 may have a material film topography exhibiting improved trench fill. Figure 2 Cross-sectional view of a semiconductor device 210 having improved trench fill and connected to a substrate 220 according to some embodiments. Figure 3 Cross-sectional view showing an optionally selected wafer bonding configuration according to some embodiments. Figure 4 Cross-sectional view showing two semiconductor devices with improved trench fill connected together according to some embodiments. For explanatory purposes, reference will be made throughout the disclosure to Figure 4 .

[0067] Reference Figure 1, according to some embodiments of the present disclosure, the semiconductor packaging device 100 may include multiple layers (e.g., a substrate, a dielectric layer, a filling layer, a covering layer, etc.), interconnects 110, wire bonds 115, solder bumps 120, and a semiconductor device 125. The semiconductor packaging device 100 may include the semiconductor device 125 in any desired configuration, e.g., disposed on the substrate and electrically coupled to one or more of the interconnects 110. In some embodiments, the semiconductor device 125 may include a material film topography that exhibits improved trench filling. The first film 130 may be etched to provide a triangular structure 135 such that the second film 140 can be filled between the conductive features 145.

[0068] Figure 2 A cross-section showing a part of a semiconductor packaging device 200 according to some embodiments of the present disclosure is shown. The semiconductor device 210 may be electrically coupled to the substrate 220 (with solder bumps 230) via interconnect solder bumps 240. In some embodiments, the semiconductor device 210 may be encapsulated with an underfill (or molding) 250. In some embodiments, the underfill or molding 250 may be a dielectric material (e.g., an amorphous or crystalline high-k material, such as a polymer, a metal oxide, an alloy oxide, or any suitable high-k material). In some embodiments, the semiconductor device 210 may include a material film topography that exhibits improved trench filling as described above. The material film 270 may be etched to provide a triangular structure 280 such that the underfill or molding 250 can be filled between the conductive features 260.

[0069] Figure 3 A diagram showing the placement of the semiconductor device 125 in the wafer bonding structure 300 according to some embodiments of the present disclosure is shown. Any one of wafer 1 310, wafer 2 320, or wafer 3 330 may be the semiconductor device 125. As Figure 3 shown, the semiconductor device 125 may be bonded using its corresponding interconnect solder bumps 215. In some embodiments, the wafer bonding structure 300 may have solder bumps 340 such that further wafer bonding can be performed.

[0070] Figure 4 A diagram showing two semiconductor devices 125 bonded together in a three-dimensional integrated circuit packaging structure 400 according to some embodiments of the present disclosure is shown. As Figure 4As shown, the first semiconductor device wafer 401 can be electrically coupled to the second semiconductor device wafer 405 using interconnects 430. The interconnects 430 are electrically coupled to conductive features 440 (e.g., metal interconnects, metal features, or mandrels). Using vias 420 disposed in a first layer (e.g., interlayer dielectric) 425, the conductive features 440 can be further electrically coupled to metal features 415 disposed on or within a substrate 410. A second layer 460 and a third layer 470 can be high-k dielectric materials (e.g., passivation layers, interlayer dielectrics, etc.) disposed above and around the conductive features 440. In some embodiments, two semiconductor devices 125 can include an improved trench fill topography. For example, the second layer 460 can be etched to form triangular peaks 480 above the conductive features 440. In some embodiments, the etching can also form valley regions 490 above the trenches 435. Additionally, in some embodiments, the third layer 470 can be filled in the valley regions 490 and can be planarized as appropriate for downstream processing.

[0071] In some embodiments of the present disclosure, a method of manufacturing a semiconductor device with improved material trench fill is described. In some embodiments of the present disclosure, Figure 5 A flowchart for illustrating an improved trench fill method 500 is shown. For illustrative purposes, reference will be made to Figure 4 and Figures 8 to 12 to describe the operations of method 500. Depending on the specific application, the operations of method 500 can be performed in a different order, repeated (either immediately or further downstream), or not performed. Additionally, it should be understood that additional operations can be provided before, during, and after method 500, and other operations can be described only briefly herein.

[0072] Referring to Figure 5 , method 500 begins with operation 510 and a process of forming metal features on a first layer (e.g., substrate, interlayer dielectric, dummy fill, gate structure, etc.). For example, as Figure 4 shown, the substrate 410 can have metal features 415 formed within the substrate. For illustrative purposes, the entire thickness of the substrate 410 is not shown, so the metal features 415 are formed on or within the surface of the substrate 410 and are exposed for connection to interlayer interconnects.

[0073] In some embodiments, at operation 520, an interlayer interconnect is provided by forming a via 420 in a first layer 425. In some embodiments, at operation 530, a conductive feature 440 (e.g., a metal feature or a mandrel) may be formed over the via 420 to provide an electrical connection to a metal feature 415 on or within the substrate 410. After forming the conductive feature 440, method 500 may include, at operation 540, depositing (e.g., covering) a second layer 460 over the conductive feature 440 and over a trench 435 between the conductive features 440. In some embodiments, the second layer 460 may be a dielectric material. For example, the second layer 460 may be any one of silicon dioxide, silicon nitride, a polymer (e.g., polyimide), or a combination thereof.

[0074] In some embodiments, depositing the second layer 460 may contribute to pinch point formation and sealing a trench 840 corresponding to Figure 4 the trench 435 depicted in, the trench 840 being located between conductive features 820 corresponding to Figure 4 the conductive feature 440 depicted in, as Figure 8 shown. As Figure 8 shown, in some embodiments, when depositing a second layer 810 corresponding to Figure 4 the second layer 460 depicted in over the conductive feature 820, the second layer 810 deposited over the conductive feature 820 may grow upward and outward, which may form a pinch point 830 over the trench 840. Thus, in some embodiments, the pinch point 830 may prevent material from filling the trench 840 corresponding to Figure 4 the trench 435 depicted in. Any plasma enhanced material deposition process may be used to deposit the second layer 810, e.g., plasma enhanced chemical vapor deposition (PECVD), sputtering, plasma enhanced atomic layer deposition (PEALD), etc. Referring to Figure 5 at operation 550, in some embodiments, the plasma enhanced material deposition may be stopped and at least a portion of the deposited second layer 810 may be etched back using a plasma.

[0075] Figure 9To provide an illustration of an embodiment of a semiconductor device structure size optionally extending along the x-axis and z-axis as shown. The sizes are provided as a minimum-maximum range, and corresponding intermediate values are provided to convey embodiments of trench filling aimed at achieving the described improvements. For example, dimension C provides the distance extending along the x-axis for the valley region 950. In some embodiments, dimensions A and B describe the film thickness (or, for example, film height) along the z-axis. For example, dimension A is greater than dimension E such that the bottom of the triangular peak 930 is wider along the x-axis than the width of the conductive feature 920. Dimension B is greater than dimension E such that the material layer 910 covers the conductive feature 920. Dimensions D and angle F provide the valley region 950, which is prone to material filling to mitigate Figure 8 the pinch point 830 shown. Accordingly, the values and value ranges provided below are provided as critical dimensions to achieve coverage of the conductive feature 920 with improved trench filling.

[0076] As Figure 9 shown, in some embodiments, the plasma etch operation 550 can provide a film surface profile 900 having a peak 930 corresponding to the triangular peak 480 depicted in Figure 4 , and the peak 930 is disposed above the conductive feature 920 corresponding to the conductive feature 440 depicted in Figure 4 . In some embodiments, the conductive feature 920 can have a height E in the range of between about 0.5 micrometers (μm) to about 6 μm along the z-axis. For example, the conductive feature height (dimension E) can be about 0.5 μm, about 0.75 μm, about 1 μm, about 1.5 μm, about 2 μm, about 2.5 μm, about 3 μm, about 3.5 μm, about 4 μm, about 4.5 μm, about 5 μm, about 5.5 μm, or about 6 μm. In some embodiments, the conductive feature 920 can have a width in the range of between about 1 μm to about 5 μm (e.g., about 1 μm, about 2 μm, about 3 μm, about 4 μm, or about 5 μm).

[0077] In some embodiments, the conductive features 920 can be separated by a center-to-center distance (dimension D) along the x-axis. For example, the conductive features 920 can be separated by a center-to-center distance in the range of between about 1.5 μm to about 6.5 μm, e.g., about 1.4 μm, about 1.6 μm, about 1.3 μm, about 1.7 μm, about 1.25 μm, or about 1.75 μm. Similarly, in some embodiments, the conductive features 920 can be separated by a feature-to-feature distance (dimension C) in the range of between about 1 μm to about 5 μm (e.g., the conductive features 920 can be separated by about 1 μm, about 1.5 μm, about 2 μm, about 2.5 μm, about 3 μm, about 3.5 μm, about 4 μm, about 4.5 μm, or about 5 μm). In some embodiments, the feature-to-feature distance is wide enough to deposit material between the conductive features 920.

[0078] In some embodiments, after depositing a material layer 910 corresponding to the second layer 460 depicted in Figure 4 , a plasma etch operation 550 can be performed using an oxygen plasma. The plasma etch time can range from about 20 seconds (s) to about 500 s. For example, the plasma etch time can be about 20 s, about 30 s, about 40 s, about 50 s, about 60 s, about 90 s, about 120 s, about 150 s, about 180 s, about 210 s, about 240 s, about 270 s, about 300 s, about 330 s, about 360 s, about 390 s, about 420 s, about 450 s, about 480 s, or about 500 s. In some embodiments, the chamber pressure during plasma etching can range from about 0.5 millitorr (mT) to about 20 mT. For example, the chamber pressure during plasma etching can be about 0.5 mT, about 0.75 mT, about 1 mT, about 5 mT, about 10 mT, about 15 mT, or about 20 mT. In some embodiments, the plasma source radio frequency (RF) can range from about 500 watts (W) to about 11 kilowatts (kW). For example, the plasma source RF can be about 500 W, about 750 W, about 1 kW, about 2 kW, about 3 kW, about 4 kW, about 5 kW, about 6 kW, about 7 kW, about 8 kW, about 9 kW, about 10 kW, or about 11 kW. Additionally, in some embodiments, the bias RF (in other words, the RF applied to the target stage to attract the excited plasma species to the target, in this case, the material layer 910) can range from about 1 kW to about 100 kW (e.g., about 1 kW, about 10 kW, about 20 kW, about 30 kW, about 40 kW, about 50 kW, about 60 kW, about 70 kW, about 80 kW, about 90 kW, or about 100 kW).

[0079] In some embodiments, performing the plasma etch operation 550 according to the above parameters can provide a film surface profile 900 as shown in Figure 9 . As shown in Figure 9 , by removing the outward film growth and the resulting pinch points 830 that may occur during the layer deposition operation 540 (see Figure 8 ), plasma etching can provide a triangular peak 930 corresponding to the triangular peak 480 depicted in Figure 4 above the conductive feature 920 corresponding to the conductive feature 440 depicted in Figure 4 . Additionally, in some embodiments, plasma etching can provide a valley region 950 corresponding to the valley region 490 depicted in Figure 4 between the peaks 930. In some embodiments, the top of the valley region 950 disposed between the peaks 930 can be substantially flat. In some embodiments, corresponding to Figure 4The material layer 910 of the second layer 460 depicted in can have a resulting base film thickness (dimension B) in the range of from about 0.6 μm to about 12 μm along the z-axis. For example, from the first layer 940 corresponding to the first layer 425 depicted in Figure 4 to the top of the material layer 910 after plasma etching, the material layer 910 can have a thickness of about 0.6 μm, about 0.7 μm, about 0.8 μm, about 0.9 μm, about 1 μm, about 2 μm, about 3 μm, about 4 μm, about 5 μm, about 6 μm, about 7 μm, about 8 μm, about 9 μm, about 10 μm, about 11 μm, or about 12 μm. Similarly, in some embodiments, the thickness of the peak above the conductive feature 920 (dimension A) can be in the range of from about 0.5 μm to about 10 μm. For example, the peak thickness above the conductive feature 920 (dimension A) can be about 0.5 μm, 0.6 μm, 0.7 μm, about 0.8 μm, about 0.9 μm, about 1 μm, about 2 μm, about 3 μm, about 4 μm, about 5 μm, about 6 μm, about 7 μm, about 8 μm, about 9 μm, or about 10 μm.

[0080] In some embodiments, after performing the plasma etching operation 550, the thickness of the peak (dimension A) can be less than the base film thickness (dimension B) along the z-axis. In some embodiments, the base film thickness (dimension B) can be greater than the height of the conductive feature 920 (dimension E). For example, the base film thickness (dimension B) can be greater than the height of the conductive feature 920 (dimension E) corresponding to the conductive feature 440 depicted in Figure 4 and have a difference G (e.g., B z轴 – E z轴 = G z轴 ). In some embodiments, the difference G between the height of the conductive feature 920 (dimension E) and the base film thickness (dimension B) can be in the range of from about 0.1 μm to about 9 μm. For example, dimension B – dimension E can be equal to about 0.1 μm, about 0.2 μm, about 0.3 μm, about 0.4 μm, about 0.5 μm, 0.6 μm, 0.7 μm, about 0.8 μm, about 0.9 μm, about 1 μm, about 2 μm, about 3 μm, about 4 μm, about 5 μm, about 6 μm, about 7 μm, about 8 μm, or about 9 μm.

[0081] In some embodiments, the aspect ratio of the valley region 950 can be in the range of from about 5 to about 10, corresponding to an angle F between the triangular peak 930 (along the z-axis) and the x-axis in the range of from about 90° to about 150°. The aspect ratio can be the ratio of the depth and / or height of the feature to the width of the feature, e.g., as Figure 9As depicted, the aspect ratio is the ratio of the value along the z-axis to the value along the x-axis, or Z:X. For example, the aspect ratio of the valley region 950 (e.g., the ratio of the height (dimension A) to the valley region 950) can be about 5, about 6, about 7, about 8, about 9, or about 10. In some embodiments, the angle F can be about 90°, 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145°, or about 150°.

[0082] In some embodiments, Figure 10 illustrates the film surface profile 1000 that may occur when plasma etching is not performed. It is noted that, in some embodiments, at the apex 1020 of the conductive feature 1030 corresponding to the conductive feature 440 depicted in Figure 4 the thickness of the material layer 1010 corresponding to the second layer 460 depicted in Figure 4 may be prone to cracking, delamination, and have poor heat dissipation. Additionally, in some embodiments, the material layer 1010 may include low aspect ratio trenches 1040 between the conductive features 1030. Optionally, these low aspect ratio trenches 1040 may be difficult to fill.

[0083] As Figure 11 shown, in some embodiments, the film surface profile 1100 provided by the plasma etching operation 550 can alleviate Figure 10 the problems shown in Figure 4 In some embodiments, the plasma etched material layer 1110 corresponding to the second layer 460 depicted in Figure 4 can be shaped and thinner at the apex 1120 of the conductive feature 1130. Additionally, the profile of the material layer 1110 can provide valley regions 1140 corresponding to the valley regions 490 depicted in Figure 4 between the peaks 1150 corresponding to the triangular peaks 480 depicted in Figure 4 The valley regions 1140 are disposed above the conductive feature 1130 corresponding to the conductive feature 440 depicted in Figure 4 and can be adapted to be filled with a desired material in the trenches 1160 corresponding to the trenches 435 depicted in

[0084] Referring to Figure 5 in some embodiments, after performing the plasma etching operation 550, the semiconductor device can be processed to provide an exposed conductive feature 1130 corresponding to the conductive feature 440 depicted in Figure 4 As Figure 11 shown, in operation 560, the corresponding Figure 4At least a portion of the material layer 1110 of the second layer 460 depicted to provide interconnected vias 1170. In some embodiments, the next layer wiring operation 570 may include metallization (e.g., resistive evaporation, sputtering, or electrochemical plating). Referring to Figure 12 , metallization may be performed to provide interconnects 1210 in the vias 1170, corresponding to Figure 4 the interconnects 430 depicted in

[0085] In some embodiments of the present disclosure, Figure 6 is a flowchart illustrating an improved trench filling method 600. For illustrative purposes, reference will be made to Figure 4 , Figure 13 and Figure 14 to describe the operations of method 600. Depending on the specific application, the operations of method 600 may be performed in a different order, repeated (immediately or further downstream), or not performed. Additionally, it should be understood that additional operations may be provided before, during, and after method 600, and other operations may be described only briefly herein.

[0086] Referring to Figure 6 , method 600 begins with operation 610 and a process of forming metal features on a substrate. For example, as Figure 4 shown, the substrate 410 may have metal features 415 formed thereon. For illustrative purposes, the entire thickness of the substrate 410 is not shown, so the metal features 415 are formed on the surface or within the subsurface of the substrate 410 and are exposed for connection to the interlayer interconnects.

[0087] In some embodiments, at operation 620, an interlayer interconnect is provided by forming vias 420 in the first layer 425. In some embodiments, at operation 630, and referring to Figure 4 and Figure 13 , conductive features 1320 (e.g., metal features or mandrels) corresponding to Figure 4 the conductive features 440 depicted in Figure 4 may be formed above the vias 420 to provide an electrical connection to the metal features 415 on or within the substrate 410. After forming the conductive features 1320 corresponding to Figure 13, an etch stop layer 1310 is deposited over the conductive feature 1320. The etch stop layer 1310 can be any suitable etch stop material, including oxides, metal oxides, nitrides, metal nitrides, metals, metal alloys, etc. For example, the etch stop layer 1310 can be any one of silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, zirconium oxide, etc. In some embodiments, the etch stop layer 1310 can have a thickness in the range of from about to about (e.g., from about 30 nanometers (nm) to about 300 nm). In some embodiments, the thickness of the etch stop layer 1310 can be about about about about about about about about about or about

[0088] After depositing the etch stop layer 1310, method 600 can include, in operation 650, depositing using plasma enhanced materials, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, plasma enhanced atomic layer deposition (PEALD), etc., a material layer 1330 corresponding to the second layer 460 depicted in Figure 4 over the conductive feature 1320 corresponding to the conductive feature 440 depicted in Figure 4 . In some embodiments, the material layer 1330 can be a dielectric material. For example, the material layer 1330 can be any one of silicon dioxide, silicon nitride, a polymer (such as polyimide), or a combination thereof. Referring to Figure 6 , in operation 660, in some embodiments, the plasma enhanced material deposition can be stopped, and at least a portion of the deposited material layer 1330 can be etched back using plasma. As shown in Figure 13 , in some embodiments, the plasma etch back operation 660 can provide a film surface profile 1300 having a corresponding to Figure 4Peak 1340 of the triangular peak 480 depicted in, peak 1340 is disposed above the conductive feature 1320. In some embodiments, after depositing the material layer 1330, an etch-back operation 660 can be performed using an oxygen plasma. In some embodiments, the etch-back time can range from about 20 s to about 500 s, the chamber pressure during the etch-back can range from about 0.5 mT to about 20 mT, the plasma source RF can range from about 500 W to about 11 kW, and the bias RF can range from about 1 kW to about 100 kW.

[0089] Reference Figure 6 、 Figure 12 and Figure 14 , in some embodiments, an etch-back operation 660 can be performed to provide a film surface profile 1400 with an exposed conductive feature 1410. As Figure 14 shown, in operation 670, the material layer 1420 corresponding to the second layer 460 depicted in Figure 4 and at least a portion of the etch stop layer 1425 can be etched to provide an opening 1430 for an interconnection via. In some embodiments, the next layer wiring operation 670 can include metallization (e.g., resistive evaporation, sputtering, or electro-chemical plating). Reference Figure 12 , metallization can be performed to provide an interconnect 1210 in the via 1170, interconnect 1210 corresponding to Figure 4 the interconnect 430 depicted in

[0090] In some embodiments of the present disclosure, Figure 7 is a flow chart illustrating an improved trench filling method 700. For illustrative purposes, reference will be made to Figure 4 and Figures 15 to 22 to describe the operations of method 700. Depending on the specific application, the operations of method 700 can be performed in a different order, repeated (either immediately or further downstream), or not performed. Additionally, it should be understood that additional operations can be provided before, during, and after method 700, and other operations can be described only briefly herein.

[0091] Reference Figure 7 , method 700 begins with operation 710 and a process of forming metal features on a substrate. For example, as Figure 4 shown, the substrate 410 can have metal features 415 formed thereon. For illustrative purposes, the entire thickness of the substrate 410 is not shown, so the metal features 415 are formed on or within the surface of the substrate 410 and are exposed for connection to an interlayer interconnect.

[0092] In some embodiments, at operation 720, an interlayer interconnect is provided by forming a via 420 in the first layer 425. In some embodiments, at operation 730, and with reference to Figure 4 and Figure 15 , a conductive feature 1510 corresponding to the conductive feature 440 depicted in Figure 4 may be formed above the via 420 to provide an electrical connection to the metal feature 415 on or within the substrate 410. After forming the conductive feature 1510, method 700 may include, at operation 740, and with reference to Figure 15 , depositing a second layer 1520 corresponding to the second layer 460 depicted in Figure 4 above the conductive feature 1510 using a plasma-enhanced material deposition process, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, plasma enhanced atomic layer deposition (PEALD), etc. In some embodiments, the second layer 1520 may be a dielectric material. For example, the second layer 1520 may be any one of silicon dioxide, silicon nitride, a polymer (such as polyimide), or a combination thereof.

[0093] With reference to Figure 7 , at operation 750, in some embodiments, the plasma-enhanced material deposition may be stopped and at least a portion of the deposited second layer 1520 may be etched back using a plasma. As Figure 15 shown, in some embodiments, the plasma etch operation 750 may provide a film surface profile 1500 having a peak 1530 corresponding to the triangular peak 480 depicted in Figure 4 , the peak 1530 being disposed above the conductive feature 1510. In some embodiments, after depositing the second layer 1520 corresponding to the second layer 460 depicted in Figure 4 , the plasma etch operation 750 may be performed using an oxygen plasma. In some embodiments, the plasma etch time may range from about 20 s to about 500 s, the chamber pressure during plasma etching may range from about 0.5 mT to about 20 mT, the plasma source RF may range from about 500 W to about 11 kW, and the bias RF may range from about 1 kW to about 100 kW.

[0094] In some embodiments, after the plasma etch operation 750, a third layer deposition operation 760 may be performed. In some embodiments, in operation 760, the method may include using plasma enhanced material deposition, such as, for example, plasma enhanced chemical vapor deposition (PECVD), sputtering, plasma enhanced atomic layer deposition (PEALD), etc., to deposit a third layer 1540 corresponding to the third layer 470 depicted in Figure 4 above a second layer 1520 corresponding to the second layer 460 depicted in Figure 4 . In some embodiments, the third layer 1540 may be a dielectric material. For example, the third layer 1540 may be any one of silicon dioxide, silicon nitride, a polymer (such as polyimide), or a combination thereof. In some embodiments, the third layer 1540 may have a thickness in the range of from about to about (e.g., from about 50 nanometers (nm) to about 500 nm). In some embodiments, the thickness of the etch stop layer (second layer 1520) may be about about about about about about about about about or about

[0095] Refer to Figure 7 , Figure 12 and Figure 16 . In some embodiments, after performing the third layer deposition operation 760, the semiconductor device may be processed to provide a surface profile 1600 having an exposed conductive feature 1610 corresponding to the conductive feature 440 depicted in Figure 4 . As shown in Figure 16 , in operation 770, at least a portion of the second layer 1620 and the third layer 1630 corresponding to the second layer 460 and the third layer 470 depicted in Figure 4 may be etched to provide an opening 1640 for an interconnect via. In some embodiments, the next layer wiring operation 570 may include metallization (such as, for example, resistive evaporation, sputtering, or electroplating). Referring to Figure 12 , metallization may be performed to provide an interconnect 1210 in the via 1170 corresponding to the interconnect 430 depicted in Figure 4 . Additionally, in some embodiments, soldering may be performed to provide solder bumps 1220.

[0096] Reference Figure 4 、 Figure 7 and Figure 17 , in some embodiments, the described method may include any and / or all of the above operations. For example, the method may include providing a semiconductor device 1700, which may include a conductive feature 1710 corresponding to the conductive feature 440 depicted in Figure 4 , an etch stop layer 1720, a second layer 1730 corresponding to the second layer 460 depicted in Figure 4 and a third layer 1740 corresponding to the third layer 470. For example, method 700 begins with operation 710 and a process of forming metal features on or in a substrate. For example, as Figure 4 shown, the substrate 410 may have metal features 415 formed thereon or therein. For illustrative purposes, the entire thickness of the substrate 410 is not shown, so the metal features 415 are formed on the surface of or within the substrate 410 and are exposed for connection to an interlayer interconnect, such as Figure 4 the interconnect 430 depicted in Figure 4 and Figure 13 . In some embodiments, in operation 720, an interlayer interconnect is provided by forming a via 420 in a first layer 425. In some embodiments, in operation 730, and with reference to Figure 4 , a conductive feature 1710 corresponding to the conductive feature 440 depicted in Figure 6 may be formed above the via 420 to provide an electrical connection to the metal features 415 on or in the substrate 410. After forming the conductive feature 1710, the method may include forming an etch stop layer 1720 corresponding to the operation 640 depicted in above the conductive feature 1710. The etch stop layer 1720 may be any suitable etch stop material, including oxides, metal oxides, nitrides, metal nitrides, metals, metal alloys, etc. For example, the etch stop layer 1720 may be any one of silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, zirconium oxide, etc. In some embodiments, the etch stop layer 1720 may have a thickness in the range of from about .

[0097] In some embodiments, after forming the etch stop layer 1720, method 700 may include, in operation 740, and with reference to Figure 17, using the plasma-enhanced material deposition processes mentioned above, for example, plasma-enhanced chemical vapor deposition (PECVD), sputtering, plasma-enhanced atomic layer deposition (PEALD), etc., deposit a second layer 1730 corresponding to the second layer 460 depicted in Figure 4 above the conductive feature 1710 and the etch stop layer 1720. In some embodiments, the second layer (etch stop layer 1720) can be a dielectric material. For example, the second layer (etch stop layer 1720) can be any one of silicon dioxide, silicon nitride, a polymer (such as polyimide), or a combination thereof.

[0098] Referring to Figure 7 , in operation 750, in some embodiments, the plasma-enhanced material deposition can be stopped, and the deposited second layer 1730 corresponding to the second layer 460 depicted in Figure 4 can be etched back using a plasma. As Figure 17 shown, in some embodiments, the plasma etch-back operation 750 can provide a film surface profile 1750 having a peak 1760 corresponding to the triangular peak 480 depicted in Figure 4 , and the peak 1760 is disposed above the conductive feature 1710 corresponding to the conductive feature 440 depicted in Figure 4 . In some embodiments, after depositing the second layer 1730, an oxygen plasma can be used to perform the plasma etch-back operation 750. In some embodiments, the plasma etch-back time can range from about 20 s to about 500 s, the chamber pressure during the plasma etch-back can range from about 0.5 mT to about 20 mT, the plasma source RF can range from about 500 W to about 11 kW, and the bias RF can range from about 1 kW to about 100 kW.

[0099] In some embodiments, after the plasma etch-back operation 750, a third layer deposition operation 760 can be performed. In some embodiments, in operation 760, method 700 can include using the plasma-enhanced material deposition mentioned above, for example, plasma enhanced chemical vapor deposition (PECVD), sputtering, plasma enhanced atomic layer deposition (PEALD), etc., to deposit a layer corresponding to Figure 4The third layer 1740 is deposited over the second layer 1730 of the second layer 460 and the third layer 470 depicted therein. In some embodiments, the third layer 1740 may be a dielectric material. For example, the third layer 1740 may be any one of silicon dioxide, silicon nitride, a polymer (such as polyimide), or a combination thereof. In some embodiments, the third layer 1740 may have a thickness in the range of from about to about .

[0100] Referring to Figure 7 , Figure 12 , Figure 16 and Figure 17 , in some embodiments, after performing the third layer deposition operation 760, the semiconductor device may be processed to provide a surface profile 1600 having exposed conductive features (1610, 1710) corresponding to the conductive features 440 depicted in Figure 4 . As shown in Figure 16 , at least a portion of the etch stop layer 1720, the second layer 1730, and the third layer 1740 may be etched in operation 770 to provide an opening for an interconnect via, such as the opening 1640 depicted in Figure 16 . In some embodiments, the next layer wiring operation 780 may include metallization (e.g., resistive evaporation, sputtering, or electroplating). Referring to Figure 12 , metallization may be performed to provide an interconnect 1210 in the via 1170, corresponding to the interconnect 430 depicted in Figure 4 . Additionally, in some embodiments, soldering may be performed to provide solder bumps 1220. Referring to Figure 7 and Figures 18 to 22 , in some embodiments, the method may include a wafer and / or die bonding and / or joining operation 790 to provide the three-dimensional integrated circuit package structure 400 depicted in Figure 4 . In some embodiments, the wafer and / or die bonding and / or joining operation 790 may include a chemical mechanical planarization operation. In some embodiments, the chemical mechanical planarization may be a global surface planarization operation. For example, the top surface of the semiconductor device being fabricated may be planarized to prepare for further downstream processing. In some embodiments, referring to Figure 18 , the second layer 1810 deposited over the conductive feature 1820 corresponding to the conductive feature 440 depicted in Figure 4 and corresponding to the second layer 460 depicted in Figure 4 may be planarized to, for example, reduce the height of the peak 1830, and the second layer 1810 has peaks 1830 and valley regions 1840 corresponding to the triangular peaks 480 and valley regions 490 depicted in Figure 4 . As shown in Figure 18As shown, the planarization can be carried out to any desired amount, e.g., to the dashed line 1850. In some embodiments, the planarization operation can provide a planar surface or a wavy surface with a variable surface topography that includes plateaus 1860 and valleys 1840.

[0101] In some embodiments, a wafer and / or die bonding and / or joining operation 790 can be applied to a semiconductor device 1900 having an etch stop layer 1910. In some embodiments, referring Figure 19 , a second layer 1920 deposited over the etch stop layer 1910 and conductive features 1930 corresponding to the conductive features 440 depicted in Figure 4 and corresponding to the second layer 460 depicted in Figure 4 can be planarized to, e.g., reduce the height of peaks 1940, which have peaks 1940 and valleys 1950 corresponding to the triangular peaks 480 and valleys 490 depicted in Figure 4 . As Figure 19 shown, the planarization can be carried out to any desired amount, e.g., to the dashed line 1960. In some embodiments, the planarization operation can provide a planar surface or a wavy surface with a variable surface topography that includes plateaus 1970 and valleys 1950.

[0102] In some embodiments, a wafer and / or die bonding and / or joining operation 790 can be applied to a semiconductor device 2000 having a third layer 2010 corresponding to the third layer 470 depicted in Figure 4 . In some embodiments, referring Figure 20 , a second layer 2020 deposited over the conductive features 2030 corresponding to the conductive features 440 depicted in Figure 4 and corresponding to the second layer 460 depicted in Figure 4 can be planarized to, e.g., reduce the height of peaks 2040 formed by the second layer 2020 and the third layer 2010, the second layer 2020 having peaks 2040 and valleys 2050 corresponding to the triangular peaks 480 and valleys 490 depicted in Figure 4 . As Figure 20 shown, the planarization can be carried out to any desired amount, e.g., to the dashed line 2060. In some embodiments, the planarization operation can provide a planar surface. In some embodiments, a chemical mechanical planarization operation can expose the second layer 2020 such that the third layer 2010 can be a fill layer within the valleys 2050 on the second layer 2020. In some embodiments, referring Figure 21 , chemical mechanical planarization can be performed such that the second layer 2110 can remain shielded by the third layer 2120, e.g., at point 2130.

[0103] In some embodiments, the wafer and / or die attachment and / or bonding operation 790 may be applied to the semiconductor device 2200, which has a third layer 2210 and vias 2220 etched through the third layer 2210 and the second layer 2230. In some embodiments, referring to Figure 22 , the second layer 2230 deposited over the conductive features 2240 having peaks 2250 and valley regions 2260 may be planarized to provide, for example, a planar surface of the third layer 2210. As shown in Figure 22 , the planarization may be carried out to any desired amount, e.g., to the dashed line 2270. The wafer and / or die attachment and / or bonding operation 790 may be performed to provide the three-dimensional integrated circuit package structure 400 depicted in Figure 4 using solder, brazing, wire bonding, epoxy resin, etc.

[0104] In some embodiments, a semiconductor device may include conductive features disposed over a first layer and a second layer disposed over the conductive features and the first layer. In some embodiments, the second layer may include a first triangular peak over a first conductive feature, a second triangular peak over a second conductive feature, and a valley region between the first triangular peak and the second triangular peak. In some embodiments, the height of the valley region over the first layer may be less than the heights of the first triangular peak and the second triangular peak over the first layer.

[0105] In some embodiments, a semiconductor device may include conductive features on a first layer, the conductive features having a height on the first layer and a distance between each of the conductive features and a second layer disposed over the conductive features and the first layer. In some embodiments, the second layer may have a first height over the conductive features and a second height over the first layer. In some embodiments, the second layer includes a first triangular peak over a first conductive feature, a second triangular peak over a second conductive feature, and a valley region between the first triangular peak and the second triangular peak. In some embodiments, the peak-to-peak distance between the first triangular peak and the second triangular peak is greater than the distance between the first conductive feature and the second conductive feature. In some embodiments, the height of the valley region over the first layer is greater than the height of each of the conductive features.

[0106] In some embodiments, a method includes: forming conductive features on a first layer; depositing a second layer over the conductive features and the first layer; and etching at least a portion of the second layer. In some embodiments, the etching includes forming a first triangular peak over a first conductive feature, a second triangular peak over a second conductive feature, and a valley region between the first triangular peak and the second triangular peak. In some embodiments, the valley region may be formed with a height over the first layer that is less than the height of the triangular peaks over the first layer.

[0107] Some embodiments of the present disclosure provide a semiconductor device, comprising: a plurality of conductive features disposed on a first layer; and a second layer disposed above the conductive features and the first layer, wherein the second layer includes a first triangular peak corresponding to a first conductive feature, a second triangular peak corresponding to a second conductive feature, and a valley region between the first triangular peak and the second triangular peak, wherein the valley region includes a height above the first layer that is less than the heights of the first triangular peak and the second triangular peak above the first layer.

[0108] In some embodiments, the first layer includes a substrate, a conductive layer, a dielectric layer, an interconnect, or a combination thereof. In some embodiments, each of the conductive features includes a metal or a mandrel. In some embodiments, the distance between each of the conductive features ranges from about 1 micron to about 5 microns. In some embodiments, the second layer and the first layer include an etch stop layer, a dielectric layer, a polymer layer, or a combination thereof. In some embodiments, the heights of the first triangular peak and the second triangular peak above each of the conductive features are substantially equal to the height of the valley region above the first layer. In some embodiments, the height of the valley region above the first layer is greater than the height of each of the conductive features. In some embodiments, the top surface of the valley region in the second layer is substantially flat. In some embodiments, the second layer includes an angle between the top surface of the valley region and the first triangular peak and the second triangular peak, the angle ranging from about 90° to about 150°.

[0109] Some embodiments of the present disclosure provide a semiconductor device, comprising: a plurality of conductive features located on a first layer, the conductive features having a height above the first layer and a distance between each of the conductive features; a second layer located above the conductive features and the first layer, the second layer including a first height above the conductive features and a second height above the first layer, wherein the second layer includes a first triangular peak above the first conductive feature, a second triangular peak above the second conductive feature, and a valley region between the first triangular peak and the second triangular peak, wherein the peak-to-peak distance between the first triangular peak and the second triangular peak is greater than the distance between the first conductive feature and the second conductive feature.

[0110] In some embodiments, the second layer includes a valley region above the first layer between a first triangular peak above the first conductive feature and a second triangular peak above the second conductive feature, and wherein the second layer includes a valley region height above the first layer, the valley region height being greater than the height of each of these conductive features. In some embodiments, each of these conductive features is a metal interconnect, a mandrel, or a combination thereof, and the second layer includes an etch stop layer, a dielectric layer, a polymer layer, or a combination thereof. In some embodiments, the second layer and the first layer are substantially flat. In some embodiments, the second layer includes a via hole exposing the top of at least one of these conductive features.

[0111] Some embodiments of the present disclosure provide a method of forming a semiconductor device, including: forming a plurality of conductive features on a first layer; depositing a second layer over these conductive features and the first layer; and etching at least a portion of the second layer, wherein etching at least a portion of the second layer includes forming a first triangular peak above a first conductive feature, forming a second triangular peak above a second conductive feature, and forming a valley region between the first triangular peak and the second triangular peak, wherein the valley region is formed with a height above the first layer, the height being less than the heights of the first triangular peak and the second triangular peak above the first layer.

[0112] In some embodiments, forming these conductive features includes: forming each of these conductive features above an interconnect or above a dielectric layer. In some embodiments, depositing the second layer over these conductive features and the first layer includes: covering each of these conductive features with a dielectric material, a polymer material, an etch stop material, or a combination thereof. In some embodiments, depositing the second layer over these conductive features and the first layer includes: depositing the second layer using a plasma enhanced deposition process. In some embodiments, etching at least a portion of the second layer includes: etching at least a portion of the second layer using plasma etching. In some embodiments, the method further includes: planarizing the second layer and the first layer.

[0113] Some embodiments of the present disclosure provide a semiconductor device, including: a plurality of conductive features, a first triangular peak, a second triangular peak, and a valley region. The plurality of conductive features are disposed on a first layer. The first triangular peak corresponds to a first conductive feature. The second triangular peak corresponds to a second conductive feature. The valley region is located between the first triangular peak and the second triangular peak. The first triangular peak, the second triangular peak, and the valley region are disposed above these conductive features and the first layer, wherein the valley region includes a height above the first layer, the height being less than the heights of the first triangular peak and the second triangular peak above the first layer, and greater than the height of each conductive feature.

[0114] It should be understood that the detailed description section, rather than the abstract section of this disclosure, is intended to explain the claims. The abstract section of this disclosure may set forth one or more but not all possible embodiments of the disclosure as contemplated by the inventor, and thus is not intended to limit the appended claims in any way.

[0115] The foregoing disclosure outlines the features of several embodiments so that those skilled in the art may better understand aspects of this disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructs do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made by those skilled in the art without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that: include: a plurality of conductive features disposed on a first layer; and a second layer disposed above the plurality of conductive features and the first layer, The second layer includes a first triangular peak corresponding to a first conductive feature, a second triangular peak corresponding to a second conductive feature, and a valley between the first triangular peak and the second triangular peak, wherein the valley includes a height above the first layer that is less than a height of the first triangular peak and the second triangular peak above the first layer.

2. The semiconductor device according to claim 1, wherein A distance between each of the plurality of conductive features is in a range from 1 micron to 5 microns.

3. The semiconductor device according to claim 1, wherein: A height of the first triangular peak and the second triangular peak above each of the conductive features is equal to the height of the valley region above the first layer.

4. The semiconductor device according to claim 3, wherein: The height of the valley region above the first layer is greater than a height of each of the conductive features.

5. The semiconductor device according to claim 1, wherein: A top surface of the valley region in the second layer is flat.

6. The semiconductor device according to claim 5, wherein: The second layer includes an angle between the top surface of the valley region and the first triangular peak and the second triangular peak, and the angle is in a range of 90° to 150°.

7. A semiconductor device, characterized in that: include: a plurality of conductive features on a first layer, the plurality of conductive features having a height above the first layer and a distance between each of the plurality of conductive features; a second layer located above the plurality of conductive features and the first layer, the second layer comprising a first height above the plurality of conductive features and a second height above the first layer, The second layer includes a first triangular peak above a first conductive feature, a second triangular peak above a second conductive feature, and a valley between the first triangular peak and the second triangular peak, wherein an inter-peak distance between the first triangular peak and the second triangular peak is greater than the distance between the first conductive feature and the second conductive feature.

8. The semiconductor device according to claim 7, wherein: wherein the second layer includes a valley region above the first layer disposed between the first triangular peak above the first conductive feature and the second triangular peak above the second conductive feature, and The second layer includes a valley height above the first layer, the valley height being greater than the height of each of the plurality of conductive features.

9. The semiconductor device according to claim 7, wherein: The second layer includes a through hole exposing a top of at least one conductive feature of the plurality of conductive features.

10. A semiconductor device, characterized in that: include: a plurality of conductive features disposed on a first layer; and a first triangular peak corresponding to a first conductive feature, a second triangular peak corresponding to a second conductive feature, and a valley region between the first triangular peak and the second triangular peak, wherein the first triangular peak, the second triangular peak, and the valley are disposed above the plurality of conductive features and the first layer, The valley region includes a height above the first layer, the height being less than a height of the first triangular peak and the second triangular peak above the first layer, and greater than a height of each of the conductive features.

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