Asymmetric delay control circuit and device

Abstract

The utility model provides an asymmetric delay control circuit and device, which can be applied to the technical field of electronic circuits. The asymmetric delay control circuit comprises a delay unit and an asynchronous trigger, the asynchronous trigger comprises a reset input end, a delay input end and an output end, the delay unit is connected with the delay input end, and the delay unit is used for delaying a clock signal input to the delay input end; wherein under the condition that the clock signal input by the reset input end is an invalid level, the output end outputs the invalid level, and under the condition that the clock signal input by the reset input end is an effective level and the clock signal input by the delay input end is detected to be switched from the invalid level to the effective level, the output end outputs the effective level.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, and more specifically, to an asymmetric delay control circuit and device. Background Art

[0002] In deep sub-micron technology, synchronous clocks usually introduce high power consumption, timing margins, and complex clock networks. Asynchronous circuits mainly rely on handshake protocols for communication, avoiding global clocks, and are thus more suitable for low-power designs. There are mainly two handshake protocols in asynchronous circuits: the two-phase handshake protocol and the four-phase handshake protocol. For a circuit that adheres to the two-phase handshake protocol, both the rising edge and the falling edge of its control signal can be regarded as valid trigger edges and have certain control functions. For a circuit that adheres to the four-phase handshake protocol, only one flip edge of its control signal has a control function (either the rising edge or the falling edge), and the other edge is used for "resetting" to set the control signal to its initial state.

[0003] In the process of implementing the concept of the utility model, the inventor found that there are at least the following problems in the related art: the delay circuit in the related art is prone to logical errors when the pulse duty cycle is high. Summary of the Utility Model

[0004] In view of this, the utility model provides an asymmetric delay control circuit and device.

[0005] One aspect of the utility model provides an asymmetric delay control circuit, including a delay unit and an asynchronous trigger;

[0006] The above asynchronous trigger includes a reset input terminal, a delay input terminal, and an output terminal. The above delay unit is connected to the above delay input terminal, and the above delay unit is used to delay the clock signal input to the above delay input terminal;

[0007] Wherein, when the clock signal input to the above reset input terminal is at an invalid level, the above output terminal outputs the above invalid level. When the clock signal input to the above reset input terminal is at a valid level and it is detected that the clock signal input to the above delay input terminal switches from the above invalid level to the above valid level, the above output terminal outputs the above valid level.

[0008] According to an embodiment of the utility model, the above asynchronous trigger further includes a data input terminal, and the above data input terminal is used to transfer the input data from the above data input terminal to the above output terminal when the output of the above output terminal is at the above valid level.

[0009] According to an embodiment of the utility model, the input signal of the above data input terminal is at a valid level.

[0010] According to an embodiment of the present invention, when the clock signal input to the above-mentioned reset input terminal is at an effective level and it is not detected that the clock signal input to the above-mentioned delay input terminal switches from the above-mentioned invalid level to the above-mentioned effective level, the output of the above-mentioned output terminal is the above-mentioned invalid level.

[0011] According to an embodiment of the present invention, the above-mentioned clock signal is directly input to the above-mentioned reset input terminal, and the above-mentioned clock signal is input to the above-mentioned delay input terminal after being delayed by the above-mentioned delay unit.

[0012] According to an embodiment of the present invention, the above-mentioned effective level is a high level, and the above-mentioned invalid level is a low level.

[0013] According to an embodiment of the present invention, the above-mentioned delay unit and the above-mentioned asynchronous flip-flop are composed of components in a standard cell library.

[0014] According to an embodiment of the present invention, the duty cycle of the above-mentioned effective level in one clock cycle of the above-mentioned clock signal is greater than 0 and less than 1.

[0015] According to an embodiment of the present invention, the above-mentioned asymmetric delay control circuit is applied to a four-phase handshake protocol.

[0016] Another aspect of the present invention provides an asymmetric delay control device, including the above-mentioned asymmetric delay control circuit.

[0017] According to an embodiment of the present invention, the delay of the clock signal is realized by a delay unit and an asynchronous flip-flop. For the effective level, after passing through the delay unit, its delay time is the time passing through the delay unit, so the time will be relatively long. While the invalid level can directly reach the output terminal through the reset input terminal without passing through the delay of the delay unit. The delay time for switching to the invalid level can be ignored compared to the delay time for switching to the effective level, indirectly eliminating the performance loss caused by the "zeroing" process of the handshake signal in the asynchronous four-phase handshake protocol, and it is only after detecting the switching of the clock signal at the delay input terminal that the effective level is output, avoiding logical errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Through the following description of the embodiments of the present invention with reference to the drawings, the above-mentioned and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0019] Figure 1A Schematically shows a schematic diagram of a two-phase handshake protocol in the related art;

[0020] Figure 1B Schematically shows a schematic diagram of a four-phase handshake protocol in the related art;

[0021] Figure 1CA schematic diagram showing a delay circuit of a MOS transistor structure based on a stacked structure in the related art is schematically shown;

[0022] Figure 1D A schematic diagram showing an asymmetric delay circuit of a simple circuit structure based on an AND gate in the related art is schematically shown;

[0023] Figure 1E A schematic diagram showing the relationship between the input signal and the output signal of an asymmetric delay circuit of a simple circuit structure based on an AND gate in the related art is schematically shown;

[0024] Figure 2 A schematic diagram showing the structure of an asymmetric delay control circuit according to an embodiment of the present invention is schematically shown;

[0025] Figure 3 A schematic diagram showing the relationship between the input signal and the output signal of an asymmetric delay control circuit according to an embodiment of the present invention; and

[0026] Figure 4 A block diagram showing an asymmetric delay control device according to an embodiment of the present invention is schematically shown. Detailed implementation manners

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0028] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising" and the like used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0029] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0030] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include but not be limited to a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0031] Figure 1A A schematic diagram showing the two - phase handshake protocol in the related art is schematically illustrated.

[0032] Figure 1B A schematic diagram showing the four - phase handshake protocol in the related art is schematically illustrated.

[0033] As Figure 1A , where both the rising edge and the falling edge of the Request signal indicate that the data is valid, and both the rising edge and the falling edge of the acknowledge signal indicate that the data has been successfully latched.

[0034] As Figure 1B shown, where the rising edge of the Request signal indicates that the data is valid, and the rising edge of the acknowledge signal indicates that the data has been successfully latched. While the falling edges of the Request signal and the acknowledge signal have no function, this redundant reset process reduces the transmission efficiency of the four - phase circuit by half compared to the two - phase circuit. However, since the four - phase handshake protocol is often required in current mainstream asynchronous designs, it is relatively important to compress and optimize the reset time during the four - phase handshake process.

[0035] In the related art, mainly starting from the delay matching unit, the traditional delay unit is replaced with a series of asymmetric delay matching units to make the delay time of the invalid edges as short as possible, thereby reducing performance loss. However, these designs all have the disadvantages of complex control, large area overhead, and inability to be synthesized. The design of the delay matching unit is generally based on stacked - structure MOS transistors or a simple circuit based on an AND gate.

[0036] Figure 1C A schematic diagram showing the delay circuit of the MOS transistor structure based on the stacked structure in the related art is schematically illustrated.

[0037] Figure 1D A schematic diagram showing the asymmetric delay circuit of the simple circuit structure based on an AND gate in the related art is schematically illustrated.

[0038] As Figure 1CAs shown, the delay circuit based on the MOS transistor structure with a stacked structure has a small area, but it cannot be compatible with current automated design tools and requires pure manual design. Circuit designers need to adjust the sizes and ratios of the upper and lower transistors to regulate the delay characteristics of the circuit. Finally, they also need to repeatedly test the average rise and fall delays of the current circuit, continuously modify and adjust it to obtain the ideal delay value. Moreover, the circuit designed in this way can only be adapted to one process. Once the process library needs to be converted, the delay characteristics of the entire circuit will change, thus requiring re-design, which greatly reduces the design efficiency and the generality of the circuit.

[0039] As Figure 1D shown in [reference], the asymmetric delay circuit based on the simple circuit structure of an AND gate, although using standard cell design and being synthesizable using electronic design automation tools, eliminating the cumbersome process of pure manual design, has a problem of logical errors in actual applications for signal propagation with a high pulse duty cycle and low delay.

[0040] Figure 1E Schematically shows the relationship diagram of the input signal and output signal of the asymmetric delay circuit based on the simple circuit structure of an AND gate in the related art.

[0041] As Figure 1E shown in [reference], a is the waveform output when the pulse duty cycle is less than or equal to 50%, Figure 1E shown in [reference], b is the waveform output when the pulse duty cycle is greater than 50%, Figure 1E The waveform circled by the circle in b in [reference] is the incorrect waveform. Therefore, the asymmetric delay circuit based on the simple circuit structure of an AND gate can only complete the function of asymmetric delay matching when the input signal with a low pulse duty cycle propagates.

[0042] An embodiment of the present invention provides an asymmetric delay control circuit, including: a delay unit and an asynchronous trigger; the asynchronous trigger includes a reset input terminal, a delay input terminal, and an output terminal. The delay unit is connected to the delay input terminal, and the delay unit is used to delay the clock signal input to the delay input terminal; wherein, when the clock signal input to the reset input terminal is at an invalid level, the output terminal outputs an invalid level, and when the clock signal input to the reset input terminal is at a valid level and it is detected that the clock signal input to the delay input terminal switches from an invalid level to a valid level, the output terminal outputs a valid level.

[0043] Figure 2 Schematically shows the structural diagram of the asymmetric delay control circuit according to the embodiment of the present invention.

[0044] As Figure 2As shown, the asymmetric delay control circuit 200 includes a delay unit 210 and an asynchronous flip-flop 220; the asynchronous flip-flop 210 includes a reset input terminal RDN, a delay input terminal CK, and an output terminal Q. The delay unit 210 is connected to the delay input terminal CK, and the delay unit 210 is used to delay the clock signal input to the delay input terminal CK. Among them, when the clock signal input at the reset input terminal RDN is at an invalid level, the output terminal Q outputs an invalid level. When the clock signal input at the reset input terminal RDN is at a valid level and it is detected that the clock signal input at the delay input terminal CK switches from an invalid level to a valid level, the output terminal Q outputs a valid level.

[0045] According to an embodiment of the present invention, the asynchronous flip-flop 210 may be an asynchronous reset D flip-flop (AR-DFF).

[0046] According to an embodiment of the present invention, the input signal is the clock signal.

[0047] According to an embodiment of the present invention, in the initial state, the clock signal input is at an invalid level, that is, the input at the reset input terminal RDN is at an invalid level, and the output terminal Q outputs an invalid level. When the clock signal switches from an invalid level to a valid level, the valid level reaches the delay input terminal CK after being delayed by the delay unit 210. When the delay input terminal CK detects the level conversion, the output terminal Q outputs a valid level. When the clock signal switches from a valid level to an invalid level, the input at the reset input terminal RDN is at an invalid level, and the output terminal Q continues to output an invalid level.

[0048] According to an embodiment of the present invention, the delay of the clock signal is realized by a delay unit and an asynchronous flip-flop. For the valid level, after passing through the delay unit, its delay time is the time passing through the delay unit, so the time will be relatively long. The invalid level can directly reach the output terminal through the reset input terminal without being delayed by the delay unit. The delay time for switching to the invalid level can be ignored compared to the delay time for switching to the valid level, indirectly eliminating the performance loss caused by the "return to zero" process of the handshake signal in the asynchronous four-phase handshake protocol. And it is only after detecting the switching of the clock signal at the delay input terminal that the valid level is output, avoiding logical errors.

[0049] According to an embodiment of the present invention, the asynchronous flip-flop 220 further includes a data input terminal D. The data input terminal D is used to transmit the input data from the data input terminal D to the output terminal Q when the output of the output terminal Q is at a valid level. The input signal of the data input terminal D is at a valid level.

[0050] According to an embodiment of the present invention, when the clock signal input to the reset input terminal RDN is at an effective level and it is not detected that the clock signal input to the delay input terminal CK switches from an ineffective level to an effective level, the output of the output terminal Q is at an ineffective level.

[0051] According to an embodiment of the present invention, the clock signal is directly input to the reset input terminal RDN, and after being delayed by the delay unit 210, the clock signal is input to the delay input terminal.

[0052] According to an embodiment of the present invention, the logical relationship of the asynchronous flip-flop 220 is as follows in formula (1):

[0053] Q = (!RDN)? 0 : (rising(CK)? D : pre_Q) (1)

[0054] The above logical relationship indicates that when the asynchronous flip-flop 220 works, it first judges whether the input of the reset input terminal RDN is at a low level. If it is at a low level, the circuit output is directly set to a low level. If the input of the reset input terminal RDN is at a high level, it then judges whether the rising edge of the delay input terminal CK arrives. If the rising edge of the delay input terminal CK appears, the data at the data input terminal D is immediately sent to the output terminal Q. If the rising edge of the CK terminal does not arrive, the output terminal Q maintains the original level value.

[0055] Figure 3 Schematically shows the relationship diagram of the input signal and the output signal of the asymmetric delay control circuit according to an embodiment of the present invention.

[0056] As Figure 3 shown, taking the effective level as a high level and the ineffective level as a low level as an example, the rising edge delay path of the input signal (i.e., the clock signal) includes the delay of the delay unit 210 and the propagation delay from the data input terminal D to the output terminal Q of the asynchronous flip-flop 220. When the falling edge of the input signal arrives, the asynchronous reset terminal RDN inputs a low level and is in an effective state. At this time, the output signal will be immediately reset to a low level without passing through the delay of the delay unit 210, thereby realizing a fast flip. The falling edge delay path of the input signal only includes the propagation delay from the asynchronous reset terminal RDN to the output terminal Q of the asynchronous flip-flop 210.

[0057] Therefore, as Figure 3As shown, for a signal pulse, after passing through the delay unit 210, its rising delay time is the time passing through the delay unit, so the time will be relatively long. While the falling edge does not need to pass through the delay unit and is directly transmitted to the output end. When the delay of the delay unit is large enough, the falling edge delay time can be negligible compared to the rising edge delay time, indirectly eliminating the performance loss caused by the "return to zero" process of the handshake signal in the asynchronous four-phase handshake protocol. Moreover, it can be applied to various scenarios where the duty cycle of the effective level in one clock cycle of the clock signal is greater than 0 and less than 1, without logical errors.

[0058] According to an embodiment of the present invention, the delay unit and the asynchronous flip-flop are composed of components in a standard cell library. It can be directly synthesized using component tools, can be compatible with multiple process libraries at the same time, and is convenient for process conversion. In the related art, the asymmetric delay is realized by adjusting the sizes of N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) transistors inside the delay unit, which often requires manual design, increasing the implementation difficulty. If the process is converted, the delay unit needs to be adjusted again, reducing the portability of the circuit; therefore, the asymmetric delay control circuit in the embodiment of the present invention is easy to implement.

[0059] According to an embodiment of the present invention, the asymmetric delay control circuit is applied to a four-phase handshake protocol.

[0060] According to an embodiment of the present invention, assume that the rising edge of a four-phase handshake protocol is the effective trigger edge. In the initial state, the input signal is at a low level, and the output is in a reset state, that is, also at a low level. The data input terminal D of the asynchronous flip-flop is always connected to the high level Vdd. When the rising edge of the input signal arrives, this rising edge is sent to the delayed input terminal CK of the asynchronous flip-flop after passing through the delay unit, and the high level signal of the data input terminal D is transmitted to the output terminal Q, then the input is at a high level at this time.

[0061] Figure 4 Schematically shows a block diagram of an asymmetric delay control device according to an embodiment of the present invention.

[0062] As Figure 4 shown, the asymmetric delay control device 400 includes an asymmetric delay control circuit 410.

[0063] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present utility model. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code, and the above-mentioned module, segment of a program, or portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in various embodiments of the present utility model can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present utility model. In particular, without departing from the spirit and teachings of the present utility model, the features described in various embodiments of the present utility model can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present utility model.

[0064] The embodiments of the present utility model have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present utility model. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present utility model, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present utility model.

Claims

1. An asymmetric delay control circuit, comprising a delay unit and an asynchronous trigger; The asynchronous trigger comprises a reset input terminal, a delay input terminal and an output terminal, the delay unit is connected to the delay input terminal, and the delay unit is used to delay a clock signal input to the delay input terminal; in, When the clock signal input to the reset input terminal is an invalid level, the output terminal outputs the invalid level. When the clock signal input to the reset input terminal is a valid level and it is detected that the clock signal input to the delay input terminal switches from the invalid level to the valid level, the output terminal outputs the valid level.

2. The circuit according to claim 1, wherein The asynchronous trigger also includes a data input terminal, and the data input terminal is used to transfer input data from the data input terminal to the output terminal when the output of the output terminal is at the valid level.

3. The circuit according to claim 2, wherein: The input signal of the data input terminal is at a valid level.

4. The circuit according to claim 1, wherein: When the clock signal input to the reset input terminal is at a valid level and it is not detected that the clock signal input to the delay input terminal switches from the invalid level to the valid level, the output of the output terminal is at the invalid level.

5. The circuit according to any one of claims 1 to 4, wherein: The clock signal is directly input to the reset input terminal, and the clock signal is input to the delay input terminal after being delayed by the delay unit.

6. The circuit according to any one of claims 1 to 4, wherein: The effective level is a high level, and the ineffective level is a low level.

7. The circuit according to any one of claims 1 to 4, wherein: The delay unit and the asynchronous flip-flop are constructed based on elements in a standard cell library.

8. The circuit according to any one of claims 1 to 4, wherein: A duty ratio of the effective level in one clock cycle of the clock signal is greater than 0 and less than 1.

9. The circuit according to any one of claims 1 to 4, wherein: The asymmetric delay control circuit is applied to a four-phase handshake protocol.

10. An asymmetric delay control device, comprising the asymmetric delay control circuit according to any one of claims 1 to 9.

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