Semiconductor device with high voltage resistance and high stability

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a semiconductor device with high voltage resistance and high stability, which comprises a VDMOS device composed of a plurality of VDMOS cells, and each VDMOS cell comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode. The semiconductor epitaxial layer comprises a P well layer, an N well layer, a diffusion layer, a substrate layer and a heavily doped P well layer II; the heavily doped P well layer II is in ohm short circuit with the drain electrode; the P-well layer comprises a lightly doped P-well layer I, a heavily doped P-well layer I, a lightly doped P-well layer II and a lightly doped P-well layer III; the N-well layer comprises a lightly doped N-well layer and a heavily doped N-well layer; the diffusion layer comprises a side edge layer, a bottom doping layer and a middle layer; wherein high-energy impurities are doped in the low doping layer. According to the utility model, the P body region is formed through ion implantation in the substrate layer, and the P body region blocks the formation of a nearest conductive path between the drain electrode and the charge channel, so that the voltage resistance of the semiconductor device can be greatly improved, and the bearing capacity of the grid electrode to peak voltage is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a semiconductor device with high breakdown voltage and high stability. Background Art

[0002] A semiconductor device is an electronic device made of semiconductor materials and is usually used to control the flow of current. Common semiconductor devices include diodes, field-effect transistors (FETs), bipolar junction transistors (BJTs), and integrated circuits (ICs), etc. Semiconductor materials play a key role because they have electrical properties between conductive metals and insulators, allowing them to be controlled by an electric field or current to achieve the functions of electronic devices. Semiconductor devices play an important role in modern electronic technology and are widely used in various fields such as computers, communications, energy, healthcare, and automobiles.

[0003] A prior patent discloses a trench-gate semiconductor power device (publication number CN102723355A), and its technical solution can be summarized as: a trench-gate semiconductor power device, which adds two high-K dielectric regions on the left and right sides of the semiconductor drift region. The two sides of the first semiconductor region in the semiconductor drift region are in contact with two second semiconductor regions, and the two high-K dielectric regions are respectively in contact with the other sides of the two second semiconductor regions. In the technology disclosed in this patent, when the peak voltage of a large wave crest appears in the voltage squeezed between the drain and the gate, the epitaxial layer of the semiconductor is extremely vulnerable to charge breakdown; and in the technology disclosed in this patent, charge cross-diffusion occurs between adjacent cells, which makes the cells with smaller resistance due to error factors have a stronger radiation effect, and the amount of charge passing through them is more, exacerbating the loss of the semiconductor device. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a semiconductor device with high breakdown voltage and high stability, solving the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a semiconductor device with high breakdown voltage and high stability includes a VDMOS device composed of a plurality of VDMOS cells. The VDMOS cell includes a drain, a semiconductor epitaxial layer, a metal source, and a gate;

[0006] The semiconductor epitaxial layer includes a P-well layer, an N-well layer, a diffusion layer, a substrate layer, and a heavily doped P-well layer two; wherein, the heavily doped P-well layer two is ohmically shorted to the drain.

[0007] The P-well layer includes a lightly doped P-well layer one, a heavily doped P-well layer one, a lightly doped P-well layer two, and a lightly doped P-well layer three; the N-well layer includes a lightly doped N-well layer and a heavily doped N-well layer.

[0008] The diffusion layer includes a side layer, a low-doped layer, and an intermediate layer; wherein, high-energy impurities are doped inside the low-doped layer.

[0009] Furthermore, a gate oxide layer is deposited between the surface of the gate, the metal source electrode, and the semiconductor epitaxial layer.

[0010] Furthermore, the heavily doped P-well layer one, the lightly doped P-well layer two, and the lightly doped P-well layer three between adjacent VDMOS cells are integrated as a whole.

[0011] Furthermore, when a positive gate voltage is applied to the gate, a reverse depletion layer is formed inside the JFET region of the diffusion layer, and the JFET region is located between two adjacent P-well layers of the diffusion layer.

[0012] Furthermore, when the voltage applied to the gate is zero, free carriers exist in the channel formed in the P-well layer to form a conduction path.

[0013] Furthermore, only the heavily doped N-well layer in the N-well layer is ohmically shorted to the metal source electrode, and the heavily doped N-well layer and the lightly doped N-well layer are divided into upper and lower layers.

[0014] Furthermore, the side layer, the low-doped layer, and the intermediate layer are ion-implanted with low-concentration phosphorus ions.

[0015] Furthermore, the heavily doped P-well layer one and the heavily doped P-well layer two are ion-implanted with high-concentration boron ions; the lightly doped P-well layer two and the lightly doped P-well layer three are ion-implanted with high-concentration boron ions.

[0016] The beneficial effects of a semiconductor device with high breakdown voltage and high stability of the present utility model are as follows:

[0017] 1. By ion-implanting a P-body region in the substrate layer in the present utility model, the P-body region blocks the formation of the shortest conduction path between the drain and the charge channel, which can greatly increase the breakdown voltage of the semiconductor device and improve the gate's tolerance to peak voltage.

[0018] 2. By implanting a lower concentration of phosphorus element between adjacent VDMOS cells in the present utility model to form a low-doped layer, the low-doped layer can concentrate charges and form an effective flow path, which can greatly reduce the on-resistance of the semiconductor device and improve the service life of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following further describes the present utility model in detail with reference to the drawings and specific implementation methods.

[0020] Figure 1 It is a schematic diagram of a semiconductor device;

[0021] Figure 2 This is a schematic diagram of the dual-cell juxtaposed structure of the present utility model.

[0022] In the figure: 1. Drain; 2. Metal source; 3. Gate oxide layer; 4. Gate; 5. Lightly doped P-well layer 1; 6. Heavily doped P-well layer 1; 7. Lightly doped P-well layer 2; 8. Lightly doped P-well layer 3; 9. Diffusion layer; 10. Lightly doped N-well layer; 11. Heavily doped N-well layer; 12. Substrate layer; 13. Heavily doped P-well layer 2; 901. Side layer; 902. Low-doped layer; 903. Intermediate layer; 904. High-energy impurity. Detailed implementation manners

[0023] The present utility model will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0024] As Figure 1-2 shown, according to one aspect of the present utility model, there is provided a semiconductor device with high breakdown voltage and high stability, including a VDMOS device composed of a plurality of VDMOS cells. The VDMOS cell includes a drain 1, a semiconductor epitaxial layer, a metal source 2, and a gate 4. The semiconductor epitaxial layer includes a P-well layer, an N-well layer, a diffusion layer 9, a substrate layer 12, and a heavily doped P-well layer 2 13. Among them, the heavily doped P-well layer 2 13 is ohmically shorted to the drain 1, and the heavily doped P-well layer 2 13 is formed by ion implantation in the substrate layer 12. The heavily doped P-well layer 2 13 can block the formation of the shortest conduction path between the drain 1 and the charge channel, thereby greatly increasing the breakdown voltage of the semiconductor device.

[0025] The P-well layer includes a lightly doped P-well layer 1 5, a heavily doped P-well layer 1 6, a lightly doped P-well layer 2 7, and a lightly doped P-well layer 3 8. The N-well layer includes a lightly doped N-well layer 10 and a heavily doped N-well layer 11. The diffusion layer 9 includes a side layer 901, a low-doped layer 902, and an intermediate layer 903. Among them, high-energy impurities 904 are doped inside the low-doped layer 902, and a lower concentration of phosphorus element is implanted between adjacent VDMOS cells to form the low-doped layer 902. The low-doped layer 902 can concentrate charges and form an effective flow path, thereby greatly reducing the on-resistance of the semiconductor device and improving the service life of the semiconductor device.

[0026] In this embodiment, the doping concentration of the side layer 901 is 4.6 - 6×10 16 mol / cm 3 ;

[0027] The doping concentration of the low-doped layer 902 is 0.3 - 1×10 16 mol / cm 3 ;

[0028] The doping concentration of the intermediate layer 903 is 7.5 - 9×10 16 mol / cm 3 .

[0029] The doping concentrations of both the heavily doped P-well layer 1 6 and the heavily doped P-well layer 2 13 are 3 - 6×10 17 mol / cm 3 ;

[0030] The doping concentration of the lightly doped P-well layer 2 7 is 4.3 - 6.8×10 16 mol / cm 3 ;

[0031] The doping concentration of the lightly doped P-well layer 3 8 is 2.7 - 3.1×10 18 mol / cm 3 .

[0032] In this embodiment, a gate oxide layer 3 is deposited between the surface of the gate 4, the metal source electrode 2, and the semiconductor epitaxial layer. The gate oxide layer 3 can ensure the formation of the gate electric field and isolate the direct passage of charges through the diffusion layer 9 into the interior of the gate 4. The heavily doped P-well layer 1 6, the lightly doped P-well layer 2 7, and the lightly doped P-well layer 3 8 between adjacent VDMOS cells are integrated as a whole. This integrated design reduces the manufacturing cost of semiconductor devices.

[0033] In this embodiment, when a positive gate voltage is applied to the gate 4, a reverse depletion layer is formed inside the JFET region of its diffusion layer 9. The JFET region is located between two adjacent P-well layers of the diffusion layer 9. When the voltage applied to the gate 4 is zero, free carriers exist in the channel formed in the P-well layer to form a conduction path. And when the reverse depletion layer expands to a certain extent, the channel region is truncated and the current cannot pass through, reaching the cut-off state; by adjusting the gate voltage, the expansion degree of the reverse depletion layer can be controlled, and further the charge density in the channel and the magnitude of the current can be controlled to achieve current control of the MOSFET device.

[0034] In this embodiment, only the heavily doped N-well layer 11 in the N-well layer is ohmically shorted to the metal source electrode 2. The heavily doped N-well layer 11 and the lightly doped N-well layer 10 are divided into upper and lower layers. Only the heavily doped P-well layer 1 6 in the P-well layer is ohmically shorted to the metal source electrode 2. The heavily doped P-well layer 2 13 is formed by ion implantation of boron elements and is located directly below the gate 4. Dividing the N-well layer into two layers with different doping ion concentrations can effectively reduce the interference of the gate electric field on the charges inside the N-well layer; and dividing the P-well layer into multiple layers can also reduce the influence of the gate electric field and avoid the accumulation and parasitism of charges inside the P-well layer.

[0035] Certainly, the above description is not a limitation to the present utility model, nor is the present utility model limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present utility model also fall within the protection scope of the present utility model.

Claims

1. A semiconductor device with high withstand voltage and high stability, characterized in that: A VDMOS device is provided which is composed of a plurality of VDMOS cells, wherein the VDMOS cells include a drain (1), a semiconductor epitaxial layer, a metal source (2) and a gate (4); The semiconductor epitaxial layer comprises a P-well layer, an N-well layer, a diffusion layer (9), a substrate layer (12) and a heavily doped P-well layer 2 (13); wherein the heavily doped P-well layer 2 (13) is ohmically short-circuited with the drain electrode (1); The P well layer includes a lightly doped P well layer 1 (5), a heavily doped P well layer 1 (6), a lightly doped P well layer 2 (7) and a lightly doped P well layer 3 (8); the N well layer includes a lightly doped N well layer (10) and a heavily doped N well layer (11); The diffusion layer (9) comprises a side layer (901), a low-doping layer (902) and an intermediate layer (903); wherein the low-doping layer (902) is doped with high-energy impurities (904).

2. The semiconductor device with high withstand voltage and high stability according to claim 1, characterized in that: A gate oxide layer (3) is deposited between the surface of the gate electrode (4), the metal source electrode (2) and the semiconductor epitaxial layer.

3. The semiconductor device with high withstand voltage and high stability according to claim 1, characterized in that: The heavily doped P-well layer 1 (6), the lightly doped P-well layer 2 (7) and the lightly doped P-well layer 3 (8) between adjacent VDMOS cells are integrated as a whole.

4. The semiconductor device with high withstand voltage and high stability according to claim 1, characterized in that: When a positive gate voltage is applied to the gate (4), a reverse depletion layer is formed inside the JFET region of the diffusion layer (9), and the JFET region is located between two adjacent P-well layers of the diffusion layer (9).

5. The semiconductor device with high withstand voltage and high stability according to claim 4, characterized in that: When the voltage applied by the gate (4) is zero, free carriers exist in the channel formed in the P-well layer to form a conductive path.

6. The semiconductor device with high withstand voltage and high stability according to claim 1, characterized in that: Among the N-well layers, only the heavily doped N-well layer (11) is ohmically short-circuited with the metal source electrode (2), wherein the heavily doped N-well layer (11) and the lightly doped N-well layer (10) are divided into two layers, an upper layer and a lower layer.

7. The semiconductor device with high withstand voltage and high stability according to claim 1, characterized in that: Only the heavily doped P-well layer 1 (6) in the P-well layer is ohmically short-circuited with the metal source electrode (2).

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